The issue of copying values or references has historically been studied for managing memory objects, especially in distributed systems. In this paper, we explore a new topic on copying values v.s. references, for memory page compaction on virtualized systems. Memory page compaction moves target physical pages to a contiguous memory region at the operating system kernel level to create huge pages. Memory virtualization provides an opportunity to perform memory page compaction by copying the references of the physical pages. That is, instead of copying pages' values, we can move guest physical pages by changing the mappings of guest-physical to machine-physical pages. The goal of this paper is a quantitative comparison between value- and reference-based memory page compaction. To do so, we developed a software mechanism that achieves memory page compaction by appropriately updating the references of guest-physical pages. We prototyped the mechanism on Linux 4.19.29 and the experimental results show that the prototype's page compaction is up to 78% faster and achieves up to 17% higher performance on the memory-intensive real-world applications as compared to the default value-copy compaction scheme.

This letter provides a direct construction of binary even-length Z-complementary pairs. To date, the maximum zero correlation zone ratio of Type-I Z-complementary pairs has reached 6/7, but no direct construction of Z-complementary pairs can achieve the zero correlation zone ratio of 6/7. In this letter, based on Boolean function, we give a direct construction of binary even-length Z-complementary pairs with zero correlation zone ratio 6/7. The length of constructed Z-complementary pairs is 2m+3 + 2m + 2+2m+1 and the width of zero correlation zone is 2m+3 + 2m+2.

End-to-end loss and delay are both fundamental metrics in network performance evaluation, and accurate measurements for these end-to-end metrics are one of the keys to keeping delay/loss-sensitive applications (e.g., audio/video conferencing, IP telephony, or telesurgery) comfortable on networks. In our previous work [1], we proposed a parallel flow monitoring method that can provide accurate active measurements of end-to-end delay. In this method, delay samples of a target flow increase by utilizing the observation results of other flows sharing the source/destination with the target flow. In this paper, to improve accuracy of loss measurements, we propose a loss measurement method by extending our delay measurement method. Additionally, we improve the loss measurement method so that it enables to fully utilize information of all flows including flows with different source and destination. We evaluate the proposed method through theoretical and simulation analyses. The evaluations show that the accuracy of the proposed method is bounded by theoretical upper/lower bounds, and it is confirmed that it reduces the error of loss rate estimations by 57.5% on average.

The multi-FPGA system known as, the Flow-in-Cloud (FiC) system, is composed of mid-range FPGAs that are directly interconnected by high-speed serial links. FiC is currently being developed as a server for multi-access edge computing (MEC), which is one of the core technologies of 5G. Because the applications of MEC are sometimes timing-critical, a static time division multiplexing (STDM) network has been used on FiC. However, the STDM network exhibits the disadvantage of decreasing link utilization, especially under light traffic. To solve this problem, we propose a hybrid router that combines packet switching for low-priority communication and STDM for high-priority communication. In our hybrid network, the packet switching uses slots that are unused by the STDM; therefore, best-effort communication by packet switching and QoS guarantee communication by the STDM can be used simultaneously. Furthermore, to improve each link utilization under a low network traffic load, we propose a dynamic communication switching algorithm. In our algorithm, each router monitors the network load metrics, and according to the metrics, timing-critical tasks select the STDM according to the metrics only when congestion occurs. This can achieve both QoS guarantee and efficient utilization of each link with a small resource overhead. In our evaluation, the dynamic algorithm was up to 24.6% faster on the execution time with a high network load compared to the packet switching on a real multi-FPGA system with 24 boards.

This paper considers tracking of a non-cooperative emitter based on a single sensor. To this end, the direct target motion analysis (DTMA) approach, where the target state is straightforwardly achieved from the received signal, is exploited. In order to achieve observability, the sensor has to perform a maneuver relative to the emitter. By suitably building an approximated likelihood function, the unscented Kalman filter (UKF), which is able to work under high nonlinearity of the measurement model, is adopted to recursively estimate the target state. Besides, the posterior Cramér-Rao bound (PCRB) of DTMA, which can be used as performance benchmark, is also achieved. The effectiveness of proposed method is verified via simulation experiments.

This paper proposes a novel random access identifier (RAID)-linked receiver beamforming method for time division duplex (TDD)-based random access. When the number of receiver antennas at the base station is large in a massive multiple-input multiple-output (MIMO) scenario, the channel estimation accuracy per receiver antenna at the base station receiver is degraded due to the limited received signal power per antenna from the user terminal. This results in degradation in the receiver beamforming (BF) or antenna diversity combining and active RAID detection. The purpose of the proposed method is to achieve accurate active RAID detection and channel estimation with a reasonable level of computational complexity at the base station receiver. In the proposed method, a unique receiver BF vector applied at the base station is linked to each of the M RAIDs prepared by the system. The user terminal selects an appropriate pair comprising a receiver BF vector and a RAID in advance based on the channel estimation results in the downlink assuming channel reciprocity in a TDD system. Therefore, per-receiver antenna channel estimation for receiver BF is not necessary in the proposed method. Furthermore, in order to utilize fully the knowledge of the channel at the user transmitter, we propose applying transmitter filtering (TF) to the proposed method for effective channel shortening in order to increase the orthogonal preambles for active RAID detection and channel estimation prepared for each RAID. Computer simulation results show that the proposed method greatly improves the accuracy of active RAID detection and channel estimation. This results in lower error rates than that for the conventional method performing channel estimation at each antenna in a massive MIMO environment.

At this stage, research in the field of Few-shot image classification (FSC) has made good progress, but there are still many difficulties in the field of Few-shot object detection (FSOD). Almost all of the current FSOD methods face catastrophic forgetting problems, which are manifested in that the accuracy of base class recognition will drop seriously when acquiring the ability to recognize Novel classes. And for many methods, the accuracy of the model will fall back as the class increases. To address this problem we propose a new memory-based method called Memorable Faster R-CNN (MemFRCN), which makes the model remember the categories it has already seen. Specifically, we propose a new tow-stage object detector consisting of a memory-based classifier (MemCla), a fully connected neural network classifier (FCC) and an adaptive fusion block (AdFus). The former stores the embedding vector of each category as memory, which enables the model to have memory capabilities to avoid catastrophic forgetting events. The final part fuses the outputs of FCC and MemCla, which can automatically adjust the fusion method of the model when the number of samples increases so that the model can achieve better performance under various conditions. Our method can perform well on unseen classes while maintaining the detection accuracy of seen classes. Experimental results demonstrate that our method outperforms other current methods on multiple benchmarks.

Various types of indices for estimating functional connectivity have been developed over the years that have introduced effective approaches to discovering complex neural networks in the brain. Two significant examples are the phase lag index (PLI) and transfer entropy (TE). Both indices have specific benefits; PLI, defined using instantaneous phase dynamics, achieves high spatiotemporal resolution, whereas transfer entropy (TE), defined using information flow, reveals directed network characteristics. However, the relationship between these indices remains unclear. In this study, we hypothesize that there exists a complementary relationship between PLI and TE to discover new aspects of functional connectivity that cannot be detected using either PLI or TE. To validate this hypothesis, we evaluated the synchronization in a coupled Rössler model using PLI and TE. Consequently, we proved the existence of non-linear relationships between PLI and TE. Both indexes exhibit a specific trend that demonstrates a linear relationship in the region of small TE values. However, above a specific TE value, PLI converges to a constant irrespective of the TE value. In addition to this relational difference in synchronization, there is another characteristic difference between these indices. Moreover, by virtue of its finer temporal resolution, PLI can capture the temporal variability of the degree of synchronization, which is called dynamical functional connectivity. TE lacks this temporal characteristic because it requires a longer evaluation period in this estimation process. Therefore, combining the advantages of both indices might contribute to revealing complex spatiotemporal functional connectivity in brain activity.

A path loss prediction formula for IoT (Internet of Things) wireless communication close to ceiling beams in the 920MHz band is presented. In first step of our investigation, we conduct simulations using the FDTD (Finite Difference Time Domain) method and propagation tests close to a beam on the ceiling of a concrete building. In the second step, we derive a path loss prediction formula from the simulation results by using the FDTD method, by dividing into three regions of LoS (line-of-sight) situation, situation in the vicinity of the beam, and NLoS (non-line-of-sight) situation, depending on the positional relationship between the beam and transmitter (Tx) and receiver (Rx) antennas. For each condition, the prediction formula is expressed by a relatively simple form as a function of height of the antennas with respect to the beam bottom. Thus, the prediction formula is very useful for the wireless site planning for the IoT wireless devices set close to concrete beam ceiling.

SiC-MOSFETs are being increasingly implemented in power electronics systems as low-loss, fast switching devices. Despite the advantages of an SiC-MOSFET, its large dv/dt or di/dt has fear of electromagnetic interference (EMI) noise. This paper proposes and demonstrates a simple and robust gate driver that can suppress ringing oscillation and surge voltage induced by the turn-off of the SiC-MOSFET body diode. The proposed gate driver utilizes the channel leakage current methodology (CLC) to enhance the damping effect by elevating the gate-source voltage (VGS) and inducing the channel leakage current in the device. The gate driver can self-adjust the timing of initiating CLC operation, which avoids an increase in switching loss. Additionally, the output voltage of the VGS elevation circuit does not need to be actively controlled in accordance with the operating conditions. Thus, the circuit topology is simple, and ringing oscillation can be easily attenuated with fixed circuit parameters regardless of operating conditions, minimizing the increase in switching loss. The effectiveness and versatility of proposed gate driver were experimentally validated for a wide range of operating conditions by double and single pulse switching tests.

Multilayer perceptron (MLP) is a basic neural network model that is used in practical industrial applications, such as network intrusion detection (NID) systems. It is also used as a building block in newer models, such as gMLP. Currently, there is a demand for fast training in NID and other areas. However, in training with numerous GPUs, the problems of power consumption and long training times arise. Many of the latest deep neural network (DNN) models and MLPs are trained using a backpropagation algorithm which transmits an error gradient from the output layer to the input layer such that in the sequential computation, the next input cannot be processed until the weights of all layers are updated from the last layer. This is known as backward locking. In this study, a weight parameter update mechanism is proposed with time delays that can accommodate the weight update delay to allow simultaneous forward and backward computation. To this end, a one-dimensional systolic array structure was designed on a Xilinx U50 Alveo FPGA card in which each layer of the MLP is assigned to a processing element (PE). The time-delay backpropagation algorithm executes all layers in parallel, and transfers data between layers in a pipeline. Compared to the Intel Core i9 CPU and NVIDIA RTX 3090 GPU, it is 3 times faster than the CPU and 2.5 times faster than the GPU. The processing speed per power consumption is 11.5 times better than that of the CPU and 21.4 times better than that of the GPU. From these results, it is concluded that a training accelerator on an FPGA can achieve high speed and energy efficiency.

This study presents a selective data-compression interconnection network to boost its performance. Data compression virtually increases the effective network bandwidth. One drawback of data compression is a long latency to perform (de-)compression operation at a compute node. In terms of the communication latency, we explore the trade-off between the compression latency overhead and the reduced injection latency by shortening the packet length by compression algorithms. As a result, we present to selectively apply a compression technique to a packet. We perform a compression operation to long packets and it is also taken when network congestion is detected at a source compute node. Through a cycle-accurate network simulation, the selective compression method using the above compression algorithms improves by up to 39% the network throughput with a moderate increase in the communication latency of short packets.

In this paper, we propose a multi-domain learning model for action recognition. The proposed method inserts domain-specific adapters between layers of domain-independent layers of a backbone network. Unlike a multi-head network that switches classification heads only, our model switches not only the heads, but also the adapters for facilitating to learn feature representations universal to multiple domains. Unlike prior works, the proposed method is model-agnostic and doesn't assume model structures unlike prior works. Experimental results on three popular action recognition datasets (HMDB51, UCF101, and Kinetics-400) demonstrate that the proposed method is more effective than a multi-head architecture and more efficient than separately training models for each domain.

With the development of blockchain technology, the automatic generation of smart contract has become a hot research topic. The existing smart contract automatic generation technology still has improvement spaces in complex process, third-party specialized tools required, specific the compatibility of code and running environment. In this paper, we propose an automatic smart contract generation method, which is domain-oriented and configuration-based. It is designed and implemented with the application scenarios of government service. The process of configuration, public state database definition, code generation and formal verification are included. In the Hyperledger Fabric environment, the applicability of the generated smart contract code is verified. Furthermore, its quality and security are formally verified with the help of third-party testing tools. The experimental results show that the quality and security of the generated smart contract code meet the expect standards. The automatic smart contract generation will “elegantly” be applied on the work of anti-disclosure, privacy protection, and prophecy processing in government service. To effectively enable develop “programmable government”.

Fast switching speed, low power consumption, and good stability are some of the important properties of spin transfer torque assisted voltage controlled magnetic anisotropy magnetic tunnel junction (STT-assisted VCMA-MTJ) which makes the non-volatile full adder (NV-FA) based on it attractive for Internet of Things. However, the effects of process variations on the performances of STT-assisted VCMA-MTJ and NV-FA will be more and more obvious with the downscaling of STT-assisted VCMA-MTJ and the improvement of chip integration. In this paper, a more accurate electrical model of STT-assisted VCMA-MTJ is established on the basis of the magnetization dynamics and the process variations in film growth process and etching process. In particular, the write voltage is reduced to 0.7 V as the film thickness is reduced to 0.9 nm. The effects of free layer thickness variation (γtf) and oxide layer thickness variation (γtox) on the state switching as well as the effect of tunnel magnetoresistance ratio variation (β) on the sensing margin (SM) are studied in detail. Considering that the above process variations follow Gaussian distribution, Monte Carlo simulation is used to study the effects of the process variations on the writing and output operations of NV-FA. The result shows that the state of STT-assisted VCMA-MTJ can be switched under -0.3%≤γtf≤6% or -23%≤γtox≤0.2%. SM is reduced by 16.0% with β increases from 0 to 30%. The error rates of writing ‘0’ in the NV-FA can be reduced by increasing Vb1 or increasing positive Vb2. The error rates of writing ‘1’ can be reduced by increasing Vb1 or decreasing negative Vb2. The reduction of the output error rates can be realized effectively by increasing the driving voltage (Vdd).

This paper shows structural optimal design of optical waveguide components utilizing an efficient 3D frequency-domain and 2D time-domain beam propagation method (BPM) with an alternating direction implicit (ADI) scheme. Usual optimal design procedure is based on iteration of numerical simulation, and total computational cost of the optimal design mainly depends on the efficiency of numerical analysis method. Since the system matrices are tridiagonal in the ADI-based BPM, efficient analysis and optimal design are available. Shape and topology optimal design shown in this paper is based on optimization of density distribution and sensitivity analysis to the density parameters. Computational methods of the sensitivity are shown in the case of using the 3D semi-vectorial and 2D time-domain BPM based on ADI scheme. The validity of this design approach is shown by design of optical waveguide components: mode converters, and a polarization beam splitter.

In order to increase communication capacity, the use of millimeter-wave and terahertz-wave bands are being actively explored. Non-radiative dielectric waveguide known as NRD guide is one of promising platform of millimeter-wave integrated circuits thanks to its non-radiative and low loss nature. In order to develop millimeter wave circuits with various functions, various circuit components have to be efficiently designed to meet requirements from application side. In this paper, for efficient design of NRD guide devices, we develop a topology optimal design technique based on function-expansion-method which can express arbitrary structure with arbitrary geometric topology. In the present approach, recently developed two-dimensional full-vectorial finite element method (2D-FVFEM) for NRD guide devices is employed to improve computational efficiency and several evolutionary approaches, which do not require appropriate initial structure depending on a given design problem, are used to optimize design variables, thus, NRD guide devices having desired functions are efficiently obtained without requiring designer's special knowledge.

This paper introduces the working principle of continuous wave (CW) illuminator and selects the test space by developing the wave impedance selection algorithm for the CW illuminator. For the vertical polarization and the horizontal polarization of CW illuminator, the law of wave impedance distribution after loading is analyzed and the influence of loading distribution on test space selection is studied. The selection principle of wave impedance based on incident field or total field at the monitoring point is analyzed.

In [2], Choi et al. proposed an identity-based password-authenticated key exchange (iPAKE) protocol using the Boneh-Franklin IBE scheme, and its generic construction (UKAM-PiE) that was standardized in ISO/IEC 11770-4/AMD 1. In this paper, we show that the iPAKE and UKAM-PiE protocols are insecure against passive/active attacks by a malicious PKG (Private Key Generator) where the malicious PKG can find out all clients' passwords by just eavesdropping on the communications, and the PKG can share a session key with any client by impersonating the server. Then, we propose a strengthened PAKE (for short, SPAIBE) protocol with IBE, which prevents such a malicious PKG's passive/active attacks. Also, we formally prove the security of the SPAIBE protocol in the random oracle model and compare relevant PAKE protocols in terms of efficiency, number of passes, and security against a malicious PKG.

The Euclidean projection operation is the most complex and time-consuming of the alternating direction method of multipliers (ADMM) decoding algorithms, resulting in a large number of resources when deployed on hardware platforms. We propose a simplified line segment projection algorithm (SLSA) and present the hardware design and the quantization scheme of the SLSA. In simulation results, the proposed SLSA module has a better performance than the original algorithm with the same fixed bitwidths due to the centrosymmetric structure of SLSA. Furthermore, the proposed SLSA module with a simpler structure without hypercube projection can reduce time consuming by up to 72.2% and reduce hardware resource usage by more than 87% compared to other Euclidean projection modules in the experiments.