The multiple registration schemes (MRSs) proposed here are classified into 3 cases by combining five registration schemes which are power up registration scheme (PURS), power down registration scheme (PDRS), zone based registration scheme (ZBRS), distance based registration scheme (DBRS), and implicit registration scheme (IRS) as follows: the first is MRS1 which covers PURS, PDRS, and ZBRS; the second is MRS2 which covers PURS, PDRS, and DBRS; the third is MRS3 which covers PURS, PDRS, IRS, and DBRS. The three proposed schemes are compared each other by analyzing their combined signaling traffic of paging and registration with considering various parameters of a mobile station behavior (unencumbered call duration, power up and down rate, velocity, etc.). Also, we derive allowable location areas from which the optimal location area is obtained. Numerical results show that MRS3 yields better performance than ZBRS, DBRS, MRS1, and MRS2 in most cases of a mobile station behavior, and it has an advantage of distributing the load of signaling traffic into every cell, which is important in personal communication system.

The number of DRAMs that have adopted hierarchical word-line architecture has increased as developed DRAM memory capacity has increased to more than 64 Mb. Use of the architecture enhances many kinds of DRAM performances, such as access time and fabrication process margin. However, the architecture does cause some problems. This paper describes some kinds of hierarchical word-line circuitries that have been proposed. It also describes a partial subarray activation scheme that is combined with hierarchical word-line and data-line architectures and discusses their potential and required specifications for future multi-giga bit DRAMs.

In this paper, we consider the following node-to-set disjoint paths problem: given a node s and a set T = {t1,...,tk} of k nodes in a k-connected graph G, find k node-disjoint paths s ti, 1 i k. We give an O(n2) time algorithm for the node-to-set disjoint paths problem in n-dimensional star graphs Gn which are (n - 1)-connected. The algorithm finds the n - 1 node-disjoint paths of length at most d(Gn) + 1 for n 4,6 and at most d(Gn) + 2 for n = 4,6, where d(Gn) = 3(n-1)/2 is the diameter of Gn. d(Gn) + 1 and d(Gn) + 2 are also the lower bounds on the length of the paths for the above problem in Gn for n 4,6 and n = 4,6, respectively.

We propose low Rayleigh scattering Na2O-MgO-SiO2 (NMS) glass as a candidate material for low-loss optical fibers. This glass exhibits Rayleigh scattering which is only 0.4 times that of silica glass, and a theoretical evaluation suggests that it is dominated by density fluctuation. An investigation of the optical properties of NMS glass reveals that a minimum loss of 0.06 dB/km is expected at a wavelength of 1.6 µm and that the zero-material dispersion wavelength is found in the 1.5 µm band. To establish the waveguide structure, we evaluated the feasibility of using F-doped NMS (NMS-F) glass as a cladding layer for an NMS core and found that it is suitable because it exhibits low relative scattering (e.g. 0.7) and is versatile in terms of viscosity matching. We also describe an attempt to draw optical fibers using the double crucible technique.

A new numerical technique, termed the method of matrix-order reduction (MMOR), is developed for handling electromagnetic problems in this paper, in which the matrix equation resulted from a method-of-moments analysis is converted either to an eigenvalue equation or to another matrix equation with the matrix order in both cases being much reduced, and also, the accuracy of solution obtained by solving either of above equations is improved by means of a newly proposed generalized Jacobian iteration. As a result, this technique enjoys the advantages of less computational expenses and a relatively good solution accuracy as well. To testify this new technique, a number of wire antennas are examined and the calculated results are compared with those obtained by using the method of moments.

A hierarchical fault tracing method for VLSIs with bi-directional busses from CAD layout data in the CAD-linked electron beam test system is described. When fault tracing reaches at a cell connected to a bi-directional bus, our method is able to judge the direction of the signal flow, input or output, by using waveforms acquired by an EB tester, in a consistent manner independently of circuit functions as with a previously proposed tracing method for circuits without bi-directional busses.

The quality of ELTRAN wafers has been improved by pre-injection in epitaxial growth, surface treatment just before bonding, high temperature annealing at bonding, high selective etching and hydrogen annealing. The pre-injection reduces defects. The surface treatment eliminates edge-voids. The high temperature bonding dramatically reduces voids all over the wafer. Hydrogen annealing is very effective for surface flattening and boron out-diffusion. In particular, the edge-void elimination by the surface treatment just before bonding is greatly effective for enlarging the SOI area and reduces the edge exclusion down to only two mm. The gate oxide integrity is well evaluated. This process promises high yield and through-put, because each of the steps can be independently optimized.

Let L be any class of languages, L' be a class of languages which is closed under λ-free homomorphisms, and Σ be any alphabet. In this paper, we show that if the following statement (1) holds, then the statement (2) holds. (1) For any language L in L over Σ, there exist an alphabet of k pairs of matching parentheses Xk, Dyck reduction Red over Xk, and a language L1 in L' over ΣXk such that L=Red(L1)Σ*. (2) For any language L in L over Σ, there exist an alphabet Γ including Σ, a homomorphism h : Γ*Σ*, a Dyck language D over Γ, and a language L2 in L' over Γ such that L=h(DL2). We also give an application of this result.

The applicability of a boundary matching technique is presented for reconstructing the refractive-index profile of a circularly symmetric cylinder from the measurement of the scattered wave when the cylinder is illuminated by an H-polarized plane wave. The algorithm of reconstruction is based on an iterative procedure of matching the scattered wave calculated from a certain refractive-index distribution with the measured scattered-wave. The limits of reconstruction for strongly inhomogeneous lossless and lossy cylinders are numerically shown through computer simulations under noisy environment, and are compared with those in the E-wave case.

Many different edge detectors have been proposed. Most of them output the edge intensity and the edge orientation as edge features. In this paper we state necessity of a measure which can discriminate a clear edge with small edge height from a noisy edge with large edge height. To find such a measure as an edge feature, we analyze variances within a window around the edge and propose an edge-feature extractor based on this analysis. Then it is noticed that the traditional edge intensity can be considered as two elements: edge height and edge reliability. In multiple edge cases, the condition is clarified for calculating accurate edge locations by analyzing the edge-height function. From this analysis we suggest a method for determining edge points by thresholding edge height. Our detector is compared to Canny's detector both in synthetic models and in a real image and it is demonstrated that our method produces better results in edge locations than Canny's. We also show that our method can detect edges with low edge height and high edge reliability.

An overview of known completion-detection methods is given and their advantages and drawbacks are briefly discussed. A relatively new class of single-rail completion-detection techniques is considered in more detail and dimulation results based on adder implementations are presented. A variant of a single-rail technique, which has the advantage of glitch-suppression and robust operation, is introduced. Simulation results are provided, based on a physical layout of the circuit with extracted parasitics.

A leaky-bucket-with-gate algorithm is proposed to control connection-setup congestion in telecommunication networks providing multimedia services, in place of the call-gapping algorithm used in telephone networks. Multimedia services may use more than one connection simultaneously, while standard telephone services use only one connection at a time. A set of connections used to construct a multimedia service is called a correlated connection group, and the setup requests of such a group form correlated request group. A correlated request group is assumed to be accepted into the network only when all the connection-setup requests for the group are accepted. In this paper, the proposed leaky-bucket-with-gate algorithm, a pure leaky-bucket algorithm, and a call-gapping algorithm are evaluated by simulating traffic with a mix of correlated and uncorrelated connection-setup requests, which models setup requests for video conferencing and telephone services. The simulation results show that the proposed algorithm accepts correlated request groups more efficiently than the pure leaky-bucket and call-gapping algorithms under the simulated traffic conditions, except when the interarrival time in a correlated request group is longer than the acceptance interval. We also present queueing analysis for determining the control parameters in the proposed algorithm. Implementation of this algorithm will facilitate the handling of both setup request traffic for correlated connection groups and for uncorrelated connections in multimedia networks.

We are working on an algorithm to optimize the logic circuits that can be realized on the super fine-grain parallel processing architecture. As a part of this work, we have developed an inverter reduction algorithm. This algorithm is based on modeling logic circuits as dynamical systems. We implement the algorithm in the PARTHENON system, which is the high level synthesis system developed in NTT's laboratories, and evaluate it using ISCAS85 benchmarks. We also compare the results with both the existing algorithm of PARTHENON and the algorithm of Jain and Bryant.

Signal Transition Graphs (STG's) are Petri nets, which were introduced to represent a behavior of asynchronous circuits. To derive logic functions from an STG, the reachability graph should be constructed. In the verification of STG's some method based on an Occurrence net (OCN) and its prefix, called an unfolding, has been proposed. OCN's can represent both causality and concurrency between two nodes by net structure. In this paper, we propose a method to derive a logic function by generating sub state space of a given STG using the structural properties of OCN.

In the proposed architecture, switching system hardware resources are allocated at the equipment level rather than at the component level of LSI chips. Equipment using these resources can thus be shared between independent systems. The efficiency of system development is improved by using structural elements called functional blocks (FBs). The hardware in each FB consists of a shared part (amicroprocessor, its peripheral circuitry, and memory) and a dedicated part that implements the specific functions of the FB. Firmware loaded into the microprocessor consists of a shared part and a dedicated part that corresponds to the hardware parts. Each FB also has its own built-in autonomous testing function to test the reliability of that FB and has its own identification function. By combining these FBs, this approach can flexibly cope with various switching system configurations for plain old telephone service (POTS), integrated services digital network (ISDN), and broad-band ISDN (B-ISDN). Tests using several types of FBs showed that the shared hardware and firmware parts of an FB can be shared between blocks. An architecture based on FBs results in a platform that can handle the hardware for various systems, making it easy to construct new switching systems.

This paper deals with minimization of ESOPs (exclusive-or sum-of-products) which represent symmetric functions. Se propose an efficient simplification algorithm for symmetric functions, which guarantees the minimality for some subclass of symmetric functions, and present the minimum ESOPs for all 6-variable symmetric functions.

In the data path circuits of asynchronous systems, logical faults may first manifest as undetectable, transient wrong codewords, in spite of encoding the inputs and the outputs and proper organization which enables the faults to be propagated to the primary outputs in the form of non-codewords. Due to this, the conventional methods of concurrent error detection (CED) using the logic (voltage) monitoring is not effective. In this paper, we suggest a mixed-signal approach to achieve CED for a class of asynchronous circuits, known as self-timed circuits. First, we show that it is impossible to guarantee the CED using logic monitoring of the primary outputs in spite of proper encoding and organization of self-timed circuits. Then, we discuss different manifestations of single stuck-at faults occurring during normal operation in these circuits. Finally, we present the feasibility of achieving CED using a built-in current sensor (BICS) along with encoding techniques.

In this paper, a novel completion prediction adder is proposed. The basic concept is to predict the completion of an adder by investigating the inputs and generate completion signal for synchronization according to the completion prediction signal. This scheme greatly enhances the performance of an adder in both aspects of delay and hardware cost. Furthermore, the relative performance enhancement compared with representative synchronous adders increases as the word length of an adder becomes longer. For example, the delay-hardware product of SCPA for a 64-bit adder is 45.1% and 42.7% of those of binary carry look-ahead adder (BCLA) and binary tree carry look-ahead adder (BTCLA), respectively.

This letter presents a realization of active current-mode resonator with complex coefficients using CCIIs. The resonator can be used for cascade or leapfrog configuration of high-order bandpass filters with complex coefficients. For realizing the resonators, only the grounded capacitors and the grounded resistors as passive elements are required, therfore the resonator is suitable for the integrated circuit realization. The letter shows that the response error of the proposed circuit caused by nonideality of active components is more easily compensated than that of voltage-mode counterpart. Experimental result is used for verifying the feasibility of the proposed resonator.

Photovoltaic devices capable of generating more than 200 volts with an area of 1 cm2 have been developed for directly driving microactuators such as piezoelectric or electrostatic actuators. The micro-devices interconnect 285 micro cells (unit cell size: about 0.5 mm 2.0 mm) in series, and have an open circuit voltage (Voc) of 207 volts, a short circuit current (Isc) of 36.6 µA, a maximum output power (Pmax) of 4.65 mW and a fill factor (F.F.) of 0.615 under AM (Air Mass) 1.5 and 100 mW/cm2 illumination. This voltage is the highest in the world for the area of 1 cm2. The series connection is precisely processed by a focused laser beam, thereby significantly reducing the area needed for device connections. It has been confirmed that a piezoelectric polymer can be directly driven by the electrical output in evaluating the potential of the devices to be used as a microactuator's power source.