In Perosonal communication systems (PCS), reduction control of call blocking rate on wireless-environments, especially in terminating-call set up, is one of the key technologies to design network architecture. This is because the error rate of transferred messages there is normally much higher than that in wired environments. Terminating-call reforwarding technologies, to forward twice terminating-call messages through paging channels depending on call states, would be essential under such conditions, and in the PCS network architecture there are two possible reforwarding schemes: network-assisted reforwarding (NAR) and cell-station-assisted reforwarding (CAR). We first propose a traffic model for evaluating the performance of terminating-call reforwarding from the viewpoint of reduction of the call blocking rate on PCS, and then we clarify the advocating domains for NAR and CAR. Finally, we present a case study using this evaluation model for the Personal Handy-phone System (PHS), which is a PCS in Japan. The results of this study confirm that NAR is more efficient than CAR.

Recently, the high-speed data transmission techniques that have been developed for communication systems have in turn necessitated the implementation of high-speed error correction circuits. Parallel processing has been found to be an effective method of speeding up operarions, since the maximum achievable clock frequency is generally bounded by the physical constraints of the circuit. This paper presents a parallel encoder and decoder architecture which can be applied to both binary and nonbinary cyclic codes. The architecture allows H symbols to be processed in parallel, where H is an arbitrary integer, although its hardware complexity is not proportional to the number of parallel symbols H. As an example, we investigate hardware complexity for a Reed-Solomon code and a binary BCH code. It is shown that both the hardware complexity and the delay for a parallel circuit is much less than that with the parallel operation of H conventional circuits. Although the only problem with this parallel architecture is that the encoder's critical path length increases with H, the proposed architecture is more efficient than a setup using H conventional circuits for high data rate applications. It is also suggested that a parallel Reed-Solomon encoder and decoder, which can keep up with optical transmission rates, i.e., several giga bits/sec, could be implemented on one LSI chip using current CMOS technology.

C1 class smooth interpolation by a fuzzy reasoning for a small data set is proposed. The drafting technique of a human expert is implemented by using a set of fuzzy rules. The effectiveness of the present method is verified by computer simulations and by applications to the practical interpolation problem in a power system.

In this paper we propose a class of byte-error-correcting codes derived from algebraic curves which is a generalization on the Reed-Solomon codes, and present their fast parallel decoding algorithm. Our algorithm can correct up to (m + b -θ)/2b byte-errors for the byte length b, where m + b -θ + 1dG for the Goppa designed distance dG. This decoding algorithm can be parallelized. In this algorithm, for our code over the finite field GF (q), the total complexity for finding byte-error locations is O (bt(t + q - 1)) with time complexity O (t(t + q - 1)) and space complexity O(b), and the total complexity for finding error values is O (bt(b + q - 1)) with time complexity O (b(b + q - 1)) and space complexity O (t), where t(m + b -θ)/2b. Our byte-error-correcting algorithm is superior to the conventional fast decoding algorithm for randomerrors in regard to the number of correcting byte-errors in several cases.

For indoor wireless communication systems, transceivers need to be placed strategically to achieve optimum communication coverage area at the lowest cost. Unfortunately the coverage region for a transceiver depends heavily on the type of building and on the placement of walls within the building. This paper proposed a slab model to simulate the wave transmission in the wall and employed this simple path loss model to predict the coverage region. This method prevents the complicated computation of wave propagation, so it could predict the coverage area real time. Numerical results show predicted path loss date are well agreed with the measurement ones.

Resonant properties of resistance shunted tunnel junctions have been investigated using the RLCSJ model. We found that an increase in dc current resulted from an increase in impedance of the shunted tunnel junctions. The static and dynamic properties of the shunted tunnel junctions were described in detail by numerical simulations and experiments. The simulated and measured results showed good agreement in I-V characteristics. A Josephson array oscillator has been proposed using the resonant properties for increasing oscillator output impedance. We designed and fabricated the oscillator with 20 shunted tunnel junctions. The output power of the oscillator delivered to the load resistor was estimated to be about 0.5µW at 312 GHz.

In this paper, a new explicit transformation method between Bezier and polynomial representation is proposed. An expression is given to approximate (n + 1) Bezier control points by another of (m + 1), and to perform simple and sufficiently good approximation without any additional transformation, such as Chebyshev polynomial. A criterion of reduction is then deduced in order to know if the given number of control points of a Bezier curve is reducible without error on the curve or not. Also an error estimation is given only in terms of control points. This method, unlike previous works, is more transparent because it is given in form of explicit expressions. Finally, we discuss some applications of this method to curve-fitting, order decreasing and increasing number of control points.

A binary counter circuit in the extended phase-mode logic (EPL) family is presented. The EPL family utilizes a single flux quantum as an information bit carrier. Numerical simulations show that a binary counter circuit with a Josephson critical current density of 1 kA/cm2 can operate up to a 30 GHz input signal. The circuit has been fabricated using Nb/AlOx/Nb Josephson junction technology. New interface circuits are employed in the fabricated chip. A low speed test result shows the correct operation of the binary counter.

A method for the recognition of handprinted Thai characters input using an image scanner is presented. We use methods of edge detection and boundary contour tracing algorithms to extract loop structures from input characters. The number of loops and their locations are detected and used as information for rough classification. For fine classification, local feature analysis of Thai characters is presented to discriminate an output character from a group of similar characters. In this paper, four parts of the recognition system are presented: Preprocessing, single-character segmentation, loop structure extraction and character identification. Preprocessing consists of pattern binarization, noise reduction and slant normalization based on geometrical transformation for the forward (backward) slanted word. The method of single-character segmentation is applied during the recognition phase. Each character from an input word including the character line level information is subjected to the processes of edge detection, contour tracing and thinning to detect loop structures and to extract topological properties of strokes. The decision trees are constructed based on the obtained information about loops, end points of strokes and some local characteristics of Thai characters. The proposed system is implemented on a personal computer, and a high recognition rate is obtained for 1000 samples of handprinted Thai words from 20 subjects.

This paper develops an efficient mechanism for extracting primary information requests from 'Seek-Object' type query messages. The mechanism consists of three steps. The first step extracts sentences which signal that the query is 'Seek-Object' type by recognizing distinctive surface expressions. The second step, biased by the expression patterns, analyzes their internal structures. The third step integrates these fragments by a partial discourse processing and represents writers' goal-directed information request; as these sentences often include referential expressions and the referred expressions are in background goal descriptions. We claim the mechanism can extract information requests fairly accurately, by showing evaluation results.

This paper presents a binary neural network approach for link activation problems in multihop radio networks. The goal of the NP-complete problems is to find a conflict-free link activation schedule with the minimum number of time slots for specified communication requirements. The neural network is composed of NM binary neurons for scheduling N links in M time slots. The energy functions and the motion equations are newly defined with heuristic methods. The simulation results through 14 instances with up to 419 links show that the neural network not only surpasses the best existing neural network in terms of the convergence rate and the computation time, but also can solve large scale instances within a constant number of iteration steps.

Multistage Interconnection Networks (MIN) with multiple outlets are networks which can support higher bandwidth than those of nonblocking networks by passing multiple packets to the same destination. Fault recovery mechanisms are proposed for two of such networks (TBSF/PBSF) with the best use of their inherent fault tolerant capability. With these mechanisms, on-the-fly fault recovery is possible for multiple faults on switching elements. For the link fault, the networks are reconfigured after fault diagnosis, and the network is available with some performance degradation. The bandwidth degradation under multiple faults on link/element is analyzed with both theoretical models and simulation. Through the analysis, F-PBSF shows high fault tolerance under high traffic load and low reliability by using 3 or more banyan networks.

For reducing requirement of large memory and minimizing computation complexity in a large-vocabulary continuous speech recognition system, speech segmentation plays an important role in speech recognition systems. In this paper, we formulate the speech segmentation as a two-phase problem. Phase 1 (frame labeling) involves labeling frames of speech data. Frames are classified into three types: (1) silence, (2) consonant and (3) vowel according to two segmentation features. In phase 2 (syllabic unit segmentation) we apply the concept of transition states to segment continuous speech data into syllabic units based on the labeled frames. The novel class of hyperrectangular composite neural networks (HRCNNs) is used to cluster frames. The HRCNNs integrate the rule-based approach and neural network paradigms, therefore, this special hybrid system may neutralize the disadvantages of each alternative. The parameters of the trained HRCNNs are utilized to extract both crisp and fuzzy classification rules. In our experiments, a database containing continuous reading-rate Mandarin speech recorded from newscast was utilized to illustrate the performance of the proposed speaker independent speech segmentation system. The effectiveness of the proposed segmentation system is confirmed by the experimental results.

The present paper investigates a two-dimensional (2-D) adaptive lattice filter used for modeling 2-D AR fields. The 2-D least mean square (LMS) lattice algorithm is used to update the filter coefficients. The proposed adaptive lattice filter can represent a wider class of 2-D AR fields than previous ones. Furthremore, its structure is also shown to possess orthogonality in the backward prediction error fields. These result in superior convergence and tracking properties to the adaptive transversal filter and other adaptive 2-D lattice models. Then, the convergence property of the proposed adaptive LMS lattice algorithm is discussed. The effectiveness of the proposed model is evaluated for parameter identification through computer simulation.

Because the match phase in OPS5-type production systems requires most of the system's execution time and memory accesses, we proposed hash-based parallel production systems, CPPS (Clustered Parallel Production Systems), based on the RETE algorithm for distributed memory parallel computers, or multicomputers to reduce such a bottleneck. CPPS was effective in speeding up the match phase, but still left room for optimizations. In this paper, we introduce software cache techniques to memory nodes in the CPPS as one of the optimizations, and implement it on a multicomputer, nCUBE2. The benchmark results show that the CPPS with the software cache is about 2-fold faster than the original, and more than 7-fold faster than the simple hash method proposed by Acharya et al. for a large scale problem. The speed-up can be attributed to decreased communication costs.

This paper proposes a new duplication redundancy technology, 2 Transistors for 1.5 Gates, that is capable of automatic defect tolerance, so making large, high-resolution, color TFT-LCD panel fabrication both easy and economical. This redundancy technology with automatic defect tolerant capability has a low hardware overhead and is very capable of compensating for open circuit defects in a large active-matrix panel. This technology was confirmed by fabricating a 9.5-inch color TFT-LCD panel with 640480 pixels(960960 dots). This panel showed excellent display performance and produced pictures without defects. The yield improvement effect of this technology was also confirmed by calculation based on the Boltzmann statistics model. Consequently, this technology is clearly seen to have a yield improvement effect equal to defect density reduction of about one order, compared to non redundancy. This technology drastically reduces dot and line defects, enabling fabrication of large, high-resolution, color TFT-LCD panels at a relatively low cost.

An attenuation correction method was proposed for laser-produced plasma emission computed tomography (ECT), which is based on a relation of the attenuation coefficient and the emission coefficient in plasma. Simulation results show that the reconstructed images are dramatically improved in comparison to the reconstructions without attenuation correction.

Physical optics(PO) and the aperture field integration method (AFIM) give accurate and similar field patterns near the first few sidelobes of reflector antennas. It is widely accepted that the use of AFIM is restricted to norrower angles than PO. In this paper, uniform equivalent edge currents of PO and AFIM are compared analytically and their equivalence in high frequency in discussed. It is asymptotically verified that the patterns by AFIM are almost identical to PO fields in the full 360angular region, provided that AFIM uses the equivalent surface currents consisting of two components, that is, the geometrical optics(GO) reflected fields from the reflector and the incident fields from the feed source, the latter of which are often neglected. Slightly weaker equivalence is predicted for cross polarization patterns. Numerical comparison of PO and AFIM confirms all these results, the equivalence holds not only for large but also for a very small refiector of the order of one wavelength diameter.

A new ATM switch architecture, named shared multibuffering, features great advantages on memory access speed for a large switch, and overall size of buffer memories to achieve excellent cell-loss performance. We have developed a 622-Mb/s 88 shared multibuffer ATM switch with multicast functions and hierarchical queueing functions to accommodate 156-Mb/s, 622-Mb/s and 2.4-Gb/s interfaces. Implementation of the shared multibuffer ATM switch is described with respect to the four sorts of 0.8-µm BiCMOS LSIs and ATM switch boards. The switch board/type-1, with C1-LSI, allows to accommodate effectively 156-Mb/s and 622-Mb/s interfaces, which is suitable for an ATM access system. The switch board/type-2, with C2-LSI, can provide multicast functions and accommodate a 2.4-Gb/s interface. By using four switch boards, it is possible to apply them to a 2.4-Gb/s ATM loop system.

To overcome the problem of narrow viewing angle in active matrix liquid crystal displasy(LCDs) in the twisted nematic mode(TN mode), we have proposed a new LCD mode using a bend-alignment cell with an optical compensator. In this new mode, we have successfully obtained a black state with almost no leakage over a wide viewing angle range with very fast response. We describe the fundamental principle and design rule of the optical compensator and discuss the properties obtained in theoretical and experimental term.