In this paper, we propose a modified R-ISMA (reserved idle signal multiple access) protocol for a wireless local area network (WLAN) with a hybrid system construction. The protocol can support a basic service area as large as that supported by a centralized system and allows the direct transmission between neighbor stations as in a distributed system without the problem of hidden terminals. Since a polling scheme is used during transmission of information packets, an ARQ (auto repeat request) scheme is easily applied. A dynamic analysis using transient fluid approximation analysys is used for performance evaluation. In the analysis, we use Fritchman channel model to describe a burst error environment. Some numerical examples using a set of practical system parameters are given. It is shown that the system performance is improved compared with a centralized system with R-ISMA.

A piezoelectric transformer (PT) converter with PWM control is presented. The combination of an active-clamp circuit and a resonant circuit makes it possible to control the output voltage of the PT converter with PWM at a constant switching frequency. The PT converter circuit is evaluated using an AC analysis, and a design procedure is presented. The PT converter implemented on a printed circuit board is experimentally evaluated and a good controllability is successfully achieved.

The paper provides the algorithm to estimate the deviation bound admitting to recovering irregularly sampled signals in wavelet subspaces, which does not need the symmetricity sampling constraint of Paley-Wiener's and relaxes the deviation bounds in some wavelet subspaces. Meanwhile the method does not need the continuity and decay constraints imposed on scaling functions by Liu-Walter and Chen-Itoh-Shiki.

As the number of different video compression algorithms in use and also the specific bit rates at which they are operated increase, there is a growing need for converters from one algorithm or bit rate to another. In general, this can only be accomplished by decoding and re-encoding. It has previously been assumed that the additional delays introduced by such decoding and re-encoding are additive and thereby become unacceptable for some interactive applications. This paper shows that it is possible to construct a transcoder such that the aggregate end-to-end delay is substantially less than the sum of the delays from the two encode and decode pairs. Two techniques are described. The first is more general while the second is simpler but is restricted to the case of reducing the bit rate and keeping the same compression algorithm. Results from simulations of the latter method are included.

Calculation Nv(x) of complex order v numerically, we must calculate Df{JN+ε(x)}. When Df{JN+ε(x)} is calculated by the recurrence method, this letter will analyze the error of Df{JN+ε(x)}, and will determine the optimum number of recurrences.

In this paper, a systematic method which generates the micro-architecture of Application Specific Instruction Processor (ASIP) is proposed. Different from previous works, the data path and control path are generated from the instruction sequence which is generated by translating the compiled assembly code. A graphical representation method called Register Transfer Graph (RTG) is introduced to describe the micro-operations of instruction sequence. To achieve high performance, we perform micro-operation level scheduling which dynamically assigns the micro-operations of instruction sequence to the control steps. By transforming the architecture using synthesis parameters, design space is explored more extensively. Connection cost is minimized by removing the inefficient data transfer paths.

Constantin and Rao have given a method for constructing single asymmetric error correcting (SAEC) codes based on the theory of the Abelian group, This paper uses the method of generating function in combinatorics to solve the implementation problems of the SAEC group theoretic codes. The encoding and decoding algorithms of the coding scheme perform simple arithmetic operations recursively. The idea of generating function can also be applied to t symmetric errors and simultaneously detect all unidirectional errors (t-syEC/AUED) codes for 1t3.

This paper describes a neuro-based optimization algorithm for three dimensional (3-D) cylindric puzzles which are problems to arrange the irregular-shaped slices so that they perfectly fit into a fixed three dimensional cylindric shape. First, the idea to expand the 2-dimensional tiling technique to 3-dimensional puzzles is described. Next, to energy function with the fitting function of each polyomino is introduced, which is available for 3-D cylindric puzzles. Furthermore our algorithm is applied to several examples using the analog neural array. Finally, it is shown that our algorithm is useful for solving 3-D cylindric puzzles.

We discuss a new decoder for the multiple-valued signed-digit number, using a current-mode CMOS transistor-oriented circuit structure. In this paper, a new decoding method with the selective summation of a redundantly represented addend "O = [-1 r]" is proposed, where r is the radix and the addend is applied to each digit with a negative value and any consecutively higher digit takes which has a value of O. A newly designed literal linear circuit is realized, which has a current-switch function that makes independently the short path when each digit has a value of O. Through the parallel connections of these current swiches, the same addend signal at the lower digit is transmitted in a higher speed, The decoder circuit is tested by using the general circuit simulation software SPICE and the circuit characteristics of the selective summation of a redundantly represented O addend and the output results of the SD decoding operation were simulated. We also evaluated the decoder circuit in terms of the processing speed and the circuit size.

This paper proposes a prediction method for non-stationary time series data with time varying parameters. A modular structured type neural network is newly introduced for the purpose of grasping the changing property of time varying parameters. This modular structured neural network is constructed by the hierarchical combination of each neural network (NNT: Neural Network for Prediction of Time Series Data) and a neural network (NNW: Neural Network for Prediction of Weights). Next, we propose a reasonable method for determination of the length of the local stationary section by using the additive learning ability of neural networks. Finally, the validity and effectiveness of the proposed method are confirmed through simulation and actual experiments.

This paper discusses the relationships of two important program classes of linearly recursive programs, that is, decomposable programs and rule commutative programs. We prove that the decomposable programs are always rule commutative. Furthermore, the rule commutative programs that satisfy certain conditions are decomposable. These results are meaningful for integrating the related specified optimization algorithms.

We present a high performance AlGaAs/GaAs power HBT with very low thermal resistance for digital cellular phones. Device structure with emitter air-bridge is utilized and device layout is optimized to reduce thermal resistance based on three-dimensional thermal flow analysis, and in spite of a rather thick substrate (100 µm), which achieved a low thermal resistance of 23/W for a multi-finger (440 µm240 fingers) HBT. This 40 finger HBT achieved power added efficiency (PAE) of over 53%, 29.1 dBm output power (Pout) and high associated gain (Ga) of 13.5 dB with 50 kHz adjacent channel leakage power (Padj) of less than -48 dBc under a 948 MHz π/4-shifted QPSK modulation with 3.4 V emitter-collector voltage. We also investigated the difference of RF performance between two bias modes (constant base voltage and current), and found which mode is adequate for each stage in several stage power amplifier for the first time.

This paper describes a concept of the quasioptical spatial power combining technique and its demonstration of active integrated antenna arrays with strong coupling as an actual example of high efficient combiner in high frequencies. Some configurations of the arrays such as a 3-element linear array and a 33 array are designed with a circuit and electromagnetic simulator. In order to predict the operating frequencies, large signal FET model parameters are determined from measured small signal S-parameters.

In recent years, fractal processes have played important roles in various application fields. Since a 1/f process possesses the statistical self-similarity, it is considered sa a main part of fractal signal modeling. On the other hand, noise reduction is often needed in real-world signal processing. Hence, we propose an enhancement algorithm for 1/f signal disturbed by white noise. The algorithm is based on constrained minimization in a wavelet domain: the power of 1/f signal distortion in the wavelet domain is minimized under a constraint that the power of residual noise in the wavelet domain is smaller than a threshold level. We solve this constrained minimization problem using a Lagrangian equation. We also consider a setting method of the Lagrange multiplier in the proposed algorithm. In addition, we will confirm that the proposed algorithm with this Lagrange multiplier setting method obtains better enhancement results than the conventional algorithm through computer simulations.

A buried gate AlGaAs/InGaAs heterojunction FET (HJFET) with gate breakdown voltage of 30 V was examined for high drain bias (higher than 10 V) operation. High breakdown voltage was realized due to the optimization of the narrow recess depth. A 1.4 mm HJFET has exhibited an output power of 30.2 dBm (1050 mW) with 50% power added efficiency (PAE) and 12.1 dB linear gain at 12 GHz with a 13 V drain bias. An internal matching circuit for a 16.8 mm HJFET was designed using a large-signal load impedance determined from load-pull measurement. The 16.8 mm internally-matched HJFET has delivered 38.9 dBm (7.8 W) output power with 46% PAE and 11.6 dB linear gain at 12 GHz with a drain bias of 13 V. This is the first report of higher than 10 V operation of an X- and Ku-band power HJFET with the excellent power performance.

In this paper, the error performance of block coded 8-PSK modulation systems of length 32, designed for unequal error protection (UEP) of messages transmitted over a Rayleigh fading channel, is investigated. Computer simulation are reported showing that, with transmission over a Rayleigh fading channel, a good improvement in coding gain is obtained by the use of a binary linear UEP (LUEP) code as a constituent code in the multilevel construction, compared with conventional block coded modulation (BCM) of the same length.

Electric fishes generate an AC electric field around themselves by the electric organ in the tail. Spatial distortion of the field by nearby objects is detected by an electroreceptor array located an over the body surface to localize the object electrically when other senses such as vision and mechanosense are useless. Each fish has its own 'frequency band' for its electric organ discharges, and jamming of the electrolocation system occurs when two fish with similar discharge frequencies encounter. To avoid janmming, the fish shift their discharge frequencies in appropriate directions. A computational algorithm for this electrical behavior and its neuronal implementation by the brain have been discovered. The design features of the system, however, are rather complex for this simple behavior and cannot be readily explained by functional optimization processes during evolution. To gain insights into the origin of the design features, two independently evolved electric fish species which perform the same behavior are compared. Complex features of the neuronal computation may be explained by the evolutionary history of neuronal elements.

We have studied the flowthrough operation to simplify operation processes and to promote the efficiency of operation flows. In this paper, we introduce the Construction Manager System (CMS) that cooperates with the ATM Transport Network Operation System (ATMOS). This system directs the construction processes using the construction tickets newly defined by the GDMO (Guidelines for the Definitions of Managed Objects); these tickets and action scenarios are prepared inside the SMS (Scenario Management System). We confirm that CMS can perform construction management using the construction tickets instead of the traditional off-line communications such as the telephone and the facsimile. Furthermore, because CMS cooperates with ATMOS, it is able to manage actual network elements (NEs) and conduct board costruction processes by using construction tickets. Moreover, CMS can confirm that the construction processes of the actual NEs have actually been executed through the Q3 interface. As a result, we verify the basic technique for flowthrough operation for configuration management.

This paper discribes the ISDN PROtocol Testing system (I-PROT). The system consists of translation & distribution function block, layer-2 fault surveillance function block, layer-3 fault surveillance function block, cause detection function block, and HMI. The system receives data from protocol monitors and detects the error recovery sequences, (we call "quasi-normal sequences"), as well as the sequences that do not follow the protocol specifications, (we call "abnormal sequences"). In the layer-3 fault surveillance function block, we use the protocol specification database whose records are converted from the state transition rules and added the judgment which classify the rules into the "normal" and "quasi-normal." We also show the classification method which is applicable to all connection-oriented protocol specifications. In the layer-2 fault surveillance function block, we explain the another easy detecting method. In the cause function block, we describe the partial pattern matching method to relate the protocol fault to the real cause of the fault. We built the prototype of the I-PROT and examine the turn around time (TAT) performance. As a result of the examination, we find the TAT of the I-PROT is directly proportional to the number of the frames analyzed by the system, and the system can reduce the load of the conventional manual analysis by the maintenance personnel.

This paper compares signal classification performance of multilayer neural networks (MLNNs) and linear filters (LFs). The MLNNs are useful for arbitrary waveform signal classification. On the other hand, LFS are useful for the signals, which are specified with frequency components. In this paper, both methods are compared based on frequency selective performance. The signals to be classified contain several frequency components. Furthermore, effects of the number of the signal samples are investigated. In this case, the frequency information may be lost to some extent. This makes the classification problems difficult. From practical viewpoint, computational complexity is also limited to the same level in both methods.IIR and FIR filters are compared. FIR filters with a direct form can save computations, which is independent of the filter order. IIR filters, on the other hand, cannot provide good signal classification deu to their phase distortion, and require a large amount of computations due to their recursive structure. When the number of the input samples is strictly limited, the signal vectors are widely distributed in the multi-dimensional signal space. In this case, signal classification by the LF method cannot provide a good performance. Because, they are designed to extract the frequency components. On the other hand, the MLNN method can form class regions in the signal vector space with high degree of freedom.