A review is presented of the fundamental principles underlying modern techniques for the active control of acoustic noise. The basic physical principles are first dealt with in the context of the active control of free field radiation and the classical approaches to the problem are briefly discussed. The active control of sound fields in ducts and enclosures is also described and the inherent physical limitations of the technique are emphasised. Modern signal processing methods for realising feedforward control systems are also outlined and least squares formulations are presented which enable performance limits to be established and adaptive algorithms to be derived.

This paper describes the application of adaptive filter and wave equalization technology to acoustics, and to noise reduction of a machine using acoustic field control. Firstly, some problems inherent in applying active noise control (ANC) technology to noise reduction in consumer products are pointed out. In particular, the behavior of Error-Adaptive Control, as named by the authors, is analyzed precisely. Secondly, the relationship between coherence and the performance of active control is investigated. The fact that coherence is large or small is more effective for ANC when adaptive control is used rather than fixed-coefficient filter control. The effects of sound spatial coherence on adaptive ANC are studied precisely. The study looks into the relationship between minimum mean square error and input signal variance, or coherence, which has been measured previously. In three-dimensional spatial control, several microphones and speakers are needed for ANC, and several acoustic paths are present. ANC performance in three-dimensional space was evaluated by multiple coherence, which shows the degree of multiple spatial correlation. Thirdly, the paper describes the application of ANC technology to compressor noise in a refrigerator, a mass product. The problem was solved by treating the machine chamber as a one-dimensional duct, preventing howl, and using Error-Adaptive control. The second application is to fan noise in a small device. The authors discovered that the spatial coherence of the sound is low in the vicinity of the fan. This causes ANC to operate at a low level.

The paper considers the design of two families of binary block codes developed for controlling large numbers of errors which may occur in LSI, optical disks and other devices. The semidistance codes are capable of assuring a required signal-to-noise ratio in information retrieval; the t-symmetric error correcting/all unidirectional error detecting" (t-SyEC/AUED) codes are capable of correcting t or fewer symmetric errors and also detecting any number of unidirectional errors caused by the asymmetric nature of transmission or storage madia. The paper establishes an equivalence between these families of codes, and proposes improved methods for constructing, for any values of t, a class of nonsystematic constant weight codes as well as a class of systematic codes. The constructed codes of both classes are shown to be optimal when t is O, and of asymptotically optimal order" in general cases. The number of redundant bits of the obtained nonsystematic code is of the order of (t+1/2)log2 K bits, where K is the amount of information encoded. The obtained systematic codes have redundancy of the order of (t+1)log2 K bits.

An efficient reconstruction algorithm for diffraction tomography based on the modified Newton-Kantorovich method is presented and numerically studies. With the Fréchet derivative obtained for the Helmholtz equation, one can derive an iterative formula for getting an object function, which is a function of refractive index of a scatterer. Setting an initial guess of the object function to zero, the pth estimate of the function is obtained by performing the inverse Fourier transform of its spectrum. Since the spectrum is bandlimited within a low-frequency band, the algorithm does not require usual regularization techniques to circumvent ill-posedness of the problem. For numerical calculation of the direct scattering problem, the moment method and the FFT-CG method are utilized. Computer simulations are made for lossless and homogeneous dielectric circular cylinders of various radii and refractive indices. In the iteration process of image reconstruction, the imaginary part of the object function is set to zero with a priori knowledge of the lossless scatterer. Then the convergence behavior of the algorithm remarkably gets improved. From the simulated results, it is seen that the algorithm provides high-quality reconstructed images even for cases where the first-order Born approximation breaks down. Furthermore, the results demonstrate fast convergence properties of the iterative procedure. In particular, we can successfully reconstruct the cylinder of radius 1 wavelength and refractive index that differs by 10% from the surrounding medium. The proposed algorithm is also effective for an object of larger radius.

The effectiveness of random-switching control, by which the switching-noise spectrum is spread and its level is reduced, is briefly described through experimental results. The noise spectrum by random switching is analyzed in general approach including a noise-generation model and a switching function with random process. Taking the normal distribution as an instance, the discussion on the amount of random perturbation is made quantitatively. The validity of the analysis is confirmed experimentally by a series of pulse serving as ideal switching-noise.

This paper presents a new type of zero-voltage-switched (ZVS) push-pull dc-dc converter with two synchronous rectifiers in the secondary circuit. ZVS is realized using the magnetizing current of the transformer as a constant current source during the commutation. The output voltage is controlled by PWM with a constant switching frequency. The circuit operation is described using equivalent circuits. The steady-state and dynamic characteristics are analyzed and confirmed experimentally.

The pressure waveforms indicated on a catheter manometer system are subject to serious distortion due to the resonance of the catheter itself, or the compliance of a particular transducer. Although several methods have been proposed for improving those characteristics, they ahave never been put into practice. We have focused on the transfer function of the catheter manometer, and made a pilot system, using the natural observation method. This method has been suggested as a means of studying the structure of the instantaneous waveform. In this manner, we were able to increace the bandwidth in the ferquency domain and reduce the ringing in the time domain. Correction was performed automatically, using a step wave. Reproduction of the waveform with a flushing device, was a task of equal simplicity, that allowed us to estimate the system parameters so that the response waveform became step-like. In the experiment, our system provided distortion-free left-ventricular pressure waveform measurements and exact evaluation of the cardiac pumping system. The values obtained came much closer to the original figures arrived at by the catheter-tip manometer system.

Strongly Fault-Secure (SFS) circuits are known to achieve the TSC goal of producing a non-codeword as the first erroneous output due to a fault. Strongly Code-Disjoint (SCD) circuits always map non-codeword inputs to non-codeword outputs even in the presence of faults so long as the faults are undetectable. This paper presents a new generalized design method for the SFS and SCD realization of combinational circuits. The proposed design is simple, and always gives an SFS and SCD combinational circuit which implements any given logic function. The resulting SFS/SCD circuits can be connected in cascade with each other to construct a larger SFS/SCD circuit if each interface is fully exercised.

In developing the SXO operating system for the SURE SYSTEM 2000 continuous operation system, we aimed to create an unprecedentedly high software and hardware fault tolerance. We devised a fault tolerant architecture and various methodologies to ensure fault tolerance. We implemented these techniques systematically throughout operating system development. In the design stage, we developed a design methodology called the recovery process chart to verify that recovery mechanisms were complete. In the manufacturing stage, we applied the concept of critical routes to recovery and other processes essential to high dependability. We also developed a method of finding critical routes in a recovery process chart. In the test stage, we added an artificial software fault injection mechanism to the operating system. It generates various reproducible errors at appropriate times and reduces the number of personnel needed for test, making system reliability evaluation easy.

It has been reported that the efficiency of a low voltage power supply is improved by replacing diodes in an output-stage with synchronous rectifiers (SR). A SR consists of a bipolar junction transistor with a low-saturation voltage and a current transformer. Although the SR has low offset-voltage, its reverse recovery characteristic is usually poor. In this paper, an RCD circuit which improves the reverse recovery characteristic of the SR is proposed. This circuit is simple, and it is composed of a diode, a capacitor and a resistor. The analysis and the experimental results of the SR with the proposed RCD circuit are presented. The optimum design of the RCD to improve the reverse recovery characteristic of SR is discussed.

Inverse filters can be designed in order to enhance the accuracy with which signals recorded in a given space can be reproduced in a given listening space. The problem is considered here of the design of an inverse filter matrix which enables K recorded signals to be accurately reproduced at K points in the listening space when transmitted via M loudspeaker channels. The analysis is sufficiently general to incorporate the case when the best (least squares) approximation is sought to the reproduction of K signals at L points in the space when LK. An analysis is presented which demonstrates that the approach suggested by the Multiple-Input/Output Inverse Filtering theorem of Miyoshi and Kaneda can be realised adaptively by using the Multiple Error LMS algorithm of Elliott et al.

A Pt-based gate and photochemical dry etching were developed to fabricate N-InAlAs/InGaAs HEMT ICs. The N-InAlAs/Pt contact showed a Schottky barrier at 0.82 eV, about 0.3 eV larger than ΔEc, and nearly ideal I-V characteristics. Its main disadvantage was the excess penetration of Pt into InAlAs. We proposed a thin-Pt/Ti/Au multilayer gate, more thermally stable than the thick-Pt gate, where Ti layer suppresses the above problem with Pt. The multilayer gate also showed a Schottky barrier (φ) of 0.83 eV and an edeality dactor of 1.1. The high φ value makes it possible to fabricate an E-mode N-InAlAs/InGaAs HEMT. We also developed photochemical selective dry etching using CH3Br gas and a low-pressure mercury lamp. The etching selectivity was 25 at an etch rate of 17 nm/min for InGaAs and 0.7 nm/min for InAlAs. The 1.2-µm-gate E-mode HEMT fabricated using the Pt-based gate and photochemical etching had an excellent peak transconductance of 620 mS/mm with a threshold voltage of +0.03 V. The standard deviation of the threshold voltage of E-mode HEMTs on a 2-inch wafer was 20 mV at an average of +0.088 V. These results indicate the effectiveness of the Pt-based gate and photochemical etching for fabricating N-InAlAs/InGaAs HEMT ICs.

Advances in semiconductor technology have made it possible to develop an experimental 1000 MIPS superscalar RISC processor. The high performance of this processor was obtained using architectural concepts such as multiple CPU configuration, superscalar microarchitecture, and high-speed device technology. This paper focuses on the novel features of this RISC processor, its device technology, architectural characteristics and one technology that has been devised to make its integer CPU cores fault-tolerant.

The detection problem of fluctuating radar targets in the presence of interference (noise and clutter) is considered; the assumed model for both target and clutter is a zero-mean stationary Gaussian random process with assigned power spectral densities. The pertaing optimum linear processor, namely the Optimized Filtering, is derived and its performance are evaluated in different operating conditions, including mismatching with the designed model. Finally, comparison with filtering techniques designed for targets with zero spectral width, i.e. the Moving Target Detector, are performed.

This paper presents an efficient heuristic algorithm for min-cut bisection of weighted hypergraphs. The proposed algorithm is based on a heuristic algorithm proposed by Kahng, which was devised for non-weighted hypergraph bisection, adopting a non-weighted graph called intersection graph to represent a given hypergraph. In the proposed algorithm, instead of an intersection graph, a bipartite graph called netgraph is newly introduced to explicitly represent the weights of nodes of a hypergraph. Using the netgraph, it is easy to partition a weighted hypergraph into two hypergraphs with same size. Computation time of the proposed method is O(m2), where m is the number of nodes of a given hypergraph. Experimental results with real circuit data show that the proposed method produces better solutions in shorter computation time compared with existing methods.

An autonatic layout scheme dedicated to bipolar analog modules is described. A layout model is settled in such a way that the VCC/GND line is laid out on top/bottom edge of a rectangular region, within which the whole elements are placed and interconnected. According to this simple modeling, a layout scheme can be constructed of a series of the following algorithms: First clustering is executed for partitioning a given circuit into clusters, each having connections with VCC and GND lines, and then linear ordering is applied to clusters so as to be placed in a one-dimensional array. After a relative placement of circuits elements in each cluster, a block compactor is implemented by means of packing blocks in each cluster into an idle space, and then a detailed router is conducted to attain 100% interconnection. Finally a layout compactor is invoked to pack all layout patterns into a rectangle of the minimum possible area. A number of implementation results are also shown to reveal the practicability of the proposed analog module generator.

Behavioral extraction from circuit description is a useful technique for logic design verification. We have proposed a technique of extraction from combinational circuits and developed a prototype system. To use this system practically, it is necessary to deal with sequential circuits. In this paper, we will present a new technique to extract behavioral descriptions from synchronous sequential circuits which include some flip-flops. Flip-flops are classified to two types. The one is a part of control registers. The other is a part of data registers. Behavior of the circuit with control registers is described by the state transition. Behavior of the circuit with data registers is described by the movement of data among registers. There are many circuits, as micro processors, which realize a function after some times of state transitions occurred. In such circuits, it is more important to abstract the function than to extract each state transition. We have progressed our system to extract such behaviors.

An integrated platform INTEGRAL has been developed for developing large complex communication software systems. At the heart of INTEGRAL, a pair of graphical and textual specification languages, DISCOL (DIStributed Communication-Oriented Language), has been developed based on Petri nets. Around DISCOL, a wide variety of design and analysis tools have been integrated in coherent manner so that a seamless support from design to verification and testing are made available along with software life-cycle. The platform has been applied to the development of a PBX simulator named UICPBX. In the development, some real communication services have been fully specified with DISCOL. Such experiences have revealed the effectiveness of the proposed techniques.

In this paper we propose a new timing verification technique named coded time-symbolic simulation, CTSS. Our interest is on simulation of logic circuits consisting of gates whose delay is specified only by its minimum and maximum values. Conventional logic simulation based on min/max delay model leads to over-pessimistic results. In our new method, the cases of possible delay values of each gate are encoded by binary vectors. The circuit behavior for all the possible combinations of the delay values are simulated based on symbolic simulation by assigning Boolean variables to the binary vectors. This simulation technique can deal with logic circuits containing feedback loops as well as combinational circuits. We implemented an efficient simulator by using shared binary decision diagrams (SBDD's) as internal representation of Boolean functions. We also propose novel techniques of analyzing the results of CTSS.

This paper presents unique specification environments for LOTOS, which is one of FDTs (Formal Description Techniques) developed in ISO. We first discuss the large gap in terms of syntax and semantics between informal specifications at the early stage of specification design and formal specifications based on FDT such as LOTOS. This large gap has been bridged by human intelligent works thus far. In order to bridge the large gap, we have designed user-friendly specification environments for FDTs. The outlines of SEGL (Specification Environment for G-LOTOS), CBP (Concept-Based Programming environment) and MBP (Model-Based Programming environment) are described. The effectiveness of software development under such an environment is demonstrated using application examples from OSI and non-OSI protocols.