Almost stoichiometric YBa2Cu3O7-δ(110) or (103) and SrTiOx(110) films, and multilayer films consisting of them have successfully been grown epitaxially on hot SrTiO3 substrates by 90off-axis rf magnetron sputtering with facing targets. Their whole composition, compositional distribution in depth, crystallinity and surface morphology were examined by inductively coupled plasma spectroscopy, Auger electron spectroscopy, reflection high-energy electron diffraction, and scanning tunneling microscopy or atomic force microscope, respectively. When any YBa2Cu3O7-δ film was exposed to air after deposition, a Ba-rich layer was formed in a near surface region of the film. However, such a compositional distribution in depth of the film was improved by in situ deposition of a SrTiOx film on it. Moreover, the surface roughness of the YBa2Cu3O7-δ film was improved by predeposition of a SrTiOx film under it. On the basis of these results, both YBa2Cu3O7-δ/SrTiOx/YBa2Cu3O7-δ/SrTiO3(sub.) and YBa2Cu3O7-δ/SrTiOx/YBa2Cu3O7-δ/SrTiOx/SrTiO3(sub.) multilayer films with average surface roughness of 3 nm were grown reproducibly, which had uniform compositional distribution throughout the depth of the film except a near surface region of the top YBa2Cu3O7-δ layer. A new 222 structure described by Sr8Ti8O20 (Sr2Ti2O5) with a long range ordered arrangement of oxygen vacancies was formed in the SrTiOx films deposited epitaxially on YBa2Cu3O7-δ films.

A new recursive method for obtaining the mean waiting time in a polling system with general service order and gated service discipline is proposed. The analytical approach used to obtain the mean waiting time is via an imbedded Markov chain and a new recursive method is used to obtain the moments of pseudocycle time which are parameters in the formula for the mean waiting time. This method is computationally tractable, so the analytical results can cover a wide range of applications. Simulations are also conducted to verify the validity of the analysis.

Overlapping multi-pulse pulse position modulation (OMPPM) is a modulation scheme having higher capacity and cutoff rate than other conventional modulation schemes when both off-duration between pulses shorter than a laser pulsewidth and resolution better than a laser pulsewidth are realized [1],[2]. In Refs. [1],[2] erasure events of a few chips that can be decoded correctly is defined as an erasure event. This results in lower bounds on the performance of OMPPM in optical-direct-detection channel in quantum limited case. This paper analyzes more exact performance of OMPPM in optical direct-detection channel in quantum limited case when both off-duration between pulses shorter than a laser pulsewidth and resolution better than a laser pulsewidth are realized. First we derive the error probability of OMPPM with considering what chips are detected or erased. Then we derive the capacity and the cutoff rate of OMPPM using the error probability. It is shown that OMPPM outperforms on-off keying (OOK), pulse position modulation (PPM), multi-pulse PPM (MPPM), and overlapping PPM (OPPM) in terms of both capacity and cutoff rate for the same pulsewidth and the same duty cycle. Moreover, it is shown that OMPPM with fewer slots and more pulses per block has better cutoff rate performance when the average received power per slot is somewhat large.

This paper describes CMOS embedded RAMs we developed utilizing 1.3 µm and 0.8 µm process technologies. Our goal was to achieve high-performance switching for digital communication systems. Because such switching can best be obtained by using high-performance embedded RAMs, we used 0.8 µm process technology and developed a 4 kW9 b single-port embedded RAM with 5 ns access time and 100 mW power dissipation during32 MHz operation, and a 1 kW9 b dual-port embedded RAM with 3.7 ns access time and 100 mW power dissipation during 40 MHz operation. We implemented these RAMs on one chip in developing three time-switch VLSIs, one buffer memory VLSI for ATM switches, and two cross-connect switch VLSIs.

We have systematically grown and characterized (Bi, Pb)2Sr2CaCu2Oy (BPSCCO) single crystals, and investigated the tunneling properties and the intrinsic Josephson effects of the single crystals as a function of the nominal composition of Pb, x. It was observed that Pb atoms (ions) were monotonically substituted for Bi atoms (ions) in the (Bi, Pb)-O layers of the crystals with increasing x in a region of 0x0.5, while the modulation structure was maintained in a range of 0x0.3, but disappeared in x0.3, accompanying the decrease of c-lattice parameter and Tc. Moreover, it was found that the energy gaps Δ of BPSCCO depend hardly on x for x0.5, which are about 24 meV, so that the Pb-induced electronic change in the (Bi, Pb)-O layer do not perturb the electronic states in this superconducting system. And it was confirmed that the currentvoltage characteristics of the BPSCCO single crystals had multiple resistive branches corresponding to a series array of several hundreds Josephson junctions, and showed Shapiro steps and zero-crossing steps with the voltage separation of the order of mV resulting from the phase locking of about a hundred Josephson junctions among them under microwave irradiation. The estimated number of junctions gave the concept that the intrinsic Josephson junctions consist of the superconducting block layers and the insulating layers in the BPSCCO single crystals.

Broadcasting with secrecy of messages is important in a situation such as pay television. In pay television only a broadcasting station broadcasts a message. On the other hand, broadcast communication is also important. Broadcast communication means any user in a whole group can broadcast a message to any subset of the group. In this paper the efficiency of secure broadcast communication is discussed in terms of the length of messages sent and the encryption speed. We prove that the length of the broadcast messages is not kept less than O(n), where n is the number of receivers, when a broadcast system has a form of a single system which is defined as the generalized form of an individual key method and a master key method. In contrast, the proposed secure broadcast communication method, a multi-dimension method, keeps the length of messages sent O(mmn), where m is the number of the dimension used in the multi-dimension method. At the same time the encryption speed was reduced from O(n(log(n+C2)+C3)) of the master key method to O(mn(logmn+C1)) of the multi-dimension method.

This paper proposes RSA-type cryptosystems over elliptic curves En(O, b) and En(a, O),where En(a, b): y2 x3+ax+b (mod n),and n is a product of from-free primes p and q. Although RSA cryptosystem is not secure against a low exponent attack, RSA-type cryptosystems over elliptic curves seems secure against a low multiplier attack. There are the KMOV cryptosystem and the Demytko cryptosystem that were previously proposed as RSA-type cryptosystems over elliptic curves. The KMOV cryptosystem uses form-restricted primes as p q 2(mod 3)or p q 3(mod 4), and encrypts/decrypts a 2log n-bit message over varied elliptic curves by operating values of x and y coordinates. The Demytko cryptosystem, which is an extension of the KMOV cryptosystem, uses form-free primes, and encrypts/decrypts a log n-bit message over fixed elliptic curves by operating only a value of x coordinates. Our cryptosystems, which are other extensions fo the KMOV cryptosystem, encrypt/decrypt a 2log n-bit message over varied elliptic curves by operating values of x and y coordinates. The Demytko cryptosystem and our cryptosystems have higher security than the KMOV cryptosystem because from-free primes hide two-bit information about prime factors. The encryption/decryption speed in one of our cryptosystems is about 1.25 times faster than that in the Demytko cryptosystem.

An analog circuit is devised which selects and outputs the kth largest element among n input voltages. The circuit is composed of n basic transconductance amplifiers connected mutually with an O(n) length wire, thus the complexity of the circuit is O(n). The circuit becomes particularly simple for the case of the selection of the median of inputs.

In this paper, authors discuss on a lexicon directed algorithm for recognition of unconstrained handwritten words (cursive, discrete, or mixed) such as those encountered in mail pieces. The procedure consists of binarization, presegmentation, intermediate feature extraction, segmentation recognition, and post-processing. The segmentation recognition and the post-processing are repeated for all lexicon words while the binarization to the intermediate feature extraction are applied once for an input word. This algorithm is essentially non hierarchical in character segmentation and recognition which are performed in a single segmentation recognition process. The result of performance evaluation using large handwritten address block database, and algorithm improvements are described and discussed to achieve higher recognition accuracy and speed. Experimental studies with about 3000 word images indicate that overall accuracy in the range of 91% to 98% depending on the size of the lexicon (assumed to contain correct word) are achievable with the processing speed of 20 to 30 word per minute on typical work station.

This paper presents a low-power 8-valued cellular array VLSI for high-speed image processing based on logical neighborhood operations with 33 windows. This array is useful for performing low-level image processing such as noise removal and edge detection, in intelligent integrated systems where immediate response to input change as well as high throughput is needed. In order to achieve high-speed image processing, template matching for neighborhood operations can be performed in parallel on each row. Each row of the image is operated in a pipelining manner. The direct 8-valued encoding of the matched results for three different 33 masks makes it possible to reduce the number of operations by one-third. In the hardware implementation, the matching cell for logical neighborhood operations can be implemented compactly using MOS transistors with different threshold voltage, which are programmed by multiple ion implants. Moreover, a new literal circuit for detecting multiple-valued signals using a dynamic design style eliminates hazards due to timing skews in the difference of various input voltage levels, so that the dynamic power dissipation of the proposed circuit is greatly reduced. Finally, it is demonstrated that the processing time of the proposed cellular array is reduced to about 40 percent in comparison with that of a corresponding binary circuit when power dissipation/area = 0.3 W/100 mm2.

The paper describes the architecture and the simulated performances of a memory-based chip that emulates human cortical processing in early visual tasks, such as texture segregation. The featural elements present in an image are extracted by a convolution block and subsequently processed by the cortical chip, whose neurons, organized into three layers, gain relational descriptions (intelligent processing) through recurrent inhibitory/excitatory interactions between both inter-and intra-layer parallel pathways. The digital implementation of this architecuture directly maps the set of equations determining the status of the cortical network to achieve an optimal exploitation of VLSI technology in neural computation. Neurons are mapped into a memory matrix whose elements are updated through a programmable computational unit that implements synaptic interconnections. By using 0.5 µm-CMOS technology, full cortical image processing can be attained on a single chip (2020 mm2 die) at a rate higher than 70 frames/second, for images of 256256 pixels.

Net theory originated by Dr. Petri in 1962 is now indispensable key concept in the analysis and design of concurrent systems. In Japan, since late seventies the net theory has attracted attention among computer scientists. This paper reviews the historical aspect of the net theory developed in Japan during the last two decades.

This paper presents a discrete Fourier analyzer using analog VLSI technology. An analog current-mode technique is employed for implementing it by a regular array structure based on the straight-forward discrete Fourier transform (DFT) algorithm. The basic components are 1-dimensional (1-D) analog current-mode multiplier array for fixed coefficient multiplication, two-dimensional (2-D) analog switch array and wired summations. The proposed scheme can process speedily N-point DFT in a time proportional to N. Possibility of the realization of the analog DFT VLSI based on 1 µm technology is discussed from the viewpoints of precision, speed, area, and power dissipation. In the case of 1024-point DFT, the standard deviation of the total error is estimated to be about 2%, the latency, or processing time is about 110 µs, and the signal sample rate based on a pipeline manner is about 4.7 MHz. A prototype MOS integrated circuit of the 16-point multiplier array has been implemented and a typical operation using the multiplier array has been confirmed.

The issue about document structure recognition and document understanding is today one of interesting subjects from a viewpoint of practical applications. The research objective is to extract the meaningful data from document images interpretatively and also classify them as the predefined item data automatically. In comparison with the traditional image-processing-based approaches, the knowledge-based approaches, which make use of various knowledge in order to interpret structural/constructive features of documents, have been currently investigated as more flexible and applicable methods. In this paper, we propose a totally integrated paradigm for understanding table-form documents from a viewpoint of the architectural framework.

This paper discusses the role of knowledge in document image understanding from the viewpoints of representation, utilization and acquisition. For the representation of knowledge, we propose two models, a layout model and a content model, which represent knowledge about the layout structure and content of a document, respectively. For the utilization of knowledge, we implement layout analysis and content analysis which utilize a layout model and a content model, respectively. The strategy of hypothesis generation and verification is introduced in order to integrate these two kinds of analysis. For the acquisition of knowledge, we propose a method of incremental acquisition of a layout model from a stream of example documents. From the experimental results of document image understanding and knowledge acquisition using 50 samples of visiting cards, we verified the effectiveness of the proposed method.

A system for segmentation of document image and ordering text areas is described, and applied to complex printed page layouts of both Japanese and English. There is no need to make any assumptions about the shape of blocks, hence the segmentation technique can handle not only skewed images without skew-correction but also documents where columns are not rectangular. In this technique, based on the bottom-up strategy, the connected components are extracted from the reduced image, and classiferd according to their local information. The connected components calssified as characters are then merged into lines, and the lines are merged into areas. Extracted text areas are classified as body, caption, header or footer. A tree graph of the layout of the body texts is made, and the texts ordered by preorder traversal on the graph. We introduce the concept of an influence range of each node, a procedure for handling titles, thus obtaining good results on various documents. The total system is fast and compact.

It is of significantly importance in relation to the problem of diagnosis of deviation faults in linear analog circuits to check whether or not it is possible to uniquely determine the element-values in a given linear analog circuit from the node-voltage measurements at its accessible nodes and then of giving a method for actual computation of the element-values if it is possible, under the assumption that i) the circuit is of known topology (and of known element-kinds if possible) and ii) the actual value of each element-value of the circuit almost always deviates from the design value and is not known exactly. In this paper, the problem of checking the unique determinability of the element-values is called the element-value determinability problem, and its solutions which have been obtained until now are reviewed in perspectives to designing a publicly available user-oriented analog circuit diagnosis system.

It is demonstrated that the enhancement in the functional capability of an elemental transistor is quite essential in developing human-like intelligent electronic systems. For this purpose we have introduced the concept of four-terminal devices. Four-terminal devices have an additional dimension in the degree of freedom in controlling currents as compared to the three-terminal devices like bipolar and MOS transistors. The importance of the four-terminal device concept is demonstrated taking the neuron MOS transistor (abbreviated as neuMOS or νMOS) and its circuit applications as examples. We have found that any Boolean functin can be realized by a two-stage configuratin of νMOS inverters. In addition, the variable threshold nature of the device allows us to build real-time reconfigurable logic circuits (no floating gate charging effect is involved in varying the threshold). Based on the principle, we have developed Soft-Hardware Logic Circuits and Real-Time Rule-Variable Data Matching Circuits. A winner-take-all circuit which finds the largest signal by hardware parallel processing has been also developed. The circuit is applied to building an associative memory which is different from Hopfield network in both principle and operation. The hardware algorithm in which binary, multivalue, and analog operations are merged at a very device level is quite essential to establish intelligent information processing systems based on highly flexible, real-time programmable hardwares realized by four-terminal devices.

A simple method for separating the dissipation factors associated with both conductor losses and dielectric losses of printed circuit boards in microwave frequencies is presented. This method utilizes the difference in dependence of two dissipation factors on the dimensions of bounded stripline resonators using a single printed circuit board specimen as a center strip conductor. In this method, the separation is made through a procedure involving the comparison of the measured values of the total dissipation factor with those numerically calculated for the resonators. A method, which is based on a TEM wave approximation and uses Green's function and a variational principle, is used for the numerical calculation. Both effective conductivity for three kinds of industrial copper conductor supported with a substrate of polymide film and dielectric loss tangent of the substrates are determined using this method from the values of the unloaded Q measured at the 10 GHz region. Radiation losses from the resonator affecting the accuracy of the separation are discussed, as well as the values of the effective conductivity of metals on the polyimide substrate which is calculated using the above method. The resulting values of the effective conductivity agree with those using the triplateline method within 10%.

We propose a beam tracing frame which shifts together with either the guiding structure or the beam propagation in optical circuits. This frame is adaptive to the beam propagation analysis based on the finite-element method and can reduce the computational window size.