IC performance simulation for statistical purpose is usually very time-consuming since the scale and complexity of IC have increased greatly in recent years. A common approach for reduction of simulation cost is aimed at the nature of simple modeling instead of actual circuit performance simulations. In this paper,a stochastic interpolation model (SIM) scheme is proposed which overcomes the drawbacks of the existing polynomial-based approximation schemes. First,the dependence of the R2press statistic upon a parameter in SIM is taken into account and by maximizing R2press this enables SIM to achieve the best approximation accuracy in the given sample points without any assumption on the sample data. Next, a sequential sampling strategy based on variance analysis is described to effectively construct SIM during its update process. In each update step, a new sample point with a maximal value of variance is added to the former set of the sample points. The update process will be continued until the desired approximation accuracy is reached. This would eventually lead to the realization of SIM with a quite small number of sample points. Finally, the coefficient of variance is introduced as another criterion for approximation accuracy check other than the R2press statistic. The effectiveness of presented implementation scheme is demonstrated by several numerical examples as well as a statistical circuit analysis example.

It has become more important to shorten development periods of high performance computer systems and their LSIs. During debugging of computer prototypes, logic designers request very frequent LSI refabrication to change logic circuits and to add some functions in spite of their extensive logic simulation by several GFLOPS supercomputers. To meet these demands, an automated on-chip direct wiring modification system has been developed, which enables wire-cut and via-digging by a precise focused ion beam machine, and via-filling and jumper-writing by a laser CVD machine, directly on pre-redesign (original) chips. This modification system was applied to LSI reworks during the development of Hitachi large scale computers M-880 and S-3800, and contributed to shorten system debugging period by four to six months.

This paper presents a design of low-power CMOS OTA-C filters suitable for on-chip integration of advanced monolithic system LSIs that have analog I/O and digital signal processing capability. First, we discuss the distortion of MOS cross-coupled circuits which have a quite low distortion when the MOS FETs have the square law characteristics. Considering the nonidealities of MOS FET, however, we find that the third harmonic component of signal dominates the total harmonic distortion (THD) of the cross-coupled pair circuit. We propose a new architecture to reduce the 3rd harmonic component. Low distortion operational transconductance amplifiers (OTA) which consist of the proposed low distortion cross-coupled pair are applied to the realization of OTA-Capacitor filters. The SPICE simulation shows that the THD of the filter is 0.0047% and the power dissipation is 22.6 mW.

The increasing size and complexity of integrated circuits has lead to the development of advanced algorithms and techniques for circuit simulation. The majority of circuit simulators rely on the Newton-Raphson algorithm for the solution of nonlinear equations that arise from the circuit description. Unfortunately, a good estimate of the root to be found is needed for the algorithm to converge. The convergence rate of the algorithm is quadratic once the method gets "close enough" to the solution, but before reaching this point the method may follow a complex route through unrealistic values of the circuit variables, leading eventually to divergence. Simulations performed with SPICE on several test circuits reveal that during the first iterations of the Newton-Raphson algorithm internal node voltages exceed the power supply voltage of several orders of magnitudes even for simple circuits. A new simulation program called MUSIC (Multilevel Simulator for Integrated Circuits) has been developed to overcome these drawbacks. In MUSIC the circuit to be simulated is decomposed in subcircuits, which may contain instances of other subcircuits up to any nesting level. Subcircuits are then simulated independently with a multilevel Newton algorithm permitting to reduce both the large oscillations that circuit variables undergo during the simulation process and the number of iterations necessary for the circuit to converge. The novel feature of this multilevel algorithm is the propagation of the already calculated terminal voltages, which become known after a subcircuit has converged, to the subcircuits connected to same terminals. In this way the information regarding node voltages is propagated through the network without constraining conditions that do not have physical counterpart. Simulations performed on chains of inverters and a 4-bit full adder evidence how MUSIC is able to improve the convergence rate and to reduce the intermediate voltage spikes.

Junction leakage current of trench isolation devices is strongly influenced by trench configuration. The origin of the leakage current is the mechanical stress that is generated by the differential thermal expansion between the Si substrate and the SiO2 filled isolation trench during the isolation forming process. A two-dimensional mechanical stress simulation was used to analyze trench-isolated devices. The simulated distribution and magnitude of stress were found to agree with Raman spectroscopic measurements of actual devices. The stress in the deeper regions between deep trenches is likely to increase greatly as the size of devices diminishes, so it is important to reduce this stress and thus suppress junction leakage current.

The consequences of energy transport related effects like velocity overshoot on the performance of bipolar transistors have already been studied previously. So far however most of the applied models were only 1D and it remained unclear whether such effects would have a significant influence on important quantities like ECL gate delay accessible only on the circuit level. To the authors' best knowledge in this paper for the first time the consequences of energy transport related effects on the circuit level are investigated in a rigorous manner by mixed level device/circuit simulation incorporating full 2D numerical hydrodynamic models on the device level.

This paper proposes a novel method to realize highly linear MOS circuits using MOSFETs in the nonsaturation region. The proposed method is based on the cancellation of nonlinearity of two MOSFETs by using a current inversiontype negative impedance converter. First, grounded and floating resistor realizations are discussed. Next, by exploiting the MOS resistor circuits, gyrators and inductors are realized. As an application example, a third-order doubly-terminated LC filter is simulated. SPICE analysis shows low total harmonic distortions, excellent controllability and small gain error in the passband.

New insights pertaining to hot-carrier degradation of CMOS inverters have been obtained using an in-house reliability simulator named HIRES (Hitachi Reliability Simulator). The simulation of three out of four different inverter configurations which utilize series-connected NMOSFET devices between the output node and ground results in higher levels if degradation than that induced by intuition. For two of the configurations--the cascode inverter (where the gate of all NMOSFET's are connected to the input) and the two-input NAND gate--degradation levels are comparable to that of a simple two-transistor CMOS inverter. This high level of degradation is found to be caused by the fact that most of the output voltage is dropped across one of the series-connected NMOSFET transistors rather than being equally divided between the two. From degradation simulation results, a design methodology is developed to optimize the inverter circuits to minimize hot-carrier degradation by balancing the degradation suffered between the two series-connected NMOSFET's. Using this approach, up to a factor of 109 improvement in device lifetime is achieved.

The theoretical modelling bandgap narrowing and percentage of ionized impurity atoms for uncompensated uniformly doped silicon containing conventional impurities (B, P, As, Sb) under thermodynamic-equilibrium conditions is presented. As distinct from existing approaches, this modelling is valid for impurity concentrations up to electrically-active-impurity-concentration limits and for the temperature range from 40 K up to 400 K. A relevant and efficient calculation software is proposed. The results of the calculations are compared with the results extracted by many authors from measurement data. A good agreement between these results is noted and possible reasons of some discrepancies are pointed out. The present modelling and software can be used for investigation of BJT charge-neutral regions as well as diffused or implanted resistors.

This paper describes modeling and simulation of submicron NMOSFET current drive focusing on carrier velocity-saturation effects. A new simple analytical model is proposed which predicts a significant degradation of drain current in sub- and quarter-micron NMOSFET's. Numerical two-dimensional simulations clarify that the degradation is namely caused by high lateral electric field along the channel, which leads to deep velocity-saturation of channel electrons even at the source end. Experimental data of NMOSFET's, with gate oxide thickness (Tox) of 9-20 nm and effective channel lengths (Leff) of 0.35-3.0 µm, show good agreement with the proposed model. It is found that the maximum drain current at the supply voltage of Vdd=3.3 V is predicted to be proportional to Leff0.54 in submicron NMOSFET's, and this is verified with experiments.

From the viewpoint of customer's satisfaction, precise information and rapid action are very important when complaints about call connection failures or service quality deterioration come from customers. It is indispensable to the propose that operators are supported by an operation system which stores and processes each customer's information, their complaint's histories, network failure status and call connection detail data. This paper shows functions and Human Machine Interface (HMI) of Customer Complaint Handling System (CCHS). This system can handle a customer's complaint by an electric ticket and necessary information is automatically collected and shown on the ticket.

Novel circuit design techniques for CMOSFET (complementary MOS field-effet transistor)-only bias circuits, which each include a current mirror with a peaking characteristic, a current reference with a positive temperature coefficient, and a voltage reference with an optional temperature dependence, are described. An MOS Nagata current mirror is analyzed, and bias circuits like a CMOS self-biasing Nagata current reference and a CMOS self-biasing Nagata voltage reference, both of which include an MOS Nagata current mirror, are discussed. In addition, a CMOS temperature coefficient shifter, used to add an offset voltage and an optional temperature coefficient to a reference voltage, is also discussed. The CMOS Nagata voltage reference was verified with a breadboard using discrete componente and a 0.15 mV/ temperature dependence.

Two types of novel nVT level shift circuits based on the square law characteristics of MOSFETs have been proposed. These circuits generate VIN+nVT or VIN-nVT (where VT is a threshold voltage), if the input voltage is applied as the VIN. These circuits can be widely used in MOSFET characterization, compensating VT effect, VT measurement, level shifting, etc. Type 1 is directly derived from the nVT-sift circuit proposed by Wang. Type 2 can reduce a total chip area than type 1 and has a wider input range. SPICE simulations show that the proposed circuits have a very wide input range and a small power consumption.

To realize a high performance optical subscriber network a route reconnect switch is desired which has bistability, polarization and wavelength independence and compactness. This paper proposes an electrocapillarity optical (ECO) switch, in which a micro-mirror formed by a mercury droplet is driven by electrocapillarity. This switch has a potential for use in bistable waveguide matrix switches, which are suitable for route reconnection in the optical subscriber network. A theoretical model is presented that the driving force of the electrocapillarity originates in an electrically induced gradient in the surface tension of the mercury-electrolyte interface where an electrical double layer is formed. The experimentally obtained relation between the flow velocity of a mercury droplet and the electric current in an electrocapillary system is well described by this model. A prototype of the ECO switch is made using a resin molded single-mode fiber with a slit sawed in it in which a electrocapillary system is made. Optical switching is demonstrated and possible improvements in switching performance are discussed.

OTA (Operational Transconductance Amplifier) is a useful circuit in analog signal processing systems, especially in high-frequency applications. Important features of OTA are: infinite input impedance, electrically changeable transconductance (Gm), and much wider operation range without negative feedback such as in OPamp applications. The good linearity of OTA over wide input range is necessary to extend the application fields of OTA. Several techniques are developed to extend the input range with good linearity. In this paper, a highly-linear CMOS-OTA operating under 1 V power supply, is proposed. The concept of the proposed OTA is based on class-AB operation of two n-channel MOSFETs in the saturation region. By improving the input stage circuits, wide input range can be achieved. SPICE simulations are performed to verify the performance of the proposed OTA.

This paper describes a segment driver IC for high-quality liquid-crystal-displays (LCDs). Major design issues in the segment driver IC are a wide signal bandwidth and excessive output-offset variation both within a chip and between chips. After clarifying the trade-off relation between the signal bandwidth and the output-offset variation originated from conventional sample-and-hold (S/H) circuits, two wide-band S/H circuits with low output-offset variation have been introduced. The basic ideas for the proposed S/H circuits are to improve timing of the sampling pulses applied to MOS analog switches and to prevent channel charge injection onto a storage capacitor when the switches turn off. The inter-chip offset-cancellation technique has been also introduced by using an additional S/H circuit. Two test chips were implemented using the above S/H circuits for demonstration purposes. The intra-chip output-offset standard deviation of 9.5 mVrms with a 3dB bandwidth of 50 MHz was achieved. The inter-chip output-offset standard deviation was reduced to 5.1 mVrms by using the inter-chip offset-cancellation technique. The evaluation of picture quality of an LCD using the chips shows the applicability of the proposed approaches to displays used for multimedia applications.

Photonic ATM switching systems with Terabit/s throughput are desirable for future broadband ISDN systems. Since electronic LSI-based ATM switching systems are planned to have the throughput of 160Gb/s, a photonic ATM switching system should take the role of the highest layer in a hybrid switching network which includes electronic LSI-based ATM switching systems as its sub-system. This report discusses the state-of-the-art photonic devices needed for a frequency-self-routing ATM photonic switching system with maximum throughput of 5Tb/s. This kind of systems seems to be a moderate system for the first phase photonic switching system with no insuperable obstacle for initiating development, even though none of the devices and technologies required have yet been developed to meet the specifications. On the contrary, for realizing further enlarged throughput as the second-phase photonic switching system, there are huge fundamental research projects still remaining for establishing the technology utilizing the spectrum broadened over 120nm and highly-dense FDM technologies based on homodyne coherent detection, if supposing a simple architecture. "Ultra devices" seem to be the photonic devices based on new tailored materials of which gain and refractive index are designed to realize ultra-wide spectrum utilization.

Koblitz and Miller proposed a method by which the group of points on an elliptic curve over a finite field can be used for the public key cryptosystems instead of a finite field. To realize signature or identification schemes by a smart card, we need less data size stored in a smart card and less computation amount by it. In this paper, we show how to construct such elliptic curves while keeping security high.

Reflection type optical switches with intersecting waveguides and curved electrodes are newly proposed. The guided incident mode is expanded into an infinite spectrum of plane wavelets. The effects of light tunneling into the transmission port is taken care of by treating the 3-layer structure and using its reflection and transmission coefficients in estimation of the extinction ratios. It is found that the electrode curved in the form of an exponential spiral provides remarkably improved power reflectivity. This is because it poses a constant angle of incidence (smaller than the critical angle) to all variously oriented impinging wavelets. In this way, all plane wavelets are made to undertake total reflections. These total reflections result in considerably high extinction ratios to be achivable at the transmission port. It is also shown that the electrode length is shorter and the intersection angle is wider than those corresponding to a straight electrode. Therefore, it is concluded that the curvature of the electrode improves the switching characteristics of the device.

Optical waveguides are one of the key devices for photonic integrated circuits considered to be one of the candidates for optical interconnects. In particular lossless bend type waveguides are necessary to integrate different optical devices monolithically. In this paper, we report on the bending loss characteristics of the multi-quantum well bend waveguide with respect to the bend radius and lateral optical mode confinement. We show that to decrease the bending loss to less than 0.5 dB, it is necessary to increase either the confinement or the bend radius. For an example, when the confinement is around 85%, the bend radius should be more than 2 mm. We also show the application of the S-bend waveguides to directional coupler type optical switch.