We examine the characteristics of the past successful m-valued I2L and ROMs that have been designed and we discuss the reasons of their success and withdraw. We look at the problems associated with scaling of m-valued CMOS current mode circuits. Then we discuss the tolerance issue, the respective propagation delays of binary and m-valued ICs and the interconnection issue. We conclude with the challenges for m-valued circuits in the competition with the exponential performance increase of binary circuits.

Some new circuit configurations for dual-input integrators and differentiators are proposed. The use of a multiplier device around the Operational Amplifier (OA) yields electronic tunability of their time-constant (To) by a Control Voltage (Vx). Experimental results in support of theoretical design and analysis are included.

Low-sensitivity digital filters are required for accurate signal processing. Among many low-sensitivity digital filters, a method using complex allpass circuits is well-known. In this paper, a new synthesis of complex allpass circuits is proposed. The proposed synthesis can be realized more easily either only in the z-domain or in the s-domain than conventional methods. The key concept for the synthesis is based on the factorization of lossless scattering matrices. Complex allpass circuits are interpreted as lossless digital two-port circuits, whose scattering matrices are factored. Furthermore, in the cases of Butterworth, Chebyshev and inverse Chebyshev responses, the explicit formulae for multiplier coefficients are derived, which enable us to synthesize the objective circuits directly from the specifications in the s-domain. Finally design examples verify the effectiveness of the proposed method.

This paper describes operating characteristics of a new device named multi-step function MOS transistor (MSF MOSFET) which has stair-shaped I-V curve caused by a stairshaped gap between drain and gate. A quantizing inverter is obtained by using only a single MSF MOSFET as a coupling element of an emitter common amplifier. A pair of the quantizing inverters whose input and output are cross-coupled to each other has multi-stable states. This multiple-valued (MV) flip-flop is available for MV registers and MV memories whose states are changeable by an analog input voltage.

In this paper, a general theory on multiple-valued static random-access-memory (RAM) is investigated. A criterion for a stable and an unstable modes is proved with a strict mathematical method and expressed with a diagrammatic representation. Based on the theory, an NMOS 6-transistor ternary and a quaternary static RAM (SRAM) cells are proposed and simulated with PSPICE. The detail circuit design and realization are analyzed. A 10-valued CMOS current-mode static RAM cell is also presented and fabricated with standard 5-µm CMOS technology. A family of multiple-valued flip-flops is presented and they show to have desirable properties for use in multiple-valued sequential circuits. Both PSPICE simulations and experiments indicate that the general theory presented are very useful and effective tools in the optimum design and circuit realization of multiple-valued static RAMs and flip-flops.

The demand for high-speed image processing is obvious in many real-world computations such as robot vision. Not only high throughput but also small latency becomes an important factor of the performance, because of the requirement of frequent visual feedback. In this paper, a high-performance VLSI image processor based on the multiple-valued residue arithmetic circuit is proposed for such applications. Parallelism is hierarchically used to realize the high-performance VLSI image processor. First, spatially parallel architecture that is different from pipeline architecture is considered to reduce the latency. Secondly, residue number arithmetic is introduced. In the residue number arithmetic, data communication between the mod mi arithmetic units is not necessary, so that multiple mod mi arithmetic units can be completely separated to different chips. Therefore, a number of mod mi multiply adders can be implemented on a single VLSI chip based on the modulus-slice concept. Finally, each mod mi arithmetic unit can be effectively implemented in parallel structure using the concept of a pseudoprimitive root and the multiple-valued current-mode circuit technology. Thus, it is made clear that the throughout use of parallelism makes the latency 1/3 in comparison with the ordinary binary implementation.

A method is proposed for realizing any k-valued n-variable function with a celluler array, which consists of linear arrays (called input arrays) and a rectangular array (called control array). In this method, a k-valued n-variable function is divided into kn-1 one-variable functions and remaining (n1)-variable function. The parts of one-variable functions are realized by the input arrays, remaintng the (n1)-variable function is realized by the control array. The array realizing the function is composed by connecting the input arrays with the control array. Then, this array requires (kn2)kn-1 cells and the number is smaller than the other rectangular arrays. Next, a ternary cell circuit and a literal circuit are actually constructed with CMOS transistors and NMOS pass transistors. The experiment shows that these circuits perform the expected operations.

An adder-based arithmetic VLSI processor using the SD number system is proposed for the applications of real-time computation such as intelligent robot system. Especially in the intelligent robot control system, not only high throughput but also small latency is a very important subject to make quick response for the sensor feedback situation, because the next input sample is obtained only after the robot actually moves. It is essential in the VLSI architecture for the intelligent robot system to make the latency as small as possible. The use of parallelism is an effective approach to reduce the latency. To meet the requirement, an architecture of a new multiple-valued arithmetic VLSI processor is developed. In the processor, addition and subtraction are performed by using the single adderbased processing element (PE). More complex basic arithmetic operations such as multiplication and division are performed by the appropriate data communications between the adder-based PEs with preserving their parallelism. In the proposed architecture, fine-grain parallel processing at the adder-based PE level is realized, and all the PEs can be fully utilized for any parallel arithmetic operations according to adder-based data dependency graph. As a result, the processing speed will be greatly increased in comparison with the conventional parallel processors having the different kinds of the arithmetic PEs such as an adder, a multiplier and a divider. To realize the arithmetic VLSI processor using the adder-based PEs, we introduce the signed-digit (SD) number system for the parallel arithmetic operations because the SD arithmetic has the advantage of modularity as well as parallelism. The multiple-valued bidirectional currentmode technology is also used for the implementation of the compact and high-speed adder-based PE, and the reduction of the number of the interconnections. It is demonstrated that these advantges of the multiple-valued technology are fully used for the implementation of the arithmetic VLSI processor. As a result, the latency of the proposed multiple-valued processor is reduced to 25% that of the binary processor integrated in the same chip size.

This paper presents a VLSI-oriented arithmetic design method using a radix-2 redundant number representation with digit set {0, 1, 2} and multiple-valued current-mode (MVCM) circuit technology. We propose a carry-propagation-free (CPF) parallel addition method with redundant digit set {0, 1, 2} which is suitable for the design with MVCM circuits. Several types of CPF parallel adders are compared and the proposed CPF parallel adder with MVCM circuits offers the best total performance with respect to speed, complexity, and power dissipation. The designed basic arithmetic circuits has sufficient noise immunity to the supply voltage fluctuation which is important for stable operations of the VLSI circuits. The CPF parallel adder is effectively used as the reduction scheme of partial products in a high-speed compact multiplier. For example, the designed 3232 bit multiplier reduces the number of active elements to two-third and the number of interconnections to one-fifth of the corresponding binary Wallace tree multiplier, where the speed is almost the same. The structure is simple and regular. The static power dissipation of the designed 32-bit multiplier is estimated to be the mean value of 212 mW and the worst case of 708 mW. The total power including dynamic power dissipation would not be so large compared with that of the 32-bit binary CMOS multiplier reported under 10 MHz operation.

Rapid advances in integrated circuit technology based on binary logic have made possible the fabrication of digital circuits or digital VLSI systems with not only a very large number of devices on a single chip or wafer, but also high-speed processing capability. However, the advance of processing speeds and improvement in cost/performance ratio based on conventional binary logic will not always continue unabated in submicron geometry. Submicron integrated circuits can handle multiple-valued signals at high speed rather than binary signals, especially at data communication level because of the reduced interconnections. The use of nonbinary logic or discrete-analog signal processing will not be out of the question if the multiple-valued hardware algorithms are developed for fast parallel operations. Moreover, in VLSI or ULSI processors the delay time due to global communications between functional modules or chips instead of each functional module itself is the most important factors to determine the total performance. Locally computable hardware implementation and new parallel hardware algorithms natural to multiple-valued data representation and circuit technologies are the key properties to develop VLSI processors in submicron geometry. As a result, multiple-valued VLSI processors make it possible to improve the effective chip density together with the processing speed significantly. In this paper, we summarize several potential advantages of multiple-valued VLSI processors in submicron geometry due to great reduction of interconnection and due to the suitability to locally computable hardware implementation, and demonstrate that some examples of special-purpose multiple-valued VLSI processors, which are a signed-digit arithmetic VLSI processor, a residue arithmetic VLSI processor and a matching VLSI processor can achieve higher performance for real-world computing system.

The main interest of this paper is the theoretical analysis of a recursive periodically time varying digital filter. The generalized transfer function of a recursive periodically time varying digital filter was obtained from its difference equation. It was proved that by making use of the generalized transfer function, we can not only derive the input and output relationship of a recursive periodically time varying digital filter easily but also obtain its equivalent structure effectively. An interesting property of a recursive periodically time varying digital filter was also derived by making use of its generalized transfer function. Moreover, it was completed in this paper the investigation of the generalized transfer functions and impulse responses of other periodically time varying models, including an input sampling polyphase model and an output sampling polyphase model. Meanwhile, the multirate Quadrature Mirror Filter bank system was proved by the authors to be a periodically time varying system. Several examples were also provided to illustrate the effectiveness of using the generalized transfer function to obtain the equivalent structure of a recursive periodically time varying digital filter.

Robust-fault tolerance is a property that a computational result becomes nearly equal to the correct one at the occurrence of faults in digital system. There are many cases where the safety of digital control systems can be maintained if the property is satisfied. In this paper, robust-fault-tolerant three-valued arithmetic modules such as an adder and a multiplier are proposed. The positive and negative integers are represented by the number of 1's and 1's, respectively. The design concept of the arithmetic modules is that a fault makes linearly additive effect with a small value to the final result. Each arithmetic module consists of identical submodules linearly connected, so that multi-stage structure is formed to generate the final output from the last submodule. Between the input and output digits in the submodule some simple functional relation is satisfied with respect to the number of 1's and 1's. Moreover, the output digit value depends on very small portion of the submodules including the input digits. These properties make the linearly additive effect with a small value to the final result in the arithmetic modules even if multiple faults are occurred at the input and output of any gates in the submodules. Not only direct three-valued representation but also the use of three-valued logic circuits is inherently suitable for efficient implementation of the arithmetic VLSI system. The evaluation of the robust-fault-tolerant three-valued arithmetic modules is done with regard to the chip size and the speed using the standard CMOS design rule. As a result, it is made clear that the chip size can be greatly reduced.

The evolution of Multiple-Valued Logic (MVL) circuits has been inexorably tied to the rapid technological changes induced by evolving needs and emerging developments in computing methodologies. Unfortunately for MVL, the numbers of designers of technologies and circuits whose lives are dedicated to the improvement of binary techniques, are large and overwhelming. Correspondingly, technological developments in MVL typically await the appearance of a problem or technique in the larger binary world to motivate and/or make possible some new advance. Such opportunities are inevitably quite transient since each such problem is simultaneously attacked by many others of a more conventional bent, and, as well, each technological change begets yet another, quickly. It is in the sensing of this reality that the present paper is written. Correspondingly, its thrust is two-fold: One target is the possibility of encouraging a leap ahead through modest technological projection. The other is the possibility of identifying application areas that already exist in this unbalanced competition, but which are specially suited to multiple-valued solutions. For example, it has been clear for decades that one such area is that of arithmetic. Correspondingly, we in MVL must strive quickly to concentrate our efforts on applications that exploit such demonstrable strengths. Some such applications are includes here; others are visible historically, many probably remain to be found: Search on!

In this paper, a design method is described for very low sensitivity fully-balanced narrow-band band-pass switched-capacitor filters (SCF's) whose worst-case sensitivities of the amplitude responses become zero at every reflection zero. The proposed method is based on applying the low-pass to high-pass transformation, the pseudo two-path technique and the capacitance-ratio reduction technique to very low sensitivity low-pass SC ladder filters. A design example of the band-pass SCF with a quality factor Q250 is given to verify the proposed method. The remarkable advantages of this approach are very low sensitivity to element-value variations, a small capacitance spread, a small total capacitance, and clock-feedthrough noise immunity inside the passband.

This paper studies multidimensional linear periodically shift-variant digital filters (LPSV filters). The notion of a generalized multidimensional transfer function is presented for LPSV filters. The frequency characteristic of the filters is discussed in terms of this transfer function. Since LPSV filters can decompose the spectrum of an input signal into some spectral partitions and rearrange the spectrum, LPSV filters can serve as a frequency scrambler. To show the effect of multidimensional frequency scramble, 2-D LPSV filters are designed based on the 1-D Parks-McClellan algorithm. The resultant LPSV filters divide the input spectrum into some components that are permuted and possibly inverted with keeping the symmetric of the spectrum. Experimental results are presented to illustrate the effectiveness of frequency scramble for real images.

This paper describes a mixed mode circuit simulation by the direct and relaxation-based methods with dynamic network partitioning. For the efficient circuit simulation by the direct method, the algorithms with circuit partitioning and latency technique have been studied. Recently, the hierarchical decomposition and latency and their validities have been researched. Network tearing techniques enable independent analysis of each subnetwork except for the local datum nodes. Therefore, if the local datum nodes are also torn, each subnetwork is separated entirely. Since the network separation is based on relaxation approach, the implementation of the separation technique in the circuit simulation by the direct method corresponds to performing the mixed mode simulation by the direct and relaxation-based methods. In this paper, a dynamic "network separation" technique based on the tightness of the coupling between subnetworks is suggested. Then, by the introduction of dynamic network separation into the simulator SPLIT with hierarchical decomposition and latency, the mixed mode circuit simulator, which selects the direct method or the relaxation method and determines the block size of the latent circuit dynamically and suitably, is constructed.

Power-law decay of current for the application of step-function voltage observed for amorphous materials can be expressed by an admittance sa(0a1) of a linear diode using complex angular frequency s. It is shown that power-law decay can be interpreted as a superposition of exponential decays having fractally distributed relaxation times and simulated using RC networks. By use of a similar manner, admittance s-b (0b1) showing the relation of duality can be simulated using RL networks. According to these methods, we can synthesize the admittance involving non-integer exponents systematically.

This paper describes design considerations for high frequency active BPFs up to 100 MHz. The major design issues for high frequency active filters are the excess phase shift in the integrators and high power consumption of the integrators. Typical bipolar transistor based transconductors such as the Gilbert gain cell and the linearized transconductor with two asymmetric emitter-coupled pairs have been analyzed and compared. It has been clarified that the power consumption of the linearized transconductor can be much smaller than that of the Gilbert gain cell because of its high transconductance to working current ratio while maintaining a signal to noise ratio of the same order. A simple high-speed fully differential linearized transconductor cell is proposed with emitter follower buffers and resistive loads for excess phase compensation. A novel gyrator based transformation for the LC ladder BPF has been introduced. This transformation has resulted in a structure with simple capacitor-coupled active resonators which exactly preserves the original transfer function. A fourth order 10.7 MHz BPF IC was designed using the proposed transconductors. It was fabricated and has demonstrated the usefulness of the proposed approach. In addition, an experimental 100 MHz second order BPF IC with Q=14 has been successfully implemented indicating the potential of the proposed approach.

Real-time database systems have the properties of database and real-time systems. This means they must keep timing constraints of transactions as required in real-time systems, and at the same time ensure database consistency as required in database systems. Real-time concurrency control is a general approach for resolving this conflict. In this type of control, a concurrency control technique for database systems is integrated with a task scheduling technique for real-time systems. This paper surveys previous studies on real-time concurrency control and considers future research directions.

This paper describes an automatic transistor model parameter generation technique for a circuit simulator which can take device geometry into account. An 'area factor' is used to generate model parameters for different transistor shapes; however, the conventional method could not reflect the actual geometry differences other than for the emitter area. This resulted in inaccurate model parameters and such parameters were not acceptable to accurately simulate circuits for RF ICs. The proposed technique uses actually measured parameters and process data for a reference transistor and generates the individual model parameters for different shape transistors. In this technique, the parasitic resistor values are calculated and fitted in place of directly extracting them from the measured data. This ensures a better estimate. The reference transistor is made sufficiently large to neglect measurement errors in generating the parasitic capacitors. Thus, the model parameters for a very small transistor can be generated accurately. The model generating procedure has been implemented as a pre-processor to SPICE. This technique enables a fast turn around for RF IC circuit design which uses various shape transistors.