This paper presents an improved current-mode circuit for implementation of a chaotic neuron model. The proposed circuit uses a switched-current integrator and a nonlinear output function circuit, which is based on an operational transconductance amplifier, as building blocks. Is is shown by SPICE simulations and experiments using discrete elements that the proposed circuit well replicates the behavior of the chaotic neuron model.

In 1963, the authors began to develop a tuning circuit (hereafter referred to as the 'circuit') consisting of an inductor, fixed capacitors and a variable capacitor. The circuit required very high accuracy and stability, and the aging influence on resonant frequency needed to be Δf/f0 0.12% for 20 years. When we started, there was no methodology available for designing such a long-term stable circuit, so we reinvestigated our previous studies concerning aging characteristics and formed a design concept. We designed the circuit by bearing in mind that an inductor was subject to natural and stress demagnetization (as indicated by disaccommodation), and assumed that a capacitor changed its characteristics linearly over a logarithmic scale of time. (This assumption was based on short-term test results derived from previous studies.) We measured the aging characteristics of the circuits at room temperature for 20 years, from 1966. The measurement results from the 20-year study revealed that the aging characteristics predicted by the design concept were reasonably accurate.

An analog approach alternative to the Hopfield method is presented for solving constrained combinatorial optimization problems. In this new method, a saddle point of a Lagrangian function is searched using a constrained dynamical system with the aid of an appropriate transformation of variables. This method always gives feasible solutions in contrast to the Hopfield scheme which often outputs infeasible solutions. The convergence of the method is proved theoretically and some effective schemes are recommended for eliminating some variables for the case we resort to numerical simulation. An analog electronic circuit is devised which implements this method. This circuit requires fewer wirings than the Hopfield networks. Furthermore this circuit dissipates little electrical power owing to subthreshold operation of MOS transistors. An annealing process, if desired, can be performed easily by gradual increase in resistance of linear resistors in contrast to the Hopfield circuit which requires the variation in the gain of amplifiers. The objective function called an energy is ensured theoretically to decrease throughout the annealing process.

Mean Time Between Failures (MTBF) is an important measure of practical repairable systems, but it has not been obtained for a repairable linear consecutive-k-out-of-n: F system. We first present a general formula for the (steady-state) availability of a repairable linear consecutive-k-out-of-n: F system with nonidentical components by employing the cut set approach or a topological availability method. Second, we present a general formula for frequency of system failures of a repairable linear consecutive-k-out-of-n: F system with nonidentical components. Then the MTBF for the repairable linear consecutive-k-out-of-n: F system is shown by using the frequency of system failure and availability. Lastly, we derive some figures which show the relationship between the MTBF and repair rate µorρ(=λ/µ) in the repairable linear consecutive-k-out-of-n: F system. The figures can be easily used and are useful for reliability design.

New focused ion beam (FIB) methods for microscopic cross-sectioning and observation, microscopic crosssectioning and elemental analysis, and aluminum film microstructure observation are presented. The new methods are compared to the conventional methods and the conventional FIB methods, from the four viewpoints such as easiness of analysis, analysis time, spatial resolution, and pinpointing precision. The new FIB methods, as a result, are shown to be the best ones totally judging from the viewpoints shown above.

The crosstalk characteristics of a long-wavelength monolithically integrated photoreceiver array are analyzed. The device consists of an array of transimpedance photoreceivers fabricated on a semi-insulating InP substrate. The distance between the photodetectors is large enough to suppress the photonic crosstalk. Therefore, the crosstalk of the device is mainly due to signal propagation from the channels through the power line shared by each channel on the chip. This crosstalk is inevitable to the photoreceiver arrays which employ common power lines. The magnitude of the crosstalk largely depends on the impedance of the power-supply circuit outside the chip. The crosstalk spectrum often has a peak and recess structure. The crosstalk peak at the edge of the operating band-width is due to the resonance characteristic of the transimpedance amplifier. The other peak and recess structures on the spectrum are due to the resonance phenomena of on-chip and off-chip capacitors and inductance on the power-supply line outside the chip. This crosstalk can be reduced by using on-chip bypass capacitance and dumping resistance. However, the resonance due to the capacitance and inductance on the power-supply circuit outside the chip can't be controlled by the on-chip components. Therefore, an optimized design for the power supply circuit outside the chip is also indispensable for suppressing crosstalk.

As promising copy networks of very large multicast switching networks for Broadband ISDN, multi-stage Recursive Copy Networks (RCN) have been proposed recently. In the multicast switch structure, the RCN precedes a point-to-point switch. At an RCN, all the copies of a master cell are generated recursively, i.e., a few copies of the master cell are made initially, and by considering each of these copies to be master cells, more copies are made which, in turn, are again considered to be master cells to make still more copies, the process thus progressing recursively till all the required copies are made. By this principle of recursive generation of copies, the number of copies that can be generated is independent of the hardware size of the RCN. A limitation of RCNs is that buffer sizes at all stages except the first stage have to be large so as to keep the cell loss due to buffer overflow within desired limits. This paper inspects a flow control scheme by which the probability of buffer overflow can be kept low, even though the buffer sizes at later stages are not large. Under this flow control procedure, a cell is not transmitted from a stage to the succeeding stage, if the occupancy level of the buffer of the succeeding stage exceeds a threshold. We study by simulation the performance aspects of such a flow control scheme in RCNs under cut-through switching scheme and under store-and-forward switching scheme. At high load intensities, the overflow probability can be reduced by an order of magnitude in 2-stage RCNs and by two orders of magnitude in 3-stage RCNs. To restrict the overflow probability within a given limit, the required buffer size is less under flow control than under no flow control. The implementation of the flow control is simple and the control overhead is small, thereby making the scheme attractive for implementation in high speed switching environments. Further, the proposed flow control scheme does not disturb the cell sequence.

Reflection type optical switches with intersecting waveguides and curved electrodes are newly proposed. The guided incident mode is expanded into an infinite spectrum of plane wavelets. The effects of light tunneling into the transmission port is taken care of by treating the 3-layer structure and using its reflection and transmission coefficients in estimation of the extinction ratios. It is found that the electrode curved in the form of an exponential spiral provides remarkably improved power reflectivity. This is because it poses a constant angle of incidence (smaller than the critical angle) to all variously oriented impinging wavelets. In this way, all plane wavelets are made to undertake total reflections. These total reflections result in considerably high extinction ratios to be achivable at the transmission port. It is also shown that the electrode length is shorter and the intersection angle is wider than those corresponding to a straight electrode. Therefore, it is concluded that the curvature of the electrode improves the switching characteristics of the device.

Koblitz and Miller proposed a method by which the group of points on an elliptic curve over a finite field can be used for the public key cryptosystems instead of a finite field. To realize signature or identification schemes by a smart card, we need less data size stored in a smart card and less computation amount by it. In this paper, we show how to construct such elliptic curves while keeping security high.

A best-fit panel model in the radio holographic metrology taking into account locations and sizes of actual surface panels in a large reflector antenna is presented. A displacement and tilt of each panel can be estimated by introducing the best-fit panel model. It was confirmed by simulations that the distinction can be drawn between a continuous surface error and a discontinuous one. Errors due to truncation of the radiation pattern were calculated by simulations. It was found that a measurement of a 128128 map is optimum for the 45-m telescope. The reliability of the measurements using this model was examined by experiments with panel displacements. Panel adjustments using the best-fit panel model successfully improved the surface accuracy of the antenna from 138µm rms to 84µm rms (/D=210-6).

Two types of circuit architecture for GaAs LSI are described. The first circuit is named Stacked DCFL which has supply voltage compatibility with Si CMOS/BiCMOS and ECL operating on 3 V or 3.3 V. A divide by 128/129 prescaler IC has been developed to confirm the Stacked DCFL circuit operation. The second circuit is named SVFL which operates on single supply voltage by using Schottky FET characteristics in spite of normally-on FET logic. Both circuit architectures are based on the virtual ground concept. The transition time of 45 psec was obtained by the SVFL ring oscillator circuit fabricated with 1 µm gate length FET process, and the transition time of DCFL using the same process was from 80 psec to 100 psec. Stacked DCFL and SVFL are candidates for an internal gate and an input/output interface circuit for GaAs ASIC, respectively.

A full-wave analysis for the scattering problem of infinite periodic arrays on dielectric substrates excited by a circularly-polarized incident wave is presented. The impedance boundary condition is solved by using the moment method in the spectral domain. Numerical results are given and scattering properties are discussed.

This paper gives a model to explain one phenomenon found in the process of creative concept formation, i.e. the phenomenon that people often get trapped in some state where the mental world remains nebulous and sometimes suddenly make a jump to a new concept. This phenomenon has been qualitatively explained mainly by the philosophers but there have not been models for explaining it quantitatively. Such model is necessary in a new research field to study the systems for aiding human creative activities. So far, the work on creation aid has not had theoretical background and the systems have been built based only on trial and error. The model given in this paper explains some aspects of the phenomena found in creative activities and give some suggestions for the future systems for aiding creative concept formation.

The design of a high speed self-routing network switch module is described. Clock distribution and timing design to achieve high-speed operation are considered. A 88-port self-routing Benes network switch prototype on multi-chip module is fabricated using 44-port space division switch LSIs. The switch module achieves a maximum measured clock frequency of 750MHz under switching operation. Resultant total throughput of the switch module is 12Gbit/s.

This paper describes a novel method to calculate the fields scattered by a polyhedron structure for an incident plane wave. In this method, the fields diffracted by an edge are calculated using the equivalent edge currents which are separated into components dependent on each of the two surfaces which form the edge. The separated equivalent edge currents are based on the Geometrical Theory of Diffraction (GTD). Using this Separated Equivalent Edge Current Method (SEECM) , fields scattered by a polyhedron structure can be calculated without special treatment of the singularity in the diffraction coefficient. This method can be also applied successfully to structures with convex surfaces by modeling them as polyhedron structures.

Four circuit techniques and a layout design scheme were proposed to realize a 2 Mb VRAM used 0.8 µm technology. They are the enhanced circuit technologies for high speed operation, the functional circuit design and the effective repair schemes for a VRAM, the low power consumption techniques to active and standby mode and a careful layout design scheme realizing high noise immunity. Using these design techniques, a 2 Mb VRAM is suitable for the graphics application of a 5125128 pixels basis screen, with a clear mode of 4.6 GByte/sec and a 4-multi column write mode of 400 MByte/sec, even using the same 0.8 µm technology as the previous VRAM (1 Mb) was realized.

Multiplication-accumulation is the basic computation required for image filtering operations. For real-time image filtering, very high throughput computation is essential. This work proposes a hardware algorithm for an application-specific VLSI architecture which realizes an area-efficient high throughput multiplier-accumulator. The proposed algorithm utilizes a priori knowledge of filter mask coefficients and optimizes number of basic hardware components (e.g., full adders, pipeline latches, etc.). This results in the minimum area VLSI architecture under certain input/output constraints.

This paper focuses on two areas in our effort to synthesize speech from neuromotor input using neural network models that effect transforms between cognitive intentions to speak, their physiological effects on vocal tract structures, and subsequent realization as acoustic signals. The first area concerns the biomechanical transform between motor commands to muscles and the ensuing articulator behavior. Using physiological data of muscle EMG (electromyography) and articulator movements during natural English speech utterances, three articulator-specific neural networks learn the forward dynamics that relate motor commands to the muscles and motion of the tongue, jaw, ant lips. Compared to a fully-connected network, mapping muscle EMG and motion for all three sets of articulators at once, this modular approach has improved performance by reducing network complexity and has eliminated some of the confounding influence of functional coupling among articulators. Network independence has also allowed us to identify and assess the effects of technical and empirical limitations on an articulator-by-articulator basis. This is particularly important for modeling the tongue whose complex structure is very difficult to examine empirically. The second area of progress concerns the transform between articulator motion and the speech acoustics. From the articulatory movement trajectories, a second neural network generates PARCOR (partial correlation) coefficients which are then used to synthesize the speech acoustics. In the current implementation, articulator velocities have been added as the inputs to the network. As a result, the model now follows the fast changes of the coefficients for consonants generated by relatively slow articulatory movements during natural English utterances. Although much work still needs to be done, progress in these areas brings us closer to our goal of emulating speech production processes computationally.

In this paper we present a method to generate test sequences for stuck-at faults in sequential circuits which have distinguishing sequences. Since the circuit may have no distinguishing sequence, we use two design techniques for circuits which have distinguishing sequences. One is at state transition level and the other is at gate level. In our proposed method complete test sequence can be generated. The sequence consists of test vectors for the combinational part of the circuit, distinguishing sequences and transition sequences. The test vectors, which are generated by a combinational test generator, cause faulty staes or faulty output responses for a fault, and disinguishing sequences identify the differences between faulty states and fault free states. Transition sequences are necessary to make the state in the combinational vectors. And the distinguishing sequence and the transition sequence are used in the initializing sequence. Some techniques for shortening the test sequence is also proposed. The basic ideas of the techniques are to use a short initializing sequence and to find the order in concatenating sequences. But fault simulation is conducted so as not to miss any faults. The initializing sequence is obtained by using a distinguishing sequence. The efficiency of our method is shown in the experimental results for benchmark circuits.

This article discusses on PDM (Petri net based Development Methodology) which integrates approaches, modeling methods, design methods and analysis methods in a coherent manner. Although various development techniques based on Petri nets have demonstrated advantages over conventional techniques, those techniques are rather ad hoc and lack an overall picture on entire development process. PDM anticipates to provide a refernce process model to develop distributed systems with various Petri net based development methods. Behavioral properties of distrbuted systems can be an appropriate application domain of PDM.