An efficient algorithm is presented for finding all solutions of piecewise-linear resistive circuits. In this algorithm, a simple sign test is performed to eliminate many linear regions that do not contain a solution. Therefore, the number of simultaneous linear equations to be solved is substantially decreased. This test, in its original form, requires O(Ln2) additions and comparisons in the worst case, where n is the number of variables and L is the number of linear regions. In this paper, an effective technique is proposed that reduces the computational complexity of the sign test to O(Ln). Some numerical examples are given, and it is shown that all solutions can be computed very efficiently. The proposed algorithm is simple and can be easily programmed by using recursive functions.

This letter presents an algorithm named SPM which generates test patterns for single stuck-at faults in synchronous sequential circuits based on a product machine traversal method. The new idea presented in this letter is partitioned image computation combined with a mixed breadth-first/depth-first search. Image computation is carried out in partitioned manner by substituting constant logical values to some input variables. This brings about significant reduction in storage requirement during image computation. A test generator based on SPM achieved 100% fault efficiency for the ISCAS'89 benchmark circuits with not more than 32 flip-flops.

We propose a new multiple folding algorithm for the gate matrix layout, and apply it to generation of rectangular blocks with flexible size. The algorithm consists of two phases, the net partitioning and the gate arangement, and both algorithms are based on the multi-way mini-cut technique. In the first and second phases, the width and height of the multiple folded gate matrix block are directly minimized, resperctively, such that the area is minimized and desired aspect ratio of the block is obtained. The features of the present algorithm are as hollows: (1) Dead space on the gate matrix block can be minimized, (2) the aspect ratio can be controlled finely, (3) since polar graphs are successfully used in the second phase, the efficiency of the algorithm can be much improved. The experimental results show the effectiveness of our algorithm.

In this paper we present a method to generate test sequences for stuck-at faults in sequential circuits which have distinguishing sequences. Since the circuit may have no distinguishing sequence, we use two design techniques for circuits which have distinguishing sequences. One is at state transition level and the other is at gate level. In our proposed method complete test sequence can be generated. The sequence consists of test vectors for the combinational part of the circuit, distinguishing sequences and transition sequences. The test vectors, which are generated by a combinational test generator, cause faulty staes or faulty output responses for a fault, and disinguishing sequences identify the differences between faulty states and fault free states. Transition sequences are necessary to make the state in the combinational vectors. And the distinguishing sequence and the transition sequence are used in the initializing sequence. Some techniques for shortening the test sequence is also proposed. The basic ideas of the techniques are to use a short initializing sequence and to find the order in concatenating sequences. But fault simulation is conducted so as not to miss any faults. The initializing sequence is obtained by using a distinguishing sequence. The efficiency of our method is shown in the experimental results for benchmark circuits.

Logic synthesizers usually have good area minimization capabilities, producing circuits of minimal area. But good delay minimization techniques are still missing in current logic synthesis technology. In [7], the RENO algorithm (which stands for REsynthesis for Network Optimization) was proposed for minimizing the area of multi-level combinational networks, and its effectiveness in designing minimal-area networks has been demonstrated. In this paper, we present improvements and extensions of the RENO algorithm for network delay minimization by using Boolean resynthesis techniques. We will discuss new algorithms for gate resynthesis which have not only reduced the processing time significantly, but also have improved the quality of minimization. Due to the generality of the gate resynthesis algorithms, we can minimize both delay and area of a network concurrently in a unified way, and network delay is reduced significantly with no or very small area penalty. Extensive experimental results and comparison with the speed_up algorithm in SIS-1.0 are presented.

Acceleration techniques have been incorporated into the generalized method of characteristics (GMC) to perform transient analysis of uniform transmission lines, for the special case when the transmission lines are driven by digital signals. These techinques have been proved to improve the simulation speed to a great extent when the analysis is carried out using iterative waveform relaxation method. It has been identified that the load impedance connected to the transmission line has a bearing on the efficiency of one of these acceleration techniques. Examples of an RLCG line terminated with linear loads as well as nonlinear loads are given to illustrate the advantage of incorporating these acceleration techniques.

In this paper, a new method of synthesizing multi-level logic circuits directly from binary decision diagrams (BDDs) is proposed. In the simple multiplexer implementation, the depth of the synthesized circuit was always O (n), where n is the number of input variables. The new synthesis method attempts to reduce the depth of circuits. The depth of the synthesized circuits is O (log n log w) where w is the maximum width of given BDDs. The synthesized circuits are 2-rail-input 2-rail-output logic circuits. The circuits have good testability; it is proved that the circuits are robustly path-delay fault testable and also totally self-checking for single stuck-at faults.

A novel approximate equivalent edge currents (EECs) are proposed for use in the modified edge representation (MER) for flat plates. It was reported that PO-EECs with classical PO diffraction coefficients, as applied to MER, perfectly recover PO surface integration. The inclusion of classical FW-EECs as it is, however, would not enhance the accuracy since the reality of the fringe wave is lost in the edge modification. This paper presents simple approximation for inclusion of FW-EECs in MER; FW-EECs are weighted by the function of the angle between the modified edge and the real edge. The key feature of this approach is that uniform fields are predicted everywhere though only classical diffraction coefficients are used. MER also simplifies the ray-tracing in the secondary diffraction analysis. Numerical results for diffraction from flat plates demonstrate the potential of these EECs.

Since the time required for testing logic circuits is proportional to the number of test vectors, the size of test sets as well as test generation time is one of the most important factors to be considered in test generation. The size of test sets becomes an essential issue, especially for scan designed circuits, because of the need to shift a test vector serially into the scan path. In this paper, we propose new methods of generating compact test sets to detect al the irredundant single stuck-at faults in combinational circuits. The proposed algorithms calculate a test function for each fault which corresponds to the set of all test vectors for the fault and generate a compact test set by analyzing the test functions. The analysis is based on finding a test vector which detects the largest number of remaining faults. Since our methods select a test vector among all the test vectors, represented by a test function, for a target fault, smaller test sets can be generated, in general, than that by conventional test set compaction methods. The experimental results show that the size of test sets generated by our method is about one-third as large as that without compaction.

This paper describes IC-oriented high-performance AlGaAs/GaAs heterojunction bipolar transistors that were fabricated to demonstrate their great potential in applications to high-speed integrated circuits. A collector structure of ballistic collection transistors with a launcher (LBCTs) shortens the intrinsic delay time of the transistors. A novel and simple self-aligned fabrication process, which features an base-metal-overlaid structure (BMO), reduces emitter- and base-resistances and collector capacitance. The combination of the thin-collector LBCT layer structure and the BMO self-alignment technology raises the average value of cutoff frequency, fT, to 160 GHz with a standard deviation as small as 4.3 GHz. By modifying collector thickness and using Pt/Ti/Pt/Au as the base ohmic contact metal in BMO-LBCTs, the maximum oscillation frequency, fmax, reaches 148 GHz with a 114 GHz fT. A 2:1 multiplexer with retiming D-type flip-flops (DFFs) at input/output stages fabricated on a wafer with the thin-collector LBCT structure operates at 19 Gbit/s. A monolithic preamplifier fabricated on the same wafer has a transimpedance of 52 dBΩ with a 3-dB-down bandwidth of 18.5 GHz and a gain S21 OF 21 dB with a 3-dB-down bandwidth of 19 GHz. Finally, a 40 Gbit/s selector IC and a 50 GHz dynamic frequency divider that were successfully fabricated using the 148-GHz fmax technologies are described.

We present algorithms for the optimization of sequential synchronous digital circuits using structural model, i.e. interconnections of combinational logic gates and synchronous registers. This approach contrasts traditional methods using state diagrams or transition tables and leveraging state minimization and encoding techniques. In particular, we model circuits by synchronous logic networks, that are weighted multigraphs representing interconnections of gates implementing scalar combinational functions. With this modeling style, area and path delays are explicit and their variation is easy to compute when circuit transformations are applied. Sequential logic optimization may target cycle-time or area minimization, possibly under area or cycle-time constraints. Optimization is performed by a sequence of transformations, directed to the desired goal. This paper describes the fundamental mechansms for transformations applicable to sequential circuits. We review first retiming and peripheral retiming techniques. The former method optimizes the position of the registers, while the latter repositions the registers to enlarge maximally the combinational region where combinational restructuring algorithms can be applied. We consider then synchronous algebraic and Boolean transformations, that blend combinational transformations with local retiming. Both classes of transformations require the representation of circuits by means of logic expressions with labeled variables, the labels representing discrete time-points. Algebraic transformations entail manipulation of time-labeled expressions with algebraic techniques. Boolean transformations exploit the properties of Boolean algebra and benefit from the knowledge of don't care conditions in the search for the best implementation of local functions. Expressing don't care conditions for sequential circuits is harder than for combinational circuits, because of the interaction of variables with different time labels. In addition, the feasibility of replacing a local function with another one may not always be verified by checking for the inclusion of the induced perturbation in local explicit don't care set. Indeed, the behavior of sequential circuits, that can be described appropriately by the relation between input and output traces, may require relational models to express don't care conditions. We describe a general formalism for sequential optimization by Boolean transformations, where the don't care conditions are expressed implicitly by synchronous recurrence equations. We present then an optimization method for this model, that can exploit degrees of freedom in optimization not possible for other methods, and hence providing solutions of possible superior quality. We conclude by summarizing the major features and limitations of optimization methods using structural models.

We discuss delay times derived from the current gain cutoff frequency of a heterostructure field effect transistor and describe three types of novel channel structures for millimeter-wave InP-based HFETs. The first structure discussed is a lattice-matched InGaAs HEMT with high state-of-the art performance. The second structure is an InAs-inserted InGaAs HEMT which harnesses the superior transport properties of InAs. Fabricated devices show high electron mobility of 12,800 cm2/Vs and high transconductance over 1.4 S/mm for a 0.6-µm-gate length. The effective saturation velocity in the device derived from the current gain cutoff frequency in 3.0107 cm/s. The third one is an InGaAs/InP double-channel HFET that utilizes the superior transport properties of InP at a high electric field. Fabricated double-channel devices show kink-free characteristics, high carrier density of 4.51012 cm-2 and high transconductance of 1.3 S/mm for a 0.6-µm-gate length. The estimated effective saturation velocity in these devices is 4.2107 cm/s. Also included is a discussion of the current gain cutoff frequency of ultra-short channel devices.

This paper presents a new idea of photometric stereo method which uses 3 point light sources as illumination source. Its intention is to extract the 3-D information of gastric surface. The merit of this method is that it is applicable to the textured and/or specular surfaces, moreover whose environment is too narrow, like gastric surface. The verification of the proposed method was achieved by the theoretical proof and experiment.

The barrier-layer was successfully fabricated for a preparation of tunneling junction using high Tc oxidesuperconductor such as Bi-Sr-Ca-Cu-O system. Bi2Sr2Ca2Cu3Ox films were used for both superconducting electrodes and the barrier was mainly Bi2Sr2CaCu2O and the rest that was formed by effects of de-calcium from the first sputtered (2223) film. The reaction of de-calcium occurred immersing it in carbonated water. The change of (2223) phase of BSCCO was confirmed with a comparison of the intensity of X-ray diffraction. The superconductive transition temperature of the junction is different from that of the single film (2223) which had no treatment with carbonated water. Zero-bias-currents through fabricated barrier are observed and the critical currents depend on temperature so far as measured temperature region of 79 K-72 K.

Nojima and Fujita have found a universal relation, irrespective of temperatures T, between the reduced field hH/Hir(T) and the reduced quantity of magnetization hysteresis mΔM (T, H)/ΔM (T, H0), where Hir is the irreversibility field and ΔM(T, H) is the hysteresis of magnetization for YBa2Cu3Ox and Bi2Sr2CaCu2Ox films. We could explain this universal relation based on a scaling theory in a three-dimensional superconducting vortex-glass phase. The exponent ν derived by this relation coincides with that obtained by nonlinear I-V characteristics for YBa2Cu3Ox films.

We have fabricated bi-epitaxial grain boundary junctions in YBa2Cu3O7δ (YBCO) thin films by using SrTiO3 (STO) seed layers on MgO(100) substrate. YBCO film growing over the STO seed layer has a different in-plane orientation from YBCO film without the seed layer, so artificial grain boundaries were created at the edge of the seed layer. The fabricated junctions have high Tc (up to 80 K), and constant-voltage current steps are observed in response to 12.1 GHz microwave radiation. Moreover, some of the junctions show characteristic current-voltage curves comprising not only an usual Josephson-like characteristic but also a low critical current due to the flux creep. This suggests that the two characteristic parts are likely to be connected in series at the junction region.

In order to investigate the characteristics of the superconducting gap structures of BSCCO oxide superconductor, tunneling spectrum measurements were carried out with several junctions on the bulk single crystal surfaces. Point contact tunneling studies by means of the M/I/S and S/(I)/S junctions have shown the reproducible gap values, 2Δ (//c-axis) of 402 meV, at the cleaved crystal surfaces, and the ratio of 2Δ(//)/kBTc5.50.3 indicates the strong coupling superconductor of this material. Somewhat larger gap values, 2Δmax(c-axis)701 meV, have been also observed at the lateral surface, and these various gap values observed on each surface of the same crystal indicate the characteristic of the large gap anisotropy, Δ()/Δ(//)1.8, of this material.

In this paper we consider multiuser detection using a neural network in a synchronous code-division multiple-access channel. In a code-division multiple-access channel, a matched filter is widely used as a receiver. However, when the relative powers of the interfering signals are large, i.e. the near-far problem, the performances of the matched filter receiver degrade. Although the optimum receiver for multiuser detection is superior to the matched filter receiver in such situations, the optimum receiver is too complex to be implemented. A simple technique to implement the optimum multiuser detection is required. Recurrent neural networks which consist of a number of simple processing units can rapidly provide a collectively-computed solution. Moreover, the network can seek out a minimum in the energy function. On the other hand, the optimum multiuser detection in a synchronous channel is carried out by the maximization of a likelihood function. In this paper, it is shown that the energy function of the neural network is identical to the likelihood function of the optimum multiuser detection and the neural network can be used to implement the optimum multiuser detection. Performance comparisons among the optimum receiver, the matched filter one and the neural network one are carried out by computer simulations. It is shown that the neural network receiver has a capability to achieve near-optimum performance in several situations and local minimum problems are few serious.

Experimental results of an N-S junction and analysis of the results using the Arnold theory were reported. Au and Pb were employed as a normal metal and a superconducting material, respectively. The excess current effect due to the Andreev reflection was observed in the current-voltage characteristics of an N-S junction whose normal resistance was 1.603 Ω. The excess current at 4.62 K was about 0.7 mA when the applied voltage was 2 mV. The barrier height and width were estimated to be 1.0169 eV and 0.7 , respectively, by comparing the experimental results and analysis based on the Arnold theory. In the voltage region less than 2 mV, the theory well agreed with the experiment. Moreover, the applied voltage dependence of the supercurrent and quasiparticle current were separately calculated. It was made clear that the supercurrent was larger than the quasiparticle current in the voltage region less than 2Δ/e, where Δ is the superconducting energy gap and e is the absolute value of an electron's charge. The supercurrent began to gradually saturate when the voltage was higher than Δ/e and became constant at the applied voltage greater than 2Δ/e. In our experiment, the excess current larger than expected from the Arnold theory was observed in the voltage region higher than 2Δ/e.

To realize next-generation high performance ULSI processors, it is a very important issue to reduce the critical delay path which is determined by a cascade chain of basic gates. To design highly parallel digital operation circuits such as an adder and a multiplier, it is difficult to find the optimal code assignment in the non-linear digital system. On the other hand, the use of the linear concept in the digital system seems to be very attractive because analytical methods can be utilized. To meet the requirement, we propose a new design method of highly parallel linear digital circuits for unary operations using the concept of a cycle and a tree. In the linear digital circuit design, the analytical method can be developed using a representation matrix, so that the search procedure for optimal locally computable circuits becomes very simple. The evaluations demonstrate the usefulness of the circuit design algorithm.