This paper describes a 95 mW MPEG2 MP@HL motion estimation processor core for portable and high-resolution video applications such as that in an HD camcorder. It features a novel hierarchical algorithm and a low-power ring-connected systolic array architecture. It supports frame/field and bi-directional prediction with half-pel precision for 19201080@30 fps resolution video. The search range is 12864 pixels. The ME core integrates 2.25 M transistors in 3.1 mm3.1 mm using 0.18-micron technology.

The measurement results of clear sky attenuation on an earth-satellite path at frequency Ku band in Laos are described. The measurement results show that diurnal clear sky noise vary with respect to humidity characteristics, which is a significant value in the early morning while low at daytime. The mean difference in variation is about 0.7 dB.

This paper presents analysis results on finite-impulse response (FIR) channel estimation used for the equalization in Advanced Television Systems Committee digital television receivers. While channel estimation results have been effectively used for the equalization, the conditions of sufficient order and high signal-to-noise ratio (SNR) were assumed in most cases. To compensate for these unrealistic assumptions, we consider diverse probable conditions for channel estimation, such as reduced order and low SNRs, and then theoretically analyze each estimation case. The analysis shows that the adaptive FIR channel estimator provides an unbiased estimation and matches well its corresponding channel coefficients irrespective of the number of taps of the estimator and the non-causality of the unknown channel. Simulation results verify our analysis on the estimation of terrestrial DTV channels.

An ultra-high-sensitivity HDTV color camcorder (camera with VTR) has been developed featuring image intensifiers with GaAsP photocathodes, which provide very high quantum efficiency. To achieve superior performance and a compact camera body, we combined three 1-inch image intensifiers with a 2/3-inch taking lens and three 2/3-inch CCDs by means of a new optical system capable of enlarging and reducing images. The camcorder provides excellent color reproducibility even under low light level conditions (0.2 lx) at an iris setting of f/2, with a signal-to-noise ratio of 55 dB at pedestal level. Its sensitivity is about 400 times greater than that of current HDTV CCD camcorders, making it particularly well suited for capturing images of faint objects in space, aurora, etc., filming the nocturnal activities of animals in their natural settings, and reporting breaking news at night.

This paper describes an ultra low power, motion estimation (ME) processor for MPEG2 HDTV resolution video. It adopts a Gradient Descent Search (GDS) algorithm that drastically reduces required computational power to 6 GOPS. A SIMD datapath architecture optimized for the GDS algorithm decreases the clock frequency and operating voltage. A low power 3-port SRAM with a write-disturb-free cell array arrangement is newly designed for image data caches of the processor. The proposed ME processor contains 7-M transistors, integrated in 4.50 mm 3.35 mm area using 0.13 µm CMOS technology. Estimated power consumption is less than 100 mW at 81 MHz@1.0 V. The processor is applicable to a portable HDTV system.

An MPEG-2 422P@HL encoder chip set composed of a preprocessing LSI, an encoding LSI, and a motion estimation LSI is described. This chip set realizes a two-type scalability of picture resolution and quality, and executes a hierarchical coding control in the overall encoder system. Due to its scalable architecture, the chip set realizes a 422P@HL video encoder with multi-chip configuration. This single encoding LSI achieves 422P@ML video, audio, and system encoding in real time. It employs an advanced hybrid architecture with a 162 MHz media processor and dedicated video processing hardware. It also has dual communication ports for parallel processing with multi-chip configuration. Transferring of reconstructed data and macroblock characteristic data between neighboring encoder modules is executed via these ports. The preprocessing LSI is fabricated using 0.25 micron three-layer metal CMOS technology and integrates 560 K gates in an area of 12.0 mm 12.0 mm . The encoding LSI is fabricated using 0.25 micron four-layer metal CMOS technology and integrates 11 million transistors in an area of 14.2 mm 14.2 mm . The motion estimation LSI is fabricated using 0.35 micron three-layer metal CMOS technology. It integrates 1.9 million transistors in an area of 8.5 mm 8.5 mm . This chip set makes various system configurations possible and allows for a compact and cost-effective video encoder with high picture quality.

We have developed an experimental 4 K 2 K pixel progressive scan color camera system. This new camera system has a data rate of 297 MHz pixel/sec and 60 frame/sec and we are sure that horizontal and vertical limiting resolution of 1500 TVL (TV lines) can be achieved on a color monitor. Instead of the previous approach of improving resolution simply by increasing the pixel count in a imager, a novel four-sensor pickup method with 2/3 inch 2 million pixel CMD (Charge Modulation Device) imagers is used in this system. These sensors have 1920 (H) 1035 (V) pixels within a 16:9 wide aspect image area and are successfully driven at 148 M pixel/sec in the progressive scan mode. In the four-sensor pickup method, two sensors are used for green and the rest are for red and blue. A spatial offset imaging method in the diagonal direction was applied to the two green sensors to improve the horizontal and vertical resolution effectively. The horizontal and vertical resolution of the red and blue signals become half that of the green signal, because only one 2 M-pixel imager is used for each signal. The resolution of this system, however, is not degraded so much because the luminance signal is mainly composed of green signals.

In this paper, a dedicated hardware design for motion estimation LSI of MPEG2 is presented. Combining our bits truncation adaptive pyramid (BTAP) algorithm with Window-MSPA architecture, the hardware cost is tremendously reduced without PSNR performance degradation for mean pyramid algorithm. The core of the test chip working at 83 MHz, performs a search range of 67 for image size of 1920 1152 and achieves video rate of 60 field/s. It can be used for HDTV purpose. The chip size is 4. 8 mm 4. 8 mm with 0. 5u 2-level metal CMOS technology. The result in this paper shows our promising future to realize one chip HDTV MPEG2 encoder.

A single chip motion estimator is described dedicatedly for MPEG2 MP＠HL moving pictures. Adopting a two-level hierarchical searching algorithm in detecting motion vectors, the computational labor can be reduced by 1/70 in comparison with the conventional algorithm. A novel mechanism is introduced into the full-search procedure, which attempts the maximum possible reuse of reference pixels in order to reduce the bandwidth of the frame memory interface. The proposed motion estimator is integrated in a 0.6 µm triple-metal CMOS chip, which contains 1,450 K transistors on a 12.713.7 mm2 die. The input clock rate can be attained up to 133 MHz, which enables the real time motion estimation for MPEG2 MP＠HL.

A single chip MPEG2 MP@HL Video decoder has been developed, which consists mainly of specific functional units and macroblock level pipeline buffers. A new organization is also devised for a set of off-chip frame memories and the interfaces associated with it. Owing to sophisticated I/O interfaces among functional units, the macroblock level pipeline in conjunction with different decording facilities attains a high throughput to such an extent as to decode HDTV images in real time. Moreover, a set of these functional units, pipeline buffers, and frame memory interfaces, together with a sequence controller, is integrated for the first time in a single chip, which has the total area of 8.8 9.2mm2 with a 0.6µm triple-mental CMOS technology, and dissipates 1.2 W from a single 3.3 V supply.

The current state of development of the television broadcasting system of the future is described with regard to LSI development. It is no need to say that television broadcasting systems are very huge and require a large number of inexpensive LSI's. Hi-Vision broadcasting has already been started in Japan. In the United States, a digital terrestrial broadcasting system (ATV) will be standardized in the near future. On the other hand, the situation in Europe remains unclear but MPEG-2 is now in the stage of system finarizing. We also hear much about "multimedia" but the concept of multimedia broadcasting still requires a lot of time to be translated into reality. Some important current technical topics and related basic technologies are also described in this paper. They include DCT, Hybrid DCT coding, error correcting coding, coded modulation, and improvement of the MUSE system. Finally, the discussion considers the relationship between system development and VLSI technology and the importance of mutual understanding between VLSI engineers and system designers. Some possible requirements for VLSI development are also stated.

Development of low power MUSE (Multiple Sub-Nyquist Sampling Encoding) chip set through reduction in operating voltage (from 5 V to 3.7 V) is described. This leads to great cost reduction since the chips could be mounted on low cost plastic packages and the necessity for cooling fans to dissipate heat was obviated. To maintain compatibility with standard 5 V analog and digital peripherals such as 4 Mbit DRAMs and an A/D converter, a special voltage-level converter was also developed.

This paper describes a design method of stuff synchronization circuit for High-definition Television (HDTV) transmission to reduce stuff jitter, one of the greatest problems in video transmission through plural Synchronous Digital Hierarchy (SDH) networks operating with different frequency sources. First, we determine the quantity of stuff jitter in SDH networks using the pointer mechanism and Administration Unit (AU) pointer bytes. From the results of a subjective test conducted for HDTV, we show that the minimum noticeable jitter is 3.6 nsec in using a color-bar pattern as a test image and a sinusoidal wave as a jitter signal. These results are used to describe the effect of stuff jitter on picture quality. We then introduce a distributed destuffing method at the receiving end, and show that jitter can be reduced by about 32dB in a 622Mbps rate system. Based on these results, we finally show that the cut-off frequency of the clock recovery PLL for distributed destuffing is more than 10 times higher than that required by conventional destuffing. This reduces the pull-in time by more than 99.9%.

In the future satellite broadcasting system in 21GHz band, the rainfall attenuation is a most significant problem. To solve this problem, the hierarchical transmission systems have been studied. This paper analyzes the performance of the hierarchical modulation scheme from the view point of power assignment in the presence of the rainfall attenuation. This paper shows an optimum power assignment ratio to maximize the spectral efficiency and the signal-to-noise ratio of received image, and these optimum ratio is varied with the measure of system performance.

High Definition Television (HDTV) is likely to be one of the major services in the Broadband Integrated Services Digital Network (B-ISDN). The transmission of HDTV signals on digital networks requires the adoption of sophisticated compression techniques to limit the bit-rate requirements and to provide high-quality and cost-effective network services. A flexible coding scheme that supports various bit-rates is needed to support the various services expected which will have different requirements. This paper describes the design of an HDTV codec based on a subband DCT coding algorithm that can encode original 1.2 Gb/s HDTV signals to less than 50Mb/s. A configuration that efficiently bridges HDTV and standard TV signals is also proposed. Computer simulation results show that the degradation caused by the bridging function is insignificant. In the coder, first stage quadrature mirror filters (QMFs) decompose the input signal into two bands in the horizontal direction, while the second stage filters decompose the two bands into four bands in the vertical direction. Adaptive DCT (Discrete Cosine Transform) is adopted for horizontal-low and vertical-low (LL) signal coding. High-band signals are coded by adaptive DPCM and PCM. To maximize bit-rate reduction efficiency, DCT coding is adaptively applied to either the intra-field signals, the inter-field signals, or the motion compensated inter-frame signals. Bi-directional inter-frame prediction is applied to the adaptive DCT coding to improve coding performance at low bit rates. The same prediction mode as for LL signal is applied to adaptive DPCM coding of LH and HL signals. Compatibility is realized by a configuration in which both the TV signal components and the residual signal, derived by subtracting the TV signal from the LL signal, are encoded.

The transmission of HDTV signals on digital networks requires adoption of sophisticated compression techniques to limit the bit-rate requirements and to provide a high-quality and reliable services to customers. This paper describes system design and transmission characteristics of an adaptive subband DCT codec that can encode original 1.2Gb/s HDTV signals at 156Mb/s. The performance of the codec was evaluated using motion picture signals. The characteristics obtained with the codec was found to maintain good picture quality.

High-Definition Television (HDTV) 2 million pixel solid state image sensors with high performances are realized, applicable for 1 inch optical format. Key technical aspects of HDTV image sensors are suppression of smear level by maintaining large optical aperture and high readout signal rate by introducing a dual channel horizontal register. From such a perspective, new HDTV image sensors such as Stack CCD, Frame-Interline Transfer (FIT) CCD and Charge Modulation Device (CMD) are developed.

Multidimensional signal processing has recently been attracting attention in various fields, and has been studied theoretically. TV receives using 3-D (3-Dimensional: horizontal, vertical and temporal) processing, such as IDTV (ImproveD TV), are already available. In addition, television systems with high quality video and mostly with wide-aspect ratio are being studied worldwide. All the proposed systems adopt 3-D signal processing. 3-D processing can fully utilize the transmitted signal, and can take full advantage of the available bandwidth. This results in improved picture quality. This paper reviews the 3-D signal processing used in IDTV and EDTV (EnhanceD TV) in Japan. Video signals are analyzed in the 3-D frequency domain, and 3-D filter design is also studied.

The present status of HDTV in Europe and the concept of an evolutionary introduction of HDTV broadcasting is described. Corresponding HDTV standards and studio technologies are outlined. Analog transmission techniques like HD-MAC as well as coding techniques for digital transmission are presented. Also some informations about investigations for non-broadcast applications are given.