We present a successful method for designing 2-D circularly symmetric R lowpass filters with constant group delay. The procedure is based on a transformation of a 1-D prototype R filter with constant group delay, whose magnitude response is the 2-D cross-sectional response. The 2-D filter transfer function has a separable denominator and a numerator which is obtained from the prototype numerator by means of a series of McClellan transformations whose free parameters can be optimized by successive procedure. The method is illustrated by an example.

Logarithmic number systems (LNS) provide a very fast computational method. Their exceptional speed has been demonstrated in signal processing and then in computer graphics. But the precision problem of LNS in computer graphics has not been fully examined. In this paper analysis is made for the problem of LNS in picture generation, in particular for circle drawing. Theoretical error analysis is made for the circle drawing. That is, some expressions are developed for the relative error variances. Then they are examined by simulation experiments. Some comparisons are also done with floating point arithmetic with equivalent word length and dynamic range. The results show that the theory and the experiments agree reasonably well and that the logarithmic arithmetic is superior to or at least comparable to the corresponding floating point arithmetic with equivalent word length and dynamic range. Those results are also verified by visual inspections of actually drawn circles. It also shows that the conversion error (from integer to LNS), which is inherent in computer graphics with LNS, does not make too much influence on the total computational error for circle drawing. But it shows that the square-rooting makes the larger influence.

Syntax-directed editors have several advantages in editing programs because programming is guided by the syntax and free from syntax errors. Nevertheless, they are less popular than text editiors. One of the reason is that they force a priori specified editing structures on the user and do not allow him to use his own structure. ACE (Algorithmically Customizable syntax-directed Editor) provides a solution for this problem by using a technique of machine learning; ACE has a special function of customizing the grammar algorithmically and interactively based on the learning method for grammars from examples and queries. The grammar used in the editor is customized through interaction with the user so that the user can edit his program in a more familiar structure. The customizing function has been implemented based on the methods for learning of context-free grammars from structural examples, for which the correctness and the efficiency are proved formally. This guarantees the soundness and the efficiency of customization. Furthermore, ACE can be used as an algorithmic and interactive tool to design grammars, which is required for several purposes such as compiler design and pretty-printer design.

The single fault model is invalid in many cases. However, it is very difficult to generate tests for all multiple faults since an m-line circuit may have 3m --1 multiple faults. In this paper, we describe a method for generating tests for combinational circuits with multiple stuck-at faults. An input vector is a test for a fault on a target line, if it find the target line to be fault-free in the presence of undetected or undetectable lines. The test is called a robust test for fault on a target line. It is shown that the sensitizing input-pair for a completely single sensitized path can be a robust test-pair. The method described here consists of two procedures. We label these as SINGLE_SEN" procedure and DECISION" procedure. SINGLE_SEN generates a single sensitized path including a target line on it by using a PODEM-like method which uses a new seven-valued calculus. DECISION determines by utilizing the method proposed by H. Cox and J. Rajski whether the single sensitizing input-pair generated by the SINGLE_SEN is a robust test-pair. By using these two procedures the described method generates robust test-pairs for the combinational circuit with multiple stuck-at faults. Finally, we demonstrate by experimental results on the ISCAS85 benchmark circuits that SINGLE_SEN is effective for an algorithmic multiple fault test generation for circuits not including many XOR gates.

Hydrogen termination of HF-treated Si surfaces and the oxidation kinetics have been studied by x-ray photoelectron spectroscopy (XPS) and Fourier Transform Infrared Spectroscopy (FT-IR) Attenuated Total Reflection (ATR). The oxidation of hydrogen-terminated Si in air or in pure water proceeds parallel to the surface presumably from step edges, resulting in the layer-by-layer oxidation. The oxide gryowth rate on an Si(100) surface is faster than (110) and (111) when the wafer is stored in pure water. This is interpreted in terms of the steric hindrance against molecular oxygen penetration throughth the (110) and (111) surfaces where the atom void size is equal to or smaller than O2 molecule. The oxide growth rate in pure water for heavily doped n-type Si is significantly high compared to that of heavily doped p-type Si. This is explained by the conduction electron tunneling from Si to absorbed O2 molecule to form the O2- state. O2- ions easily decompose and induce the surface electric field, enhancing the oxidation rate. It is found that the oxidation of heavily doped n-type Si in pure water is effectively suppressed by adding a small amount (1003600 ppm) of HCl.

This letter describes the waveform relaxation algorithm with the dynamic circuit partitioning technique based on the operation point of bipolar devices. Finally, we verify its availability for the simulation of the digital bipolar transistor circuit.

The Asynchronous Transfer Mode (ATM) is expected to be the basic transmission technology for B-ISDN. Before this happens, however, it will be necessary to predict the impact of fully-deployed ATM-based networks quantitatively. This paper compares the cost-efficiency of an ATM-based network with that of an STM-based network and clarifies the applicable areas of ATM network configurations, in terms of required facilities and considering the effect of statistical multiplexing. It shows cost-effective network configurations based on different service classes and a network configuration suited to ATM. It also discusses the effect of a Synchronous Digital Hierarchy architecture for Virtual Path dimensioning.

In this letter, introducing a highly accurate model for a real current mode DC-DC converter, an innovative design strategy is proposed in order to optimize circuit behavior in cases in which chaotic effects are present.

Fourier holographic image storage and reconstruction using BaTiO3 photorefractive crystal waveguide is investigated. The phase conjugation technique, which compensates image distortion caused by modal phase dispersion, successfully retores images stored in a test BaTiO3 crystal waveguide.

In this paper, voltage-input current-output Membership Function Circuit (MFC) and Normalization Locked Loop (NLL) are proposed. They are useful building blocks for the current-mode analog fuzzy hardware. The voltage-input current-output MFC consists of one source coupled type Operational Transconductance Amplifier (OTA). The MFC is used in the input parts of the analog fuzzy hardware system. The fuzzy hardware system can execute the singleton fuzzy control algorithm. In the algorithm, the weighted average operation is processed. When the weighted average operation is directly realized by analog circuits, a divider must be implemented. Here, the NLL circuit, which can process the weighted average operation without the divider, is implemented using one source coupled type OTA. The proposed circuits were designed by using 2 µm CMOS design rules and its operations were confirmed using SPICE simulations.

A dual transformation incorporating the frequency-dependent scaling factor with the impedance dimension is proposed to synthesize the current-mode counterpart of a voltage-mode original. A general class of current-mode active-RC biquadratic filters and a switched-capacitor low-pass biquad are derived to demonstrate the synthesis procedure. Their simulation and test results show that the current transfer functions are the same as the voltage transfer functions of the originals, and thus confirm the validity of the procedure. The dual trasformation described herein is general in that with the scaling factor chosen appropriately it can meet a wide variety of circuit transformation, and thus useful also for circuit classification and identification.

This paper describes the waveform relaxation (WR) algorithm with the under relaxation method based on the virtual state formulation (VSF) technique and the effect of multirate behavior in this algorithm. First, we present the virtual state relaxation method using VSF technique. Next, we introduce the VSF method into WR algorithm in order to exploit the multirate behavior. Furthermore, we construct the relaxation-based circuit simulator DESIRE2 and apply this simulator to the transient analysis of MOS circuits. Finally, we show that the present technique enables to use efficiently the multirate integration method in VSR and reduce the total simulation time without losing the waveform accuracy.

For a realization of a DC-DC converter using no magnetic devices, a new switched capacitor (SC) transformer is introduced, which gives voltage ratios by Fibonacci series corresponding to the stages. This transformer is connected in cascade by each basic block which is assembled by a capacitor and three MOSFET switches. This operates on a simple two-phase clock and has a large step-up or step-down voltage ratio in spite of its simple configuration. The characteristics of this transformer with n stages of basic block are derived and calculated by means of a 4 4 cascade matrix. The optimal arrangement of each stage's capacitances is shown to reduce the SC resistance by about 20%. The simulation results are compared with the characteristics of a prototype transformer with four stages (8 times step-up ratio). Its power efficiency achieves 88% in case of 97 V output voltage, 0.2 A output current, and 100 kHz switching frequency. Lastly, the proposed SC transformer is compared and discussed with other typical SC transformers.

Noise characteristics of InAlAs/InGaAs HEMT's passivated by SiN are investigated to ascertain their suitability for practical applications in circuit such as MMIC's. A 0.18-µm-gate-length device with 125-µm-gate width and 8-gate fingers showed the lowest minimum noise figure of 0.43 dB at 26 GHz with an associated gain of 8.5 dB of any passivated device ever reported. This value is also comparable to the lowest reported minimum noise figure obtained by bare InAlAs/InGaAs HEMT's in spite of increased parasitic capacitances due to the SiN passivation. Thes excellent noise performance was achieved by employing non-alloyed ohmic contact, a T-shaped gate geometry and a multi-finger gate pattern. To reduce the contact resistance of the non-alloyed ohmic contact, a novel n+-InGaAs/n+-InAlAs cap layer was used resulting in a very low contact resistance of 0.09 Ωmm and a low sheet resistance for all layers of 145 Ω/sq. No increase in these resistances was observed after SiN passivation, and a very low source resistance of 0.16 Ωmm was obtained. An analysis of equivalent circuit parameters revealed that the T-shaped gate and multi-finger gate pattern drastically decrease gate resistance.

A new set of self-consistent linear equations is presented for the analysis of the startup characteristics of gyrotron oscillators with an open cavity consisting of weakly irregular waveguides. Numerical results on frequency detuning and oscillation starting current for a whispering-gallery-mode gyrotron are described in which these equations were utilized. Experiments for making a check on the effectiveness of the derived equations showed that they well express the operation of gyrotrons in comparison with the linear theory using an empty cavity field as the wave field.

The outputs of all gates in a circuit are assumed to be observable unber the highly observable condition, which is mainly based on the use of E-beam testers. When using the E-beam tester, it is desirable that the test set for a circuit is small and the test vectors in the test set can be applied in a successive and repetitive manner. For a combinational circuit, these requirements can be satisfied by modifying the circuit into a k-UCP circuit, which needs only a small number of tests for diagnosis. For a sequential circuit, however, even if the combinational portion has been modified into a k-UCP circuit, it is impossible that the test vectors for the combinational portion can always be applied in a successive and repetitive manner because of the existence of feedback loops. To solve this problem, the concept of k-UCP scan circuits is proposed in this paper. It is shown that the test vectors for the combinational portion in a k-UCP scan circuit can be applied in a successive and repetitive manner through a specially constructed scan-path. An efficient method of modifying a sequential circuit into a k-UCP scan circuit is also presented.

A closure test MCT (meet-in-the-middle closure test) has been introduced to analyze the algebraic properties of cryptosystems. Since MCT needs a large amount of memory, it is hard to implement with an ordinary meet-in-the-middle method. As a feasible version of MCT, this paper presents a switching closure test SCT based on a new memoryless meet-in-the-middle method. To achieve the memoryless method, appropriate techniques, such as expansion of cycling detection methods for one function into a method for two functions and an efficient intersection search method that uses only a small amount of memory, are effectively used.

This paper describes a new approach towards the performance-driven layout for analog LSIs. Based on our approach, we developed an automatic performance-driven layout system LIBRA. The performance-driven layout has an advantage that numerical evaluations of performance requirements may exactly specify layout requirements so that a better layout result will be expected with regard to both the size and the performances. As the first step to the final goal, we only concern with the DC characteristics of analog circuits affected by the placement and routing. First of all, LIBRA performs the sensitivity analysis with respect to process parameters and wire parasitics, which are major causes for DC performance deviations of analog LSIs, so as to describe every perfomance deviation by its first order approximation. Based on the estimations of those performance deviations, LIBRA designs the placement of devices. The placement approach here is the simulated annealing method driven by their circuit performance specification. The routing of inter-cell wires is performed according to the priority of the larger total wire sensitivities in the net by the maze router. Then, the simple compaction eliminates the empty space as much as possible. After that, the power lines optimization is performed so as to minimize the ferformance deviations. Finally, an advantage of the performance improvement by our approach is demonstrated by showing a layout result of a practical bipolar circuit and its excellent performance evaluations.

This paper outlines an approach for specifying emissions performance at the component level. The objective is to move towards an industry specification for radiated emissions from large integrated circuits in order to facilitate cost effective system design for EMI compliance. Simple models of the mechanisms of direct chip radiation are provided based on the physical and electrical structure of large integrated circuits. These models lead to simple algorithms for estimating the total IC radiation based on IC design parameters. These models can be related to proposed emissions limits based on the desired application of the IC. Finally a measurement methodology is described which permits evaluation of the IC's relative to the limits and provides the information required to make detailed simulation models.

Mechanism for radiation phenomenon caused by a finite-length transmission line is discussed. Coupling of an external wave to a transmission line has been studied by using a circuit concept because of a TEM transmission. Since the relationship between coupling and radiation is reciprocal, radiation can be treated by using the circuit concept. It is shown that the equations obtained by using the field theory are quite coincident with those by the circuit theory. From the resultant, it can be concluded that the radiated fields are composed of those by the line current of TEM and the terminal currents. A method for an application of the circuit concept to radiation due to a trace on a printed circuit board is studied by comparing the experimental results.