In this paper, we propose an autonomously distributed QoS control method for MPEG video streaming in a wide area network. The capacity of the links and the characteristics of video streams change dynamically. However, managing the condition of all the links and streams in the network is difficult. In the proposed method, the routers in the network monitor the conditions of the links and streams locally and control the transmission rate of the stream server. Picture-quality oriented fairness is achieved by reducing the transmission rate of the streams with the higher PSNR in the bottleneck link. The computer simulation results show that the proposed method can be applied to a wide area network.

This paper introduces a new frame-based bit-rate control scheme for bandwidth-adaptive video coding. Proposed method can accurately adapt to the rapid varying scene characteristics by reducing the number of occurrences of the extrapolations while updating the rate-distortion model used for determine the appropriate quantization steps.

In this paper, we propose an optimal bit rate control algorithm which is fully compatible with MPEG-4 or H.263+. The proposed algorithm is designed to identify the optimal quantizer set through Lagrangian optimization when used for optimal bit allocation. To find the optimal quantizer set, we make use of the Viterbi algorithm in order to solve the dependency between quantization parameters of each macroblock due to the unique characteristics of MPEG-4 or H.263+. We set the Lagrangian cost function as a cost function of the Viterbi algorithm. We implement the proposed algorithm in MPEG-4 coders and compare its performance to the VM8 and optimal bit rate control algorithm, using independent quantization parameters in the circumstance of a low bit rate.

The MPEG-2 Test Model 5 (TM5) algorithm describes a rate control method which consists of three steps: bit allocation, rate control and modulation. In TM5, however, buffer overflow and picture quality degradation may occur at the end of the GOP because the target bits and the actual coding bits for each picture do not match well. This paper presents a new bit rate control algorithm for matching the target and the actual coding bits based on accurate bit allocation. The key idea of the proposed algorithm is to determine quantization parameters which enable us to generate the actual coding bits close to the target bits for each picture, while improving the picture quality. The proposed algorithm exploits the relationship between the number of the actual coding bits and the number of the estimated bits of the previous macroblock within a picture.

This letter presents a novel video and audio PTSs self-adaptive interlace strategy in MPEG-2 transport stream. By adaptive regulating the relative position of audio and video access units in bit-stream according to their PTSs, the proposed strategy provides reliable video and audio synchronization.

The block-based fast transmission scheme, which is one of typical stored video delivery schemes, is reasonable in terms of its bandwidth efficiency and tolerance to the delay jitter, etc. However, it causes packet loss because of its burst data transmission method. Thus, we propose a slotted multicast scheme for MPEG video based on the block transmission scheme to maintain a higher quality and to include time constraints. We define two delivery units, the "GoPs Group" and the "Frame Type," on the basis of the MPEG characteristics with periodical NACK feedback from the clients. The former is tolerant to burst packet loss, and the latter gives priority to important frames. Our block multicast has two phases: a "Transmission Phase" and a "Retransmission Phase." In the former, a server multicasts a block, and in the latter, a server retransmits lost packets using multicast according to the proper delivery unit. We evaluate our proposal from some viewpoints with a computer simulation. We also measure the quality of the video reflected the result of a computer simulation. From these results, we confirm performance effectiveness of our proposal.

A method of scrambling MPEG video by exchanging the motion vector (MV) in the MPEG bitstream is proposed. It deals directly with the MPEG bitstream and exclusive MPEG encoders are unnecessary. The size of the scrambled bitstream does not increase and image quality is maintained after descrambling. Moreover, the structure of the MPEG bitstream is maintained and can be decoded with a standard MPEG video decoder. We demonstrate the effectiveness of this method through simulation results that reveal unchanged image quality and size of bitstreams.

A method for automatic and fast shot detection for the MPEG video is proposed. Shot detection is the first step in analyzing and searching a large amount of video data. Our proposed method is based on activity of images as well as intra MBs in the video frame. It is possible to detect scene changes rapidly by using information from the compressed MPEG video data without the need for full-frame decoding. Experimental results show that the proposed method can provide good performance at a low computational cost.

A single chip processor suitable for various multimedia communication products has been developed. This chip achieves real-time bi-directional encoding/decoding for CIF resolution video at a frame rate of 30 fr/s, and meets such standards, as H.320 and H.324. The chip is composed of a video-processing unit for MPEG-4 and H.26X standards, a DSP unit for speech codec and multiplex processes, and a RISC unit for managing the whole chip. By heterogeneous multiple processor architecture, careful study of task sharing for each processing unit and bus configuration, a single chip solution can be achieved with reasonable operation speed and low-power consumption suitable for consumer products. Moreover, by applying an original video processing unit architecture, this chip achieves real-time bi-directional encoding/decoding for CIF-resolution video at a frame rate of 30 fr/s. An original video bus was developed to provide high performance and low-power consumption while sharing one external memory which is necessary for various video processes and graphics functions. This shared memory also has the effect of minimizing die size and I/O ports. This chip has been fabricated with 4-metal 0.18 µm CMOS technology to produce a chip area of 10.510.5 mm2 with 1.2 W power dissipation including I/O power, at 1.8 V for internal supply and 3.3 V for I/O power supply.

This paper describes a VLSI-oriented motion estimation algorithm using a steepest descent method (SDM) applied to MPEG-4 visual communication with a mobile terminal. The SDM algorithm is optimized for QCIF or CIF resolution video and VLSI implementation. The SDM combined with a subblock search method is developed to enhance picture quality. Simulation results show that a mean PSNR drop of the SDM algorithm processing QCIF 15 fps resolution video in comparison with a full search algorithm is -0.17 dB. Power consumption of a VLSI based on the SDM algorithm assuming 0.18 µm CMOS technology is estimated at 2 mW. The VLSI attains higher picture quality than that based on the other fast motion estimation algorithm, and is applicable to mobile video applications.

In this paper, we describe a feed-forward dynamic voltage/clock-frequency control method enabling low power MPEG4 on multi-regulated voltage CPU with combining the characteristics of the CPU and the video encoding processing. This method theoretically achieves minimum low power consumption which is close to the hardware-level power consumption. Required processing performance for MPEG4 visual encoding totally depends on the activity of the sequence, and high motion sequence requires high performance and low motion sequence requires low performance. If required performance is predictable, lower power consumption can be achieved with controlling the adequate voltage and clock-frequency dynamically at every frame. The proposed method in this paper is predicting the required processing performance of a future frame using our unique feed-forward analysis method and controlling a voltage and frequency dynamically at every frame along with the forward analysis value. The simulation results indicate that the proposed feed-forward analysis method adequately predicts the required processing performance of every future frame, and enables to minimize power consumption on software basis MPEG4 visual encoding processing. In the case that CPU has Frequency-Voltage characteristics of 1.8 V @400 MHz to 1.0 V @189 MHz, the proposed method reduces the power consumption approximately 37% at high motion sequences or 65% at low motion sequences comparing with the conventional software video encoding method.

In this paper, we propose a dynamic bit-rate reduction scheme for transcoding an MPEG-1 bitstream into an MPEG-4 simple profile bitstream with a typical bit-rate of 384 kbps. For dynamic bit-rate reduction, a significant reduction in the bit-rate is achieved by combining the processes of requantization and frame-skipping. Conventional requantization methods for a homogeneous transcoder cannot be used directly for a heterogeneous transcoder due to the mismatch in the quantization parameters between the MPEG-1 and MPEG-4 syntax and the difference in the compression efficiency between MPEG-1 and MPEG-4. Accordingly, to solve these problems, a new requantization method is proposed for an MPEG-1 to MPEG-4 transcoder consisting of R-Q (rate-quantization) modeling with a simple feedback and an adjustment of the quantization parameters to compensate for the different coding efficiency between MPEG-1 and MPEG-4. For bit-rate reduction by frame-skipping, an efficient method is proposed for estimating the relevant motion vectors from the skipped frames. The conventional FDVS (forward dominant vector selection) method is improved to reflect the effect of the macroblock types in the skipped frames. Simulation results demonstrated that the proposed method combining requantization and frame-skipping can generate a transcoded MPEG-4 bitstream that is much closer to the desired low bit-rate than the conventional method along with a superior objective quality.

We present a single-chip MPEG-4 audiovisual LSI in a 0.13 µm CMOS, 5-layer metal technology with 16 Mbit embedded DRAM, which integrates four 16 bit RISC and dedicated hardware accelerators including a 5 GOPS post filtering unit. It consumes 160 mW at 125 MHz and dissipates 80 nA in the standby mode. The chip is the world first LSI handling MPEG-4 CIF video encoding at 15 frames/sec and audio/speech encoding simultaneously.

Although watermarking techniques have been extensively developed for natural videos, little progress is made in the area of graphics animation. Following the former successful MPEG-1 and MPEG-2 coding standards that provide efficient representations of natural videos, the emerging MPEG-4 standard incorporates new coding tools for 2D mesh animation. Graphics animation information is crucial for many applications and may need proper protection. In this paper, we develop a watermarking technique suitable for MPEG-4 2D mesh animation. The proposed method is based on the multiresolution analysis of 2D dynamic mesh. We perform wavelet transform on the temporal sequence of the node points to extract the significant spectral components of mesh movement, which we term the "feature motions. " A binary watermark invisibly resides in the feature motions based on the spread-spectrum principle. Before watermark detection, a spatial-domain least-squares registration technique is used to restore the possibly geometrically distorted mesh data. Each watermark bit is then detected by hard decision with cryptographically secure keys. We have tested the proposed method with a variety of attacks, including affine transformations, temporal smoothing, spectral enhancement and attenuation, additive random noise, and a combination of the above. Experimental results show that the proposed watermarks can withstand the aforementioned attacks.

Video transmission over Terrestrial Trunked Radio (TETRA) mobile channel employing MPEG-4 visual coding standard is proposed in this paper. Detail parameters of the proposed systems are discussed in this paper. Performance of the proposed systems was evaluated in Average Peak Signal to Noise Ratio (APSNR) versus Signal to Noise Ratio (SNR) and Bit Error Rate (BER). In particular, the video quality that can be achieved at different channel conditions and employing different combinations of MPEG-4 visual error resilient tools is presented in this paper. Results obtained show that higher video bitrate does not necessarily lead to higher video quality at the receiver as the received video quality depends on the bit error pattern or the number of error free video packets.

We propose an efficient motion estimation algorithm to search an additional area according to the motion of a camcorder, which is obtained from a gyro sensor. When the camcorder moves, the background moves in the opposite direction. The proposed algorithm searches three regions, one around the center, another around the predicted region and another in the background around the region associated with the camcorder motion. Compared to conventional algorithms without the last region, the proposed one reduces the amount of computation to 1/5 while maintaining or enhancing the quality.

This paper presents a novel digit-level algorithm for motion estimation (ME) and its hardware implementations. It uses the most-significant-digit-first (MSD-first) processing and on-line arithmetic ME components. A dedicated array architecture is also proposed for applications with high-throughput ME. Various fast search algorithms were presented in literatures to reduce the complexity but sacrifice the motion vector (MV) quality. Our MSD-first ME decomposes the summation of absolute differences (SAD) and comparison operations to digit level with MSD-plane first. These comparisons are interleaved into SADs to distinguish the MV as soon as possible. The algorithm precisely extracts the impossible candidates and removes their rest operations. It saves 47.4 % to 64.3 % of SAD computations in full search block matching (FSBM) ME. In the past, the high implementation cost of redundant number system prevented the practical use of on-line arithmetic. Besides, the redundant SAD removal results in irregular data flow in system-level integration. All these problems are solved by our novel architecture design. In this paper, we propose novel architecture designs to solve these problems. Besides, the architecture requires only one memory access per pixel to lower memory bandwidth by extensive data parallelism and a particular memory addressing while keeping the controller simple. A 4 4 array processor is implemented in 0.35 µm 1P4M CMOS cell library, with 2.84 ns cycle time and 1510 gates. It can support 83 M FSBM operations per second. After normalization, our implementation can support 2.67 times SAD operations per unit area (estimated in gate count) of the conventional two's complement ones. MSD-first ME can realize with other ME algorithms to improve the performance as well.

A low power MPEG-4 video codec LSI with the capability for core profile decoding is presented. A 16-b DSP with a vector pipeline architecture and a 32-b arithmetic unit, eight dedicated hardware engines to accelerate MPEG-4 SP@L1 codec, CP@L1 decoding and post video processing, 20-Mb embedded DRAM, and three peripheral blocks are integrated together on a single chip. MPEG-4 SP@L1 codec, CP@L1 decoding and post video processing are realized with a hybrid architecture consisting of a programmable DSP and dedicated hardware engines at low operating frequency. In order to reduce the power consumption, clock gating technique is fully adopted in each hardware block and embedded DRAM is employed. The chip is implemented using 0.18-µm quad-metal CMOS technology, and its die area is 8.8 mm 8.6 mm. The power consumption is 90 mW at a SP@L1 codec and 110 mW at a CP@L1 decoding.

The proxy mechanism widely used in WWW systems offers low-delay data delivery by means of "proxy server." By applying proxy mechanisms to video streaming system, we expect that high-quality and low-delay video distribution can be accomplished without introducing extra load on the system. In addition, it is effective to adapt the quality of cached video data appropriately in the proxy if user requests are diverse due to heterogeneity in terms of the available bandwidth, end-system performance, and user's preferences on the perceived video quality. In this paper, we propose proxy caching mechanisms to accomplish high-quality and low-delay video streaming services. In our proposed system, a video stream is divided into blocks for efficient use of cache buffer. A proxy cache server is assumed to be able to adjust the quality of cached or retrieved video blocks to requests through video filters. We evaluate our proposed mechanisms in terms of the required buffer size, the play-out delay and the video quality through simulation experiments. Furthermore, to verify the practicality of our mechanisms, we implement our proposed mechanisms on a real system and conducted experiments. Through evaluations from several performance aspects, it is shown that our proposed mechanisms can provide users with a low-latency and high-quality video streaming service in a heterogeneous environment.

In this paper, we present a design of MPEG-4 video codec chip to reduce the power consumption using frame level clock gating, macro block level and motion estimation skip scheme. It performs 30 frames/s of codec (encoding and decoding) mode with quarter-common intermediate format (QCIF) at 27 MHz. Power consumption is 290 mW at 27 MHz operation, which is achieving 35% power saving compared to a conventional CMOS. Motion Estimation skip method is employed to reduce 32% computation load. This chip performs MPEG-4 Simple Profile Level 2 (Simple@L2) and H. 263 base mode. Its contains 388,885 gates, 662 k bits memory, and the chip size was 9.7 mm9.7 mm which was fabricated using 0.35 micron 3-layers metal CMOS technology.