We developed programmable high-performance and high-speed neurocomputer for a large neural network using ASIC neurocomputing chips made by CMOS VLSI technology. The neurocomputer consists of one master node and multiple slave nodes which are connected by two data paths, a broadcast bus and a ring bus. The nodes are made by ASIC chips and each chip has plural nodes in it. The node has four types of computation hardware that can be cascaded in series forming a pipeline. Processing speed is proportional to the number of nodes. The neurocomputer is built on one printed circuit board having 65 VLSI chips that offers 1.5 billion connections/sec. The neurocomputer uses SIMD for easy programming and simple hardware. It can execute complicated computations, memory access and memory address control, and data paths control in a single instruction and in a single time step using the pipeline. The neurocomputer processes forward and backward calculations of multilayer perceptron type neural networks, LVQ, feedback type neural networks such as Hopfield model, and any other types by programming. To compute neural computation effectively and simply in a SIMD type neurocomputer, new processing methods are proposed for parallel computation such as delayed instruction execution, and reconfiguration.

The generation mechanism for excess intensity noise due to optical feedback is analyzed theoretically and experimentally. Modal rate equations under the weakly coupled condition with external feedback are derived to include the mode competition phenomena in DFB and Fabry-Perot lasers. We found that the sensitivity of the external feedback strongly depends on design parameters of structure, such as the coupling constant of the corrugation, the facet reflection and the phase relation between the corrugation and the facet. A DFB laser whose oscillating wavelength is well adjusted to Bragg wavelength through insertion of a phase adjustment region becomes less sensitive to external optical feedback than a Fabry-Perot laser, but other types of DFB lasers revealing a stop band are more sensitive than the Fabry-Perot laser.

Recently, studies aiming at the next generation of visual communication services which support better human communication have been carried out intensively in Japan. The principal motive of these studies is to develop new services which are not restricted to a conventional communication framework based on the transmission of waveform signals. This paper focuses on three important key words in these studies; "intelligent," "real," and "distributed and collaborative," and describes recent research activities. The first key word "intelligent" relates to intelligent image coding. As a particular example, model-based coding of moving facial images is discussed in detail. In this method, shape change and motion of the human face is described by a small number of parameters. This feature leads to the development of new applications such as very low bit-rate transmission of moving facial images, analysis and synthesis of facial expression, human interfaces, and so on. The second key word "real" relates to communication with realistic sensations and virtual space teleconferencing. Among various component technologies, real-time reproduction of 3-D human images and a cooperative work environment with virtual space are discussed in detail. The last key word "distributed and collaborative" relates to collaborative work in a distributed work environment. The importance of visual media in collaborative work, a concept of CSCW, and requirements for realizing a distributed collaborative environment are discussed. Then, four examples of CSCW systems are briefly outlined.

The main result of this paper is an almost-everywhere hierarchy theorem for nondeterministic space that is as tight as the well-known infinitely-often hierarchy theorems for deterministic and nondeterministic space. In addition, we show that the complexity-theoretic notion of almost-everywhere complex functions is identical to the recursion-theoretic notion of bi-immune sets in the nondeterministic space domain. Finally, we investigate bi-immunity in nondeterministic and alternating time complexity classes and derive a similar hierarchy result for alternating time.

By a measure we mean a function µ from {0, 1}* (the set of all binary sequences) to real numbers such that µ(x)0 and µ({0, 1}*). A malign measure is a measure such that if an input x in {0, 1}n (the set of all binary sequences of length n) is selected with the probability µ(x)/µ ({0, 1}n) then the worst-case computation time tWOA (n) and the average-case computation time tav,µA(n) of an algorithm A for inputs of length n are functions of n of the same order for any algorithm A. Li and Vitányi found that measures that are known as a priori measures are malign. We prove that a priori" -ness and malignness are different in one strong sense.

The hierarchies of multihead finite automata over a one-letter alphabet are investigated. Let SeH(k) [NSeH(k) ] denote the class of languages over a one-letter alphabet accepted by deterministic [nondeterministic] sensing two-way k-head finite automata. Let H (k)s[NH(k)s] denote the class of sets of square tapes over a one-letter alphabet accepted by two-dimensional four-way deterministic [nondeterministic] k-head finite automata. Let SeH(k)s[NSeH(k)s] denote the class of sets of square tapes over a one-letter alphabet accepted by two-dimensional four-way sensing deterministic [nondeterministic] k-head finite automata. This paper shows that SeH(k) SeH(k1) and NSeH(k) NSeH(k1) hold for all k3. It is also shown that H(k)s[NH(k)s] H(k1)s[NH (k1)s] and SeH (k)s[NSeH(k)s] SeH(k1)s[NSeH(k1)s] hold for all k1.

A cyclic analog-to-digital (A/D) converter is developed which accomplishes an n-b conversion in n/2 clock cycles. The architecture consists of two 1-b quantizers connected in a loop. A CMOS design of the 1-b quantizer is given to evaluate the performance of the A/D converter when implemented using presently available process. Spice simulations and error analyses show that a resolution higher than 10-b and a sampling rate up to 1.4 Msps are attainable with a 3-µm CMOS process. A prototype converter breadboarded using discrete components has confirmed the principles of operation and error analyses. The device count and the power consumption are small compared to those of a successive-approximation A/D converter. A chip area required for the CMOS implementation is also small because only four unit capacitors are involved. Therefore, the architecture proposed herein is most suited for high accuracy, medium speed A/D conversion.

The performance of analog circuits is strongly influenced by their layout. Performance specifications are usually translated into physical constraints such as symmetry, common orientation, and distance constraints among certain components. Automatic digital layout tools can be adopted and modified to deal with the imposed performance constraints on the analog layout. The selection and modifications of algorithms to handle the analog constraints became the area of research in analog layout systems. The existing systems are characterized by the use of stochastic optimization techniques based placement, grid based or channel routers, and lack of compaction. In this paper, algorithms for analog circuit placement, routing, and compaction are presented. The proposed algorithms consider the analog oriented constraints, which are important from an analog layout point of view, and reduce the computation cost. The placement algorithm is based on a force directed method and consists of two main phases, each of which includes a tuning procedure. In the first phase, we solve a set of simultaneous linear equations, based upon the attractive forces. These attractive forces represent the interconnection topology of given blocks and some specified constraints. Symmetry constraint is considered throughout the tuning procedure. In the second phase, block overlap resulting from the first phase is resolved iteratively, where each iteration is followed by the symmetry tuning procedure. Routing is performed using a line expansion based gridless router. Routing constraints are taken into account and several routing priorities are imposed on the nets. The compactor part employs a constraint graph based algorithm while considering the analog symmetry constraints. The algorithms are implemented and integrated within an analog layout design system. An experimental result for an OP AMP provided by MCNC benchmark is shown to demonstrate the performance of the algorithms.

We describe an approach for modelling a person's face for model-based coding. The goal is to estimate the 3D shape by combining the contour analysis and shading analysis of the human face image in order to increase the quality of the estimated 3D shape. The motivation for combining contour and shading cues comes from the observation that the shading cue leads to severe errors near the occluding boundary, while the occluding contour cue provides incomplete surface information in regions away from contours. Towards this, we use the deformable model as the common level of integration such that a higher-quality measurement will dominate the depth estimate. The feasibility of our approach is demonstrated using a real facial image.

A novel sampling comparator circuit is presented for extending the pull-in range of microwave phase-locked oscillators (PLOs). It performs both phase and frequency detection without any frequency dividers, and a GaAs MMIC prototype is developed and tested. The proposed comparator improves the pull-in range by about 10 times more than is possible with conventional sampling phase detectors.

The self-organization rule of planar neural networks has been proposed for learning of 2D distributions. However, it cannot be applied to 3D objects. In this paper, we propose a new model for global representation of the 3D objects. Based on this model, global topology reserving self-organization is achieved using parallel local competitive learning rule such as Kohonen's maps. The proposed model is able to represent the objects distributively and easily accommodate local features.

This paper describes new methematical tools, taken from quantum field theory (QFT), which may make it possible to characterize localized excitations (including solitons, but also including chaotic modes) generated by PDE systems. The significance to computer hardware and neurocomputing is also discussed. This mathematics--IF further developed--may also have the potential to reorganize and simplify our understanding of QFT itself--a topic of very great intellectual and practical importance. The paper concludes by describing three new possibilities for research, which will be very important to achieving these goals.

A new computer architecture using multiwavelength optoelectronic integrated circuits (OEICs) is proposed to attack the problems caused by interconnection complexity. Multiwavelength-OEIC architecures, where various wavelengths are employed as information carriers, provide the wavelength as an extra dimension of freedom for parallel processing, so that we can perform several independent computations in parallel in a single optical module using the wavelength space. This multiplex computing" enables us to reduce the wiring area required by a network and improve their complexity. In this paper, we discuss the efficient multiplexing of Batcher's bitonic sorting networks, highly parallel computing architectures that require global interconnections inherently. A systematic multiplexing of interconnection topology is presented using a binary representation of the connectivities of interconnection paths. It is shown that the wiring area can be reduced by a factor of 1/r2 using r kinds of wavelength components.

The problem of local minima is inevitable when solving combinatorial optimization problems by conventional methods such as the Hopfield network, relying on the minimization of an objective function E(X). Such a problem arises from the search mechanism in which only the local information about the objective function E(X) is used. In this paper we propose a new approach called the Single Minimum Method (SMM) which uses the global information in searching for the solutions to combinatorial optimization problems. In this approach, we add a function -TS(X) to the original objective function E(X) to construct the function F(X)=E(X)-TS(X) which has only one minimum, one which can be easily found by any general gradiet method including the Hopfield network. Based on an analogy between thermodynamic systems and neural networks, it is shown that the global information about the original objective function E(X) is included in the single minimum of the function F(X) and can be used for finding the global minimum of the objective function E(X). In order to show how to apply the Single Minimum Method to a combinatorial optimization problem we give an algorithm for the TSP problem based on our method. The simulation results show that the algorithm can almost always find the shortest or near shortest paths. Finally, a modified SMM, which has some great advantages for hardware implementation, is also given.

A priori estimation is presented for a computational complexity of the homotopy method applying to a certain class of strongly monotone nonlinear equations. In the present papers, a condition is presented for a certain class of uniquely solvable equations, under which an upper bound of a computational complexity of the Newton type homotopy method can be a priori estimated. In this paper, a condition is considered in a case of linear homotopy equations including the Newton type homotopy equations. In the first place, the homotopy algorithm based on the simplified Newton method is introduced. Then by using Urabe type theorem, which gives a sufficient condition guaranteeing the convergence of the simplified Newton method, a condition is presented under which an upper bound of a computational complexity of the algorithm can be a priori estimated, when it is applied to a certain class of strongly monotone nonlinear equations. The presented condition is demonstrated by numerical experiments.

An idea of optimal output permutation of multiple-valued sum-of-products expressions is presented. The sum-of-products involve the TSUM operator on the MIN of window literal functions. Some bounds on the maximum number of implicants needed to cover an output permuted function are clarified. One-variable output permuted functions require at most p1 implicants in their minimal sum-of-products expressions, where p is the radix. Two-variable functions with radix between three and six are analyzed. Some speculations of maximum number of the implicants could be established for functions with higher radix and more than 2-variables. The result of computer simulation shows that we can have a saving of approximately 15% on the average using permuting output values. Moreover, we demonstrate the output permutation based on the output density as a simpler method. For the permutation, some speculation is shown and the computer simulation shows a saving of approximately 10% on the average.

Design of locally computable combinational circuits is a very important subject to implement high-speed compact arithmetic and logic circuits in VLSI systems. This paper describes a multiple-valued code assignment algorithm for the locally computable combinational circuits, when a functional specification for a unary operation is given by the mapping relationship between input and output symbols. Partition theory usually used in the design of sequential circuits is effectively employed for the fast search for the code assignment problem. Based on the partition theory, mathematical foundation is derived for the locally computable circuit design. Moreover, for permutation operations, we propose an efficient code assignment algorithm based on closed chain sets to reduce the number of combinations in search procedure. Some examples are shown to demonstrate the usefulness of the algorithm.

This paper presents Bi-CMOS current-mode multiple valued logic circuit with 1.5 V supply voltage. This circuit is composed of current mirror, threshold detector and current source. This circuit has advantages such as high accuracy, high speed, high density and low supply voltage. So, it is possible to realize high-radix multiple valued logic circuit. As an other application of the proposed circuit, a processing unit of fuzzy inference is given. This circuit operates with high speed and high accuracy. The circuit simulation of the proposed circuit has been performed using SPICE2 program.

With increases in frequency and density of RISC microprocessors due to rapid advances in architecture, circuit and fine device technologies, power consumption becomes a bigger concern. Supply voltage should be reduced from 5 V to 3.3 V. In this paper, several novel circuits using 0.5µm BiCMOS technology are proposed. These can be applied to a superscalar RISC microprocessor at 3.3 V power supply or below. High speed and low power consumption characteristics are achieved in a floating-point data path, an integer data path and a TLB by using the proposed circuits. The three concepts behind the proposed high speed circuit techniques at low voltage are summarized as follows. There are a number of heavy load paths in a microprocessor, and these become critical paths under low voltage conditions. To achieve high speed characteristics under heavy load conditions without increasing circuit area, low voltage swing operation of a circuit is effective. By exploiting the high conductance of a bipolar transistor, instead of using an MOS transistor, low swing operation can be got. This first concept is applied to a single-ended common-base sense circuit with low swing data lines in the register file of a floating and an integer data path. Both multi-series transistor connections and voltage drops by Vth of MOS transistors and Vbe of bipolar transistors also degrade the speed performance of a circuit. Then the second concept employed is a wired-OR logic circuit technique using bipolar transistors which is applied to a comparator in the TLB instead of multi-series transistor connections of CMOS circuits. The third concept to overcome the voltage drops by Vth and Vbe is addition of a pull up PMOS to both the path logic adder and the BiNMOS logic gate to ensure the circuits have full swing operation.

We describe an approach to describe moving pictures in terms of their structural properties for video editing, video indexing, and video coding. The description contains 2D shape, motion, spatial relation, and relative depth of each region. To obtain the description, we develop the incremental segmentation scheme which includes dynamic occlusion analysis to determine relative depths of several objects. The scheme has been designed along the analysis-by-synthesis" approach, and uses a sequence of images to estimate object boundaries and motion information successively/incrementally. The scheme consists of three components: motion estimation, prediction with dynamic occlusion analysis, and update of the segmentation results. By combining the information from extended (longer) image sequences, and also by treating the segmentation and dynamic occlusion analysis simultaneously, the scheme attempts to improve successively over time the accuracy of the object boundary and motion estimation.