A stored channel simulator for digital mobile radio enviroments is proposed, which enables the field tests in the laboratory under identical conditions, since it can reproduce the actual multipath radio channels by using the channel impulse responses (CIR's) measured in the field. Linear interpolation of CIR is introduced to simplify the structure of the proposed simulator. The performance of the proposed simulator is confirmed by the laboratory tests.

This paper describes a planning method for ATM networks. The method is based on evaluation of two design items, VC routing and VP routing, as well as on consideration of VPI constraints. In the evaluation, VC routing is compared with VP routing in separate case studies undertaken from the point of view of various parameters such as traffic volume, cost function and network scale. The results suggest the vertical relationship between VC and VP levels in optimally designed ATM networks. VC and VP network levels are then studied separately, and design methods are proposed for individual levels. In addition a perturbation method is proposed for the VC and VP routing use, whose optimum is varied as a function of the parameters described above. Evaluation results show the proposed perturbation method provides cost-effective networks.

This paper describes a novel method to calculate the fields scattered by a polyhedron structure for an incident plane wave. In this method, the fields diffracted by an edge are calculated using the equivalent edge currents which are separated into components dependent on each of the two surfaces which form the edge. The separated equivalent edge currents are based on the Geometrical Theory of Diffraction (GTD). Using this Separated Equivalent Edge Current Method (SEECM) , fields scattered by a polyhedron structure can be calculated without special treatment of the singularity in the diffraction coefficient. This method can be also applied successfully to structures with convex surfaces by modeling them as polyhedron structures.

The emerging discipline of responsive systems demands fault-tolerant and real-time performance in uniprocessor, parallel, and distributed computing environments. The new proposal for responsiveness measure is presented, followed by an introduction of a model for responsive computing. The model, called CONCORDS (CONsensus/COmputation for Responsive Distributed Systems), is based on the integration of various forms of consensus and computation (progress or recovery). The consensus tasks include clock synchronization, diagnosis, checkpointing scheduling and resource allocation.

We deal with a new type ceramic emitter which is used in a cleanroom ionizer system and is composed of a needle-shaped silicon and a rod-shaped silicon carbide ceramics. The discharge test was carried out to investigate the particle generation from the emitter and the degradation of the emitter. As a result, it was found that the ceramic emitter had practically higher performance than a conventional tungsten emitter.

Material research on capacitor dielectrics for DRAM applications is reviewed. The state of the art technologies to prepare Si3N4,Ta2O5, and SrTiO3 thin films for capacitors are described. The down-scaling limits for Si3N4 and Ta2O5 capacitors seem to be 3.5 and 1.5 nm SiO2 equivalent thickness, respectively. Combined with a rugged polysilicon electrode surface,Si3N4 and Ta2O5 based-capacitors are available for 256 Mbit and 1 Gbit DRAMs. At the present time, the minimum SiO2 equivalent thickness for high permittivity materials is around 1 nm with the leakage current density of 10-7 A/cm2. Among the great variety of ferroelectrics, two families of materials,i.e., Pb (Zr, Ti) O3 and (Ba, Sr) TiO3 have emerged as the most promising candidates for 1 Gbit DRAMs and beyond. If the chemical vapor deposition technology can be established for these materials, capacitor dielectrics should not be a limiting issue for Gbit DRAMs.

In this paper, an exact algorithm for finding minimum test set which detects all testable stuck-at faults of a given combinational circit is presented. So far several heuristic algorithms for this problem are proposed, but no efficient exact algorithms are known. To solve this exactly, minimum test set problem is formalized as a minimum set covering problem, and then implicit manipulation technique using binary decision diagrams(BDDs) is applied. The algorithm presented in the paper has two contributions. One is utilization of maximal compatible fault set, which can drastically reduce the number of candidates for minimum test set. A new BDD based algorithm for extracting all maximal compatible fault sets is shown. The other is a new implicit manipulation technique handling with huge covering matrix. Actually, the algorithm using this technique can handle minimum set covrering problem with over ten thousand columns in a few minutes. Experiments using ISCAS benchmark circuits show that the algorithm is quite efficient for small(100-300 gates) circuits. A computational complexith of minimum test set problen is much higher than that of ordinary test pattern generation problem, so that practical signifcance of this method is not high. But the algorithm is still useful for evaluation of other heuristic algorithms. furthermore, this implicit manipulation technique can also be applied to other minimumset covering problems.

High performances of CMOS/SOI inverter by simulations of analytical model, reducing the poly-Si gate thickness (tm), and experiments are verified and proposed. It is shown that the tm and gate oxide thickness(tox) are correlated to gate fringing capacitance, which largely influences on the Propagation Delay Time(TPD). Contributions of gate fringing capacitance to CMOS/SIMOX inverter time delay in deep submicrometer gate devices are propounded. Measurements of the fifty-one stage ring oscillator's TPDs are completed for comparison with analytical model. Simulation results by the analytical model, including Time-Dependent Gate Capacitance (TDGC) model, agree well with the experimental results at the same conditions. Simulation results are also predicted that SOI technology is promising for speed enhancement by reducing the poly-Si gate thickness, while the tox remains constant. It is concluded that the TPDs by reducing the tm to zero are improved up to about two times faster than typically fabricated ring oscillator at 350 nm of the tm in deep-submicrometer gate CMOS/SIMOX inverters at room temperature.

An analysis of wave guidance by surface-relief grating waveguides is presented for the case of oblique propagation. This analysis is based on the first-order differential equations expressing the coupling of the space harmonics and an improved differential method is applied to solve the equations in the grating region with arbitrary profile. The propagation constants are calculated for isotropic grating waveguids with sinusoidal profile and the calculated results indicate that the accurate solutions can be obtained by increasing the number of expansion terms and the number of segments. Moreover, this method is extended to the case of the analysis of obliquely propagating waves and it is shown that peculiar leaky waves and stop bands appear owing to the coupling between TE and TM waves.

We propose a third-order low-pass notch filter realized by a single operational amplifier and a minimum number of equal-valued capacitors. As a design example we realize a Chebyshev filter with a ripple of 0.5 dB and it is shown that the experiment result is very good.

We present an extension of the previously proposed 3-layer feedforward network called a cascaded network. Cascaded networks are trained to realize category classification employing binary input vectors and locally represented binary target output vectors. To realize a nonlinearly separable task the extended cascaded network presented here is consreucted by introducing high order cross producted inputs at the input layer. In the construction of the cascaded network, two 2-layer networks are first trained independently by delta rule and then cascaded. After cascading, the intermediate layer can be understood as a hidden layer which is trained to attain preassigned saturated outputs in response to the training set. In a cascaded network trained to categorize binary image patterns, saturation of hidden outputs reduces the effect of corrupted disturbances presented in the input. We demonstrated that the extended cascaded network was able to realize a nonlinearly separable task and yielded better generalization ability than the Backpropagation network.

To derive blood flow dynamics from cineangiograms (CAG), we have developed an image processing algorithm to estimate a two-dimensional blood fiow velocity map projected on CAG. Each image area of CAG is diveded into blocks, and it is assumed that the movement of the contrast medium between two serial frames is restricted only to adjacent blocks. By this assumption, a fundamental equation" and the maximum flow constraints" are derived. The equation and constraints state the relationship between the volume of contrast medium in each block and the flow components" that are the volumes of contrast medium flowing from/to its adjacent blocks. The initial guess" that is a set of approximately obtained flow components is corrected using these relationships. The corrected flow components are then transformed into blood flow velocities, which are illustrated in the form of a needle diagram. In numerical experiments, the estimation error between the real flow velocity generated artificially and the flow velocity estimated with our algorithm was evaluated under one of the worst conditions. Although the maximum error was fairly large, the estimated flow velocity map was still acceptable for visual inspection of flow velocity pattern. We then applied our algorithm to an abdominal CAG (clinical data). The results showed flow stagnation and reverse flow in the abdominal aneurysm, which are consistent with the presence of a thrombus in the aneurysm. This algorithm may be a useful diagnostic tool in the assessment of vascular disease.

Since its successful launch in February of 1992, the Japan Earth Resources Satellite-1 (JERS-1) has been sending back high resolution images of the earth for various studies, including the investigation of earth resources, the preservation of environments and the observation of coastal lines. Currently, received images are processed using the Earth Resources Satellite Data Information System (ERSDIS). The ERSDIS is a high speed image processing system utilizing an extended cellular array processor as its main processing module. The extended cellular array processor (CAP), consisting of 4096 processing elements configured into a two-dimensional array, is designed to have many parallel processing optimizing capabilities targetting large-scale image processing at a high speed. This paper desctribes a typical image processing flow, the structure of the ERSDIS, and the details of the CAP design.

This letter presents an algorithm named SPM which generates test patterns for single stuck-at faults in synchronous sequential circuits based on a product machine traversal method. The new idea presented in this letter is partitioned image computation combined with a mixed breadth-first/depth-first search. Image computation is carried out in partitioned manner by substituting constant logical values to some input variables. This brings about significant reduction in storage requirement during image computation. A test generator based on SPM achieved 100% fault efficiency for the ISCAS'89 benchmark circuits with not more than 32 flip-flops.

As RAMs become dense, their reliability reduces because of complex interactions between memory cells and soft errors due to alpha particle radiations. In order to rectify this problem, RAM manufacturers have started incorporating on-chip (built-in) ECC. In order to minimize the area overhead of on-chip ECC, the same technology is used for implementing the check bits and the information bits. Thus the check bits are exposed to the same failure modes as the information bits. Furthermore, faults in the check bits will manifest as uncorrectable multiple errors when a soft error occurs. Therefore it is important to test the check bits for all failure modes expected of other cells. In this paper, we formulate the problem of testing RAMs with on-chip ECC capability. We than derive necessary and sufficient conditions for testing the check bits for arbitrary and adjacent neighborhood pattern sensitive faults. We also provide an efficient solution to test a memory array of N bits (including check bits) for 5-cell neighborhood pattern sensitive faults in O (N) reads and writes, with the check bits also tested for the same fault classes as the information bits.

This paper proposes a scheme that offers robust extraction of target images in standard view from input facial images, in order to realize accurate and automatic identification of human faces. A standard view for target images is defined using internal facial features, i.e., the two eyes and the mouth, as steady reference points of the human face. Because reliable detection of such facial features is not an easy task in practice, the proposed scheme is characterized by a combination of two steps: first, all possible regions of facial features are extracted using a color image segmentation algorithm, then the target image is selected from among the candidates defined by tentative combination of the three reference points, through applying the classification framework using the sub-space method. Preliminary experiments on the scheme's flexibility based on subjective assessment indicate a stability of nearly 100% in consistent extraction of target images in the standard view, not only for familiar faces but also for unfamiliar faces, when the input face image roughly matches the front view. By combining this scheme for normalizing images into the standard view with an image matching technique for identification, an experimental system for identifying faces among a limited number of subjects was implemented on a commercial engineering workstation. High success rates achieved in the identification of front view face images obtained under uncontrolled conditions have objectively confirmed the potential of the scheme for accurate extraction of target images.

This paper describes a new algorithm for finding the contours of a moving object in an image sequence. A distinctive feature of this algorithm is its complete bottom-up strategy from image data to a consistent contour description. In our algorithm, an input image sequence is immediately converted to a complete set of quasi logical spatio-temporal measures on each pixel, which provide constraints on varying brightness. Then, candidate regions in which to localize the contour are bounded based on consistent grouping among neighboring measures. This reduces drastically the ambiguity of contour location. Finally, Some mid-level constraints on spatial and temporal smoothness of moving boundaries are invoked, and they are combined with these low-level measures in the candidate regions. This is performed efficiently by the regularization over the restricted trajectory of the moving boundary in the candidate regions. Since any quantity is dimensionless, the results are not affected by varying conditions of camera and objects. We examine the efficiency of this algorithm through several experiments on real NTSC motion pictures with dynamic background and natulal textures.

Scattering characteristics of a stratified chiral slab, which is composed of dielectric chiral layers of different material properties and thicknesses, are extensively explored. Design considerations for optical filters are also presented for both the cases of normal and oblique incidence. In the analysis, the incident field is assumed to be a plane monochromatic wave of any arbitrary polarization. The transmitted and reflected electric fields are obtained by noting the fact that the electric field inside a chiral medium is expressed as a sum of the left- and right-circularly polarized plane waves of different phase velocities. Then one can describe the power densities and the Stokes parameters of the transmitted and reflected waves in terms of their field components. As is well known,the Stokes parameters characterize every possible state of polarization of a plane wave. Numerical examples are presented to show the effects of chirality on polarization conversion properties of the stratified chiral slab. The cross- and co-polarized powers and the Stokes parameters of the transmitted and reflected waves are computed for the incident wave of perpendicular polarization. The numerical results demonstrate novel depolarization properties of the slab with application to the design of efficient filters active at the optical region. It is seen from the results that the stratified chiral slab acts as a polarization-conversion transmission filter that passes only a cross-polarized component of the transmitted wave at some frequency band. Furthermore, the slab may be utilized as an antireflection filter for both the cross- and co-po1arized components of the reflected wave at the band region.

The scattering of electromagnetic waves by a dielectric grating with planar slanted-fringe is analyzed using the improved Fourier series expansion method. In the analysis, the slanted grating region is divided into layers to make an assembly of stratified thin modulated index layers. This method can be applied to a wide range of periodic structures and is especially effective in the case of planar slanted grating, because the electromagnetic fields in the each layer can easily be obtained by shifting the solution in the first layer. In this paper, the numerical results are given for grating with rectangular and sinusoidal dielectric profiles, and for TM and TE cases of arbitrary incident angle. The diffraction efficiencies obtained by the presented method are compared with the results by the coupled-wave approach; the influences of the slant angle on the diffraction efficiencies at the Wood's anomaly and at the coupling resonance frequency are also discussed.

High speed simulation of neural networks can be achieved through parallel implementations capable of exploiting their massive inherent parallelism. In this paper, we show how this inherent parallelism can be effectively exploited on parallel data-driven systems. By using these systems, the asynchronous parallelism of neural networks can be naturally specified by the functional data-driven programs, and maximally exploited by pipelined and scalable data-driven processors. We shall demonstrate the suitability of data-driven systems for the parallel simulation of neural networks through a parallel implementation of the widely used back propagation networks. The implementation is based on the exploitation of the network and training set parallelisms inherent in these networks, and is evaluated using an image data compression network.