In this paper, a design method is described for very low sensitivity fully-balanced narrow-band band-pass switched-capacitor filters (SCF's) whose worst-case sensitivities of the amplitude responses become zero at every reflection zero. The proposed method is based on applying the low-pass to high-pass transformation, the pseudo two-path technique and the capacitance-ratio reduction technique to very low sensitivity low-pass SC ladder filters. A design example of the band-pass SCF with a quality factor Q250 is given to verify the proposed method. The remarkable advantages of this approach are very low sensitivity to element-value variations, a small capacitance spread, a small total capacitance, and clock-feedthrough noise immunity inside the passband.

The demand for high-speed image processing is obvious in many real-world computations such as robot vision. Not only high throughput but also small latency becomes an important factor of the performance, because of the requirement of frequent visual feedback. In this paper, a high-performance VLSI image processor based on the multiple-valued residue arithmetic circuit is proposed for such applications. Parallelism is hierarchically used to realize the high-performance VLSI image processor. First, spatially parallel architecture that is different from pipeline architecture is considered to reduce the latency. Secondly, residue number arithmetic is introduced. In the residue number arithmetic, data communication between the mod mi arithmetic units is not necessary, so that multiple mod mi arithmetic units can be completely separated to different chips. Therefore, a number of mod mi multiply adders can be implemented on a single VLSI chip based on the modulus-slice concept. Finally, each mod mi arithmetic unit can be effectively implemented in parallel structure using the concept of a pseudoprimitive root and the multiple-valued current-mode circuit technology. Thus, it is made clear that the throughout use of parallelism makes the latency 1/3 in comparison with the ordinary binary implementation.

An adder-based arithmetic VLSI processor using the SD number system is proposed for the applications of real-time computation such as intelligent robot system. Especially in the intelligent robot control system, not only high throughput but also small latency is a very important subject to make quick response for the sensor feedback situation, because the next input sample is obtained only after the robot actually moves. It is essential in the VLSI architecture for the intelligent robot system to make the latency as small as possible. The use of parallelism is an effective approach to reduce the latency. To meet the requirement, an architecture of a new multiple-valued arithmetic VLSI processor is developed. In the processor, addition and subtraction are performed by using the single adderbased processing element (PE). More complex basic arithmetic operations such as multiplication and division are performed by the appropriate data communications between the adder-based PEs with preserving their parallelism. In the proposed architecture, fine-grain parallel processing at the adder-based PE level is realized, and all the PEs can be fully utilized for any parallel arithmetic operations according to adder-based data dependency graph. As a result, the processing speed will be greatly increased in comparison with the conventional parallel processors having the different kinds of the arithmetic PEs such as an adder, a multiplier and a divider. To realize the arithmetic VLSI processor using the adder-based PEs, we introduce the signed-digit (SD) number system for the parallel arithmetic operations because the SD arithmetic has the advantage of modularity as well as parallelism. The multiple-valued bidirectional currentmode technology is also used for the implementation of the compact and high-speed adder-based PE, and the reduction of the number of the interconnections. It is demonstrated that these advantges of the multiple-valued technology are fully used for the implementation of the arithmetic VLSI processor. As a result, the latency of the proposed multiple-valued processor is reduced to 25% that of the binary processor integrated in the same chip size.

Rapid advances in integrated circuit technology based on binary logic have made possible the fabrication of digital circuits or digital VLSI systems with not only a very large number of devices on a single chip or wafer, but also high-speed processing capability. However, the advance of processing speeds and improvement in cost/performance ratio based on conventional binary logic will not always continue unabated in submicron geometry. Submicron integrated circuits can handle multiple-valued signals at high speed rather than binary signals, especially at data communication level because of the reduced interconnections. The use of nonbinary logic or discrete-analog signal processing will not be out of the question if the multiple-valued hardware algorithms are developed for fast parallel operations. Moreover, in VLSI or ULSI processors the delay time due to global communications between functional modules or chips instead of each functional module itself is the most important factors to determine the total performance. Locally computable hardware implementation and new parallel hardware algorithms natural to multiple-valued data representation and circuit technologies are the key properties to develop VLSI processors in submicron geometry. As a result, multiple-valued VLSI processors make it possible to improve the effective chip density together with the processing speed significantly. In this paper, we summarize several potential advantages of multiple-valued VLSI processors in submicron geometry due to great reduction of interconnection and due to the suitability to locally computable hardware implementation, and demonstrate that some examples of special-purpose multiple-valued VLSI processors, which are a signed-digit arithmetic VLSI processor, a residue arithmetic VLSI processor and a matching VLSI processor can achieve higher performance for real-world computing system.

Broadband multimedia information environments are part of the next big advance in communications and computer technology. The use of multimedia infrastructures in offices is becoming very important. This paper deals with a service concept and human interfaces based on a paper metaphor. The proposed service offers the advantages of paper and eliminates the disadvantages. The power of multimedia's expressiveness, user interaction, and hypermedia technology are key points of our solution. We propose a system configuration for implementing the service/human interface.

Low-sensitivity digital filters are required for accurate signal processing. Among many low-sensitivity digital filters, a method using complex allpass circuits is well-known. In this paper, a new synthesis of complex allpass circuits is proposed. The proposed synthesis can be realized more easily either only in the z-domain or in the s-domain than conventional methods. The key concept for the synthesis is based on the factorization of lossless scattering matrices. Complex allpass circuits are interpreted as lossless digital two-port circuits, whose scattering matrices are factored. Furthermore, in the cases of Butterworth, Chebyshev and inverse Chebyshev responses, the explicit formulae for multiplier coefficients are derived, which enable us to synthesize the objective circuits directly from the specifications in the s-domain. Finally design examples verify the effectiveness of the proposed method.

Global dynamic behavior particularly the bifurcation of periodic orbits of a parallel blower system is studied using a piecewise linear model and the one-dimensional map defined by the Poincare map. First several analytical tools are presented to numerically study the bifurcation process particularly the bifurcation point of the fixed point of the Poincare map. Using two bifurcation diagrams and a bifurcation set, it is shown how periodic orbits bifurcate and leads to chaotic state. It is also shown that the homoclinic bifurcations occur in some parameter regions and that the Li & Yorke conditions of the chaotic state hold in the parameter region which is included in the one where the homoclinic bifurcation occurs. Together with the above, the stable and unstable manifolds of a saddle closed orbit is illustrated and the existence of the homoclinic points is shown.

In this paper, two models for associative memory based on a measure of manhattan length are proposed. First, we propose the two-layered model which has an advantage to its implementation by using PDN. We also refer to the way to improve the recalling ability of this model against noisy input patterns. Secondly, we propose the other model which always recalls the nearest memory pattern in a measure of manhattan length by lateral inhibition. Even if a noise of input pattern is so large that the first model can not recall, this model can recall correctly against such a noisy pattern. We also confirm the performance of the two models by computer simulations.

This paper presents a VLSI-oriented arithmetic design method using a radix-2 redundant number representation with digit set {0, 1, 2} and multiple-valued current-mode (MVCM) circuit technology. We propose a carry-propagation-free (CPF) parallel addition method with redundant digit set {0, 1, 2} which is suitable for the design with MVCM circuits. Several types of CPF parallel adders are compared and the proposed CPF parallel adder with MVCM circuits offers the best total performance with respect to speed, complexity, and power dissipation. The designed basic arithmetic circuits has sufficient noise immunity to the supply voltage fluctuation which is important for stable operations of the VLSI circuits. The CPF parallel adder is effectively used as the reduction scheme of partial products in a high-speed compact multiplier. For example, the designed 3232 bit multiplier reduces the number of active elements to two-third and the number of interconnections to one-fifth of the corresponding binary Wallace tree multiplier, where the speed is almost the same. The structure is simple and regular. The static power dissipation of the designed 32-bit multiplier is estimated to be the mean value of 212 mW and the worst case of 708 mW. The total power including dynamic power dissipation would not be so large compared with that of the 32-bit binary CMOS multiplier reported under 10 MHz operation.

This paper describes a mixed mode circuit simulation by the direct and relaxation-based methods with dynamic network partitioning. For the efficient circuit simulation by the direct method, the algorithms with circuit partitioning and latency technique have been studied. Recently, the hierarchical decomposition and latency and their validities have been researched. Network tearing techniques enable independent analysis of each subnetwork except for the local datum nodes. Therefore, if the local datum nodes are also torn, each subnetwork is separated entirely. Since the network separation is based on relaxation approach, the implementation of the separation technique in the circuit simulation by the direct method corresponds to performing the mixed mode simulation by the direct and relaxation-based methods. In this paper, a dynamic "network separation" technique based on the tightness of the coupling between subnetworks is suggested. Then, by the introduction of dynamic network separation into the simulator SPLIT with hierarchical decomposition and latency, the mixed mode circuit simulator, which selects the direct method or the relaxation method and determines the block size of the latent circuit dynamically and suitably, is constructed.

When we study time-domain electromagnetic fields, we frequently use the finite-difference time-domain (FD-TD) method. In this paper, we discuss errors of the FD-TD method and present the optimum mesh spacings in the FD-TD method when the three mesh spacings are different.

We consider an asymptotically sparsely encoded associative memory. Patterns are encoded by n-dimensional vectors of 1 and 1 generated randomly by a sequence of biased Bernoulli trials and stored in the network according to Hebbian rule. Using a heuristic argument we derive the following capacities:c(n)ne/4k log n'C(n)ne/4k(1e)log n'where, 0e1 controls the degree of sparsity of the encoding scheme and k is a constant. Here c(n) is the capacity of the network such that any stored pattern is a fixed point with high probability, whereas C(n) is the capacity of the network such that all stored patterns are fixed points with high probability. The main contribution of this technical paper is a theoretical verification of the above results using the Poisson limit theorems of exchangeable events.

This letter extends the overfitting lattice filter for ARMA parameter estimation with additive noise proposed by Sun and Yahagi. A new way of calculating the lattice parameters is proposed, making their computation truly recursive. This simplifies the method in Ref.(1), and makes it suitable to the parameter estimation of high-order systems.

In this paper, four simple nonlinear circuits with time-varying resistors are analyzed. These circuits consist of only four elements; a inductor, a capacitor, a diode and a time-varying resistor and are a kind of parametric excitation circuits whose dissipation factors vary with time. In order to analyze chaotic phenomena observed from these circuits a degeneration technique is used, that is, diodes in the circuits are assumed to operate as ideal switches. Thereby the Poincar maps are derived as one-dimensional maps and chaotic phenomena are well explained. Moreover, validity of the analyzing method is confirmed theoretically and experimentally.

A file transmission net N is a directed communication net with vertex set V and arc set B such that each arc e has positive cost ca(e) and each vertex u in V has two parameters of positive cost cv(u) and nonnegative integral demand d(u). Some information to be distributed through N is supposed to have been written in a file and the written file is denoted by J, where the file means an abstract concept of information carrier. In this paper, we define concepts of file transfer, positive demand vertex set U and mother vertex set M, and we consider a problem of distributing d(v) copies of J through a file transfer on N from a vertex v1 to every vertex v in V. As a result, for N such that MU, we propose an O(nm+n2 log n) algorithm, where n=|V| and m=|B|, for synthesizing a file transfer whose total cost of transmitting and making copies of J is minimum on N.

This paper presents a new algorithm for finding the kth-shortest paths between a specified pair of vertices in a directed graph with arcs having non-negative costs.

In this paper, optimal static load balancing in a tree hierarchy network that consists of a set of heterogeneous host computers is considered. It is formulated as a nonlinear optimization problem. We study the effects of the link communication time on the optimal link flow rate (i.e., the rate at which a node forwards jobs to other nodes for remote processing), the optimal node load (i.e., the rate at which jobs are processed at a node), and the optimal mean response time, by parametric analysis. We show that the entire network can be divided into several independent sub-tree networks with respect to the link flow rates and node loads. We find that the communication time of a link has the effects only on the link flow rates and the loads on nodes that are in the same sub-tree network. The increase in the communication time of a link causes the decrease in the link flow rates of its descendant nodes, its ancestor nodes and itself, but causes the increase in the link flow rates of other nodes in the same sub-tree network. It also causes the increase in the loads of its descendant nodes and itself, but causes the decrease in the loads of other nodes in the same sub-tree network. In general, it causes the increase in the mean response time.

We propose a direct-sequence spread-spectrum multi-access (DS/SSMA) receiver that incorporates multipath diversity combining and multistage co-channel interference (CCI) cancellation. This receiver structure which is more resistant to the near/far problem essentially removes more and more of the CCI with each successive cancellation stage. With the assumption that perfect channel estimates have been obtained, we analyze the bit error rate (BER) performance of this system when received powers are unequal. Results show that the BER can approach that of a single-user case as the number of CCI cancellation stages increases.

In this paper, some misconceptions about "multipath propagation" are discussed for those propagation engineers, who are not familiar with the close relationship between multipath propagation and a communication system in a mobile/portable radio communication environment. It is shown that believed facts about multipath propagation are not always true. Namely, it is well-known that multipath propagation is undesirable if a conventional sample-and-decision receiver is assumed. It is not well-recognized that it can be a desirable phenomenon if a sophisticated communication system uses adaptive equalization, anti-multipath modulation, or spread spectrum communication, for example. On the other hand, it is widely accepted that root mean square (rms) multipath delay spread is a good measure of bit-error-rate performance, i.e., as rms delay spread gets larger, bit-error-rate generally gets worse. However, it is pointed out that this is not always true, especially in propagation conditions with very long-delayed multipath signals. In short, it is the purpose of this paper to show examples that the facts believed to be true sometimes turn out to be false, unless we pay attention to both aspects of propagation and system design in the field of mobile/portable radio communications. In fact, for highly efficient communication systems design, propagation, antenna and system factors should be taken into account simultaneously.

A new theoretical propagation model for wideband fading channel simulation in mobile radio environments is presented. It is based on a path model which produces scattered waves according to Poisson process. The typical properties of transmission characteristics deduced from the theoretical and experimental studies are taken in the model. Using the propagation model, an analytical method for the near-far problem of CDMA in mobile radio environments is proposed. An example of the analysis by means of a simulation is also presented.