It is shown that two-dimensional linear phase FIR digital filters with various shapes of frequency response can be designed and realized as modular array structures free of multiplier coefficients. The design can be performed by judicious selection of two low order linear phase transfer functions to be used at each module as kernel filters. Regular interconnection of the modules in L rows and K columns conditioned with boundary coefficients 1, 0 and 1/2 results in higher order digital filters. The kernels should be chosen appropriately to, first, generate the desired shape of frequency response characteristic and, second, lend themselves to multiplierless realization. When these two requirements are satisfied, the frequency response can be refined to possess narrower transition bands by adding additional rows and columns. General properties of the frequency response of the array are investigated resulting in Theorems that serve as valuable tools towards appropriate selection of the kernels. Several design examples are given. The array structures enjoy several favorable features. Specifically, regularity and lack of multiplier coefficients makes it suitable for high-speed systolic VLSI implementation. Computational complexity of the structure is also studied.

The parasitic bipolar effect in a 200-V-class thin-film SOI power MOSFET fabricated using the silicon wafer direct bonding wafer was investigated by electrical measurement, two-dimensional process simulation, emission microscopy, and 2-dimensional thermal analysis. It degraded the breakdown voltage of the thin-film SOI power MOSFET and was caused by the increase in the sheet resistance of the body contact region. Photo emission analysis indicated that excess holes recombined in the n+-source region.

In this paper, we extend the circuit partitioning algorithm which we have proposed for multi-FPGA systems and present a new algorithm in which the delay of each critical signal path is within a specified upper bound imposed on it. The core of the presented algorithm is recursive bipartitioning of a circuit. The bipartitioning procedure consists of three stages: 0) detection of critical paths; 1) bipartitioning of a set of primary inputs and outputs; and 2) bipartitioning of a set of logic-blocks. In 0), the algorithm computes the lower bounds of delays for paths with path delay constraints and detects the critical paths based on the difference between the lower and upper bound dynamically in every bipartitioning procedure. The delays of the critical paths are reduced with higher priority. In 1), the algorithm attempts to assign the primary inputs and outputs on each critical path to one chip so that the critical path does not cross between chips. Finally in 2), the algorithm not only decreases the number of crossings between chips but also assigns the logic-blocks on each critical path to one chip by exploiting a network flow technique. The algorithm has been implemented and applied to MCNC PARTITIONING 93 benchmark circuits. The experimental results demonstrate that it resolves almost all path delay constraints with maintaining the maximum number of required I/O blocks per chip small compared with conventional alogorithms.

We are working on an algorithm to optimize the logic circuits that can be realized on the super fine-grain parallel processing architecture. As a part of this work, we have developed an inverter reduction algorithm. This algorithm is based on modeling logic circuits as dynamical systems. We implement the algorithm in the PARTHENON system, which is the high level synthesis system developed in NTT's laboratories, and evaluate it using ISCAS85 benchmarks. We also compare the results with both the existing algorithm of PARTHENON and the algorithm of Jain and Bryant.

This paper proposes a parallel word alignment procedure for m Binary with 1 Complement Insertion (mBlC) or Differential m Binary with l Mark Insertion (DmBlM) line code. In the proposed procedure for mBlC line code, the word alignment circuit searches (m+1) bit pairs in parallel for complementary relationships. A Signal Flow Graph Model for the parallel word alignment procedure is also proposed, and its performance attributes are numerically analyzed. The attributes are compared with those of the conventional bit-by-bit procedure, and it is shown that the proposed procedure displays superior performance in terms of False-Alignment Probability and Maximum Average Aligning Time. The proposed procedure is suitable for high speed optical data links, because it can be easily implemented using a parallel signal processor operating at a clock rate equal to 1/(m+1) times the mBlC line rate.

We introduce two probabilistic algorithms to determine the motion parameters of a planar shape without knowing a priori the point-to-point correspondences. If the target is limited to rigid objects, an Euclidean transformation can be expressed as a linear equation with six parameters, i.e. two translational parameters and four rotational parameters (the axis of rotation and the rotational speed about the axis). These parameters can be determined by applying the randomized Hough transform. One remarkable feature of our algorithms is that the calculations of the translation and rotation parameters are performed by using points randomly selected from two image frames that are acquired at different times. The estimation of rotation parameters is done using one of two approaches, which we call the triangle search and the polygon search algorithms respectively. Both methods focus on the intersection points of a boundary of the 2D shape and the circles whose centers are located at the shape's centroid and whose radii are generated randomly. The triangle search algorithm randomly selects three different intersection points in each image, such that they form congruent triangles, and then estimates the rotation parameter using these two triangles. However, the polygon search algorithm employs all the intersection points in each image, i.e. all the intersection points in the two image frames form two polygons, and then estimates the rotation parameter with aid of the vertices of these two polygons.

Partial capture effect for multi-carrier radio packet communication network is evaluated in frequency selective fading channel. In multi-carrier modulation (MCM) network where each terminal uses several sub-carriers for transmission,the terminals have different instantaneous frequency responses because of its location, fading pattern, and other various factors. This generates the difference of received power in frequency domain, then partial capture effect can be considered at each sub-carrier. Moreover these partially captured packets are not damaged by inter symbol interference (ISI) caused by frequency selective fading, which seriously degrades single-carrier modulation (SCM) network. From this point of view we present the partial capture effect for the MCM network in the frequency selective fading environment. The results show that the MCM network with partial capture has more advantages than the MCM network without partial capture in terms of the throughput and the average number of transmissions.

This paper presents an 8-bit 200M-sample/s (Ms/s) analog-to-digital converter (ADC) applicable to liquid crystal display (LCD) driver systems. The ADC features such circuit techniques as a low-power and high-speed comparator, an open-loop sample-and-hold amplifier with a 3.4-ns acquisition time, a fully differential two step architecture, and a replica circuit. It is fabricated with a 0.8µm BiCMOS process onto an area of only 12mm2 and it dissipates 500mW from a single-5.2V power supply.

In this paper we discuss a certain constrained optimization problem which is often encountered in the geometrical optimization. Since these kinds of problems occur frequently, constrained genetic optimization becomes very important topic for research. This paper proposes a new methodology to handle constraints using the Genetic Algorithm through a multiprocessor system (FIN) which has a self-similarity network.

We have developed and operated a newly conceived multiprobe scanning force microscope (SFM) using microfabricated piezoelectric cantilevers. An array of piezoelectric microcantilevers with a piezoelectric ZnO layer on an SiO2 film makes it possible to build a multiprobe SFM system. Multiprobe SFMs are required for the application of SFM to the probe lithography and high density data storage. Each cantilever probe of multiprobe system should have a detector for sensing of its own deflection and an actuator for positioning of its tip. The piezoelectric cantilever can detect its own vibration amplitude by measuring the piezoelectric current, and it can also drive its tip by applying a voltage to the piezoelectric layer. Therefore, the piezoelectric cantilever is suitable for each cantilever of the array in the multiprobe SFM. We have verified the applicability of the piezoelectric cantilever to each lever of the array by characterizing the sensitivities of the deflection sensing and actuation. The ZnO piezoelectric cantilever with the length of 125 µm works as the z scanner with the sensitivity of 20 nm/V. We have also fabricated an experimental piezoelectric microcantilever array with ten cantilevers. We have constructed parallel operation SFM system with two cantilevers of the fabricated array and successfully obtained parallel images of 1 µm pitch grating in constant height mode.

We present a new class of trellis-codes for partial-response channel. Our code configuration is based on the coded 1 - D scheme due to Wolf and Ungerboeck. However, no precoder between a convolutional encoder and the partialresponse channel is used. A new lower bound on the minimum free squared Euclidean distance of channel code is shown. The bound is available for any PR channel with a finite response. New codes for 1 - D and (1 - D) (1 + D)2 channels are found by computer code search using the lower bound. Some of the new codes have excellent properties: a significant d2free and a small decoding complexity.

This paper presents an analog 2-dimensional discrete cosine transform (2-D DCT) processor for focal-plane image compression. The on-chip analog 2-D DCT processor can process directly the analog signal of the CMOS image sensor. The analog-to-digital conversion (ADC) is preformed after the 2-D DCT, and this leads to efficient AD conversion of video signals. Most of the 2-D DCT coefficients can be digitized by a relatively low-resolution ADC or a zero detector. The quantization process after the 2-D DCT can be realized by the ADC at the same time. The 88-point analog 2-D DCT processor is designed by switched-capacitor (SC) coefficient multipliers and an SC analog memory based on 0.35µm CMOS technology. The 2-D DCT processor has sufficient precision, high processing speed, low power dissipation, and small silicon area. The resulting smart image sensor chips with data compression and digital transmission functions are useful for the high-speed image acquisition devices and portable digital video camera systems.

The response time of adders is mainly determined by the carry propagation delay. This letter deals with a scheme which combines the address addition and decoding together. Although addition is involved in the process, we show that it can be computed without carry propagation. Memory latency is one of the most performance limiting factors. The authors present a new decoder logic named fused add-decoder (FADEC), which performs address addition and decoding in a single process. FADEC can reduce memory latency by eliminating separate address addition cycle.

This paper presents a reshufflable and laziness tolerant mental card game protocol. First, our protocol can reshuffle any subset of cards. For example, some opened cards and some face down cards can be shuffled together. Next, we consider two types of honest players, currently active and currently nonactive. A player is currently nonactive if he dropped out the game or he declared "pass" and has not declared "rejoin" yet. In the proposed protocol, if more than half of the players are currently active, they can play the game. In this case, the privacy of the currently nonactive players are kept secret.

A simple extension to treat evanescent modal excitation at the aperture of a parallel plane waveguide is shown here by GTD diffracted rays with complex propagation angles. Numerical comparison with other solution confirmed that our simple solution can be used for modal excitation estimation below the cut-off frequency.

In this paper, we show that a parity function with n variables can be computed by a threshold circuit of depth O((log n)/c) and size O((2clog n)/c), for all 1c [log(n+1)]-1. From this construction, we obtain an O(log n/log log n) upper bound for the depth of polylogarithmic size threshold circuits for parity functions. By using the result of Impagliazzo, Paturi and Saks[5], we also show an Ω (log n/log log n) lower bound for the depth of the threshold circuits. This is an answer to the open question posed in [11].

So far, neuronal dendrites have been characterized as electrically passive cables. However, recent physiological findings have revealed complex dynamics due to active conductances distributed over dendrites. In particular, the voltage-gated calcium and calcium-activated conductances are essential for producing diverse neuronal dynamics and synaptic plasticity. In this paper, we investigate the functional significance of the dendritic calcium-activated dynamics by computer simulations. First, the dendritic calcium-activated responses are modeled in a discrete compartmental form based on the physiological findings. Second, the basic stimulus-response characteristics of the single compartment dendrite model are investigated. The model is shown to reproduce the neuronal responses qualitatively. Third, the spatio-temporal dynamics of the dendrite shafts are modeled by longitudinally connecting 10 single compartments with coupling constants which are responsible for the dendrite thickness. The thick dendrite models, corresponding to proximal dendrites, respond in a spatially cooperative manner to a localized constant or periodic current stimulation. In contrast, the highly activated compartments are forced to be localized in the neighborhood of the stimulation-site in the fine dendrite models corresponding to distal dendrites. These results suggest that dendritic activities are spatially cooperated in a site-dependent manner.

In this paper, we show an entropy-based approach to the privacy of multi-party protocols. First, we formulate the amount of leaked information by using mutual information for a two-party case. This is a better measure for some situations than the combinatorial measure known so far. Next, we apply multi-terminal information theoty to more than two parties and give the first formulation of the leaked information for more than two parties.

Two methods of the second step of the elliptic curve method for factoring are known. One is the standard method that is similar to the second step of the p-1 method, and the other is the Brent method that is based on the "birthday paradox." In this paper, we propose a revised standard method and a revised Brent method. On an average, the revised standard method is the most efficient, the standard method is the second efficient, the revised Brent method is the third and the Brent method is the fourth. If the largest prime factor on the order of an elliptic curve is congruent to 1 modulo 3, then the revised Brent method becomes more efficient than the standard method. By applying these methods to unsolved problems in the Cunningham project, we found 18 new prime factors. The largest prime factor among them was 43-digits.

This paper deals with the synthesis of Petri nets. Partial languages adequately represent the concurrent behaviors of Petri nets. We first propose a construction problem for Petri nets, in which the objective is to synthesize a Petri net to exhibit the desired behavior specified as a partial language. We next discuss the solvability of this problem and last present the cutline of a solution technique.