An advanced characterization method for sub-micron DRAM cell transistors has been proposed for the analysis of transistor test structures using memory cell patterns. When the actual memory cell layout is used as a test structure, the parasitic source and drain resistance of the test structure affected conventional transistor parameters such as threshold voltage. To solve this problem, reduced drain current measurement methods have been proposed to suppress the parasitic resistance voltage drop. In these measurements, two new transistor parameters, Vgoff and Vgsat, have been proposed which are related to off-leakage and full writing, respectively. These parameters are found to be good parameters for monitoring DRAM bit failures. A new threshold voltage measurement methodology has also been proposed for test structures with high parasitic resistance.

The self-healing capability against network failure is one of indispensable features for the B-ISDN infrastructure. One problem in realizing such self-healing backbone network is the inefficient utilization of the large spare capacity designed for the failure-restoration purpose since it will be used only in the failure time that does not occur frequently. "Pool-capacity" is the concept that allows some VPs (virtual paths) to efficiently utilize this spare capacity part. Although the total capacity can be saved by using the "Pool Capacity," it is paid by less reliability of VPs caused by the emerging influence of indirect-failure. Thus, this influence of indirect-failure has to be considered in the capacity designing process so that network-designers can trade off the saving of capacity with the reliability level of VPs in their self-healing networks. In this paper, Damage Rate:DR which is the index to indicate the level of the influence caused by indirect-failure is defined and the pool-capacity design scheme with DR consideration is proposed. By the proposed scheme, the self-healing network with different cost (pool-capacity) can be designed according to the reliability level of VPs.

In order to reduce state explosion problem, techniques such as symbolic state space traversal and partial order reduction have been proposed. Combining these two techniques, however, seems difficult, and only a few research projects related to this topic have been reported. In this paper, we propose handling single place zero reachability problem of Petri nets by using both partial order reduction and symbolic state space traversal based on ZBDDs. We also show experimental results of several examples.

In this paper, we propose a novel fault-tolerant multicast algorithm for n-dimensional wormhole routed hypercubes. The multicast algorithm will remain functional if the number of faulty nodes in an n-dimensional hypercube is less than n. Multicast is the delivery of the same message from one source node to an arbitrary number of destination nodes. Recently, wormhole routing has become one of the most popular switching techniques in new generation multicomputers. Previous researches have focused on fault-tolerant one-to-one routing algorithms for n-dimensional meshes. However, little research has been done on fault-tolerant one-to-many (multicast) routing algorithms due to the difficulty in achieving deadlock-free routing on faulty networks. We will develop such an algorithm for faulty hypercubes. Our approach is not based on adding physical or virtual channels to the network topology. Instead, we integrate several techniques such as partitioning of nodes, partitioning of channels, node label assignments, and dual-path multicast to achieve fault tolerance. Both theoretical analysis and simulation are performed to demonstrate the effectiveness of the proposed algorithm.

The conventional synthesis procedure of discrete time sparsely interconnected neural networks (DTSINNs) for associative memories may generate the cells with only self-feedback due to the sparsely interconnected structure. Although this problem is solved by increasing the number of interconnections, hardware implementation becomes very difficult. In this letter, we propose the DTSINN system which stores the 2-dimensional discrete Walsh transforms (DWTs) of memory patterns. As each element of DWT involves the information of whole sample data, our system can associate the desired memory patterns, which the conventional DTSINN fails to do.

Effects of the model order estimation error in the TLS-ESPRIT algorithm were investigated. It was found that if the model order is overestimated true signal parameters are preserved even though spurious signals of which power values are negligibly small appear, whereas if the model order is underestimated some signals degenerate to each others, resulting in the erroneous estimates.

An unbiased estimation method for symmetric noncausal ARMA model parameters is presented. The proposed algorithm works in two steps: first, a spectrally equivalent causal system is identified by lattice whitening filter and then the equivalent noncausal system is reconstructed. For AR system with noise or ARMA system without noise, the proposed method does not need any iteration method nor any optimization procedure. An estimation method of noise variance when the observation is made in noisy situation is discussed. The potential capabilities of the algorithm are demonstrated by using some numerical examples.

Optimum filters for an image restoration are formed by a degradation operator, a covariance operator of original images, and one of noise. However, in a practical image restoration problem, the degradation operator and the covariance operators are estimated on the basis of empirical knowledge. Thus, it appears that they differ from the true ones. When we restore a degraded image by an optimum filter belonging to the family of Projection Filters and Parametric Projection Filters, it is shown that small deviations in the degradation operator and the covariance matrix can cause a large deviation in a restored image. In this paper, we propose new optimum filters based on the regularization method called the family of Regularized Projection Filters, and show that they are stable to deviations in operators. Moreover, some numerical examples follow to confirm that our description is valid.

Recently, we proposed a low power consumption FIR switched-capacitor filter constructed with capacitors having capacitances in proportion to square roots of transfer function coefficient values. It is referred to as an FIR semi-parallel cyclic type (SPCT) filter. In this paper, we present IIR SPCT filter. It needs only a single operational amplifier, hence being low power consumption. The IIR SPCT filter has smaller total capacitance than one of the IIR parallel cyclic type (PCT) filter and better high frequency response than one of the IIR transfer function coefficient ratio (TCR) filter. As a whole, the IIR SPCT filter has middle performance of the IIR PCT and TCR filters for the total capacitance, the number of types of clock pulses, and high frequency response.

The Conjugate Residual method, one of the iterative methods for solving linear systems, is applied to the problems with a dense coefficient matrix on distributed memory parallel computers. Based on an assumption on the computation and communication times of the proposed algorithm for parallel computers, it is shown that the optimal number of processing elements is proportional to the problem size N. The validity of the prediction is confirmed through numerical experiments on Hitachi SR2201.

Thanks to rapid progress in computer technology and VLSI technology, we are approaching the stage where ordinary PCs will be able to handle real-time video signals as easily as they handle text data. First, features and applications of the video compression standard MPEG2 are surveyed as a typical video processing. It is clarified that real-time capability becomes more important as applications of MPEG2 widely spread. The trends of video coding in LSIs are summarized. And it is shown that the most advanced encoder/decoder LSI has an improved price-performance ratio that allows it to be adopted in consumer equipment. Finally, future directions of parallel architecture in video processing are surveyed in terms of special-purpose and general-purpose processing. The special approach has always taken the lead in video processing using sophisticated hardware-oriented parallel architectures. The general-purpose architecture method has gradually evolved in accordance with a software-oriented architecture. Both approaches will continue to evolve into a new stage by selecting possible parallel architectures such as multimedia instruction sets and process-level parallelism, and applying them in compound use. The so-called super processor architecture will emerge in the near future and it will be an ideal method that can manage rapid increase in requirements of capability and applicability in video processing.

A 1.5 V 8 mW BiCMOS video A/D converter has been developed by using a BiCMOS pumping comparator. Combining Bipolar high-speed and good-matching characteristics with CMOS switched capacitor techniques, this A/D converter is suitable for use in battery-operated multimedia terminals.

This paper presents an algorithm for viewpoint-based similarity discernment of linguistic concepts on Semantic Network Array Processor (SNAP). The viewpoint-based similarity discernment plays a key role in retrieving similar propositions. This is useful for advanced knowledge processing areas such as analogical reasoning and case-based reasoning. The algorithm assumes that a knowledge base is constructed for SNAP, based on information acquired from the WordNet linguistic database. The algorithm identifies paths on the knowledge base between each given concept and a given viewpoint concept, then computes a similarity degree between the two concepts based on the number of nodes shared by the paths. A small scale knowledge base was constructed and an experiment was conducted on a SNAP simulator that demonstrated the feasibility of this algorithm. Because of SNAP's scalability, the algorithm is expected to work similarly on a large scale knowledge base.

Divisor-Skip Wavelength Division Multiplexing (DS-WDM) ring is an optical interconnection network for workstation clusters or parallel machines which can connect various number of nodes easily using wavelength division multiplexing techniques. However, the wavelength-ordered routing algorithm proposed for the DS-WDM ring requires complicated processes in each router. Here, a new routing algorithm called the comparing dimensional number routing algorithm for the DS-WDM ring is proposed and evaluated. Although the diameter and average distance are almost same as traditional wavelength-ordered routing, the cost and latency are much reduced.

In this paper, we present an efficient approach for technology scaling of MOS analog circuits by using circuit optimization techniques. Our new method is based on matching equivalent circuit parameters between a previously designed circuit and the circuit undergoing redesign. This method has been applied to a MOS operational amplifier. We were able to produce a redesigned circuit with almost the same performance in under 4 hours, making this method 5 times more efficient than conventional methods

We propose a real-time low-rate video compression algorithm using fixed-rate multi-stage hierarchical vector quantization. Vector quantization is suitable for mobile computing, since it demands small computation on decoding. The proposed algorithm enables transmission of 10 QCIF frames per second over a low-rate 29.2 kbps mobile channel. A frame is hierarchically divided by sub-blocks. A frame of images is compressed in a fixed rate at any video activity. For active frames, large sub-blocks for low resolution are mainly transmitted. For inactive frames, smaller sub-blocks for high resolution can be transmitted successively after a motion-compensated frame. We develop a compression system which consists of a host computer and a memory-based processor for the nearest neighbor search on VQ. Our algorithm guarantees real-time decoding on a poor CPU.

The disk allocation problem examined in this paper is finding a method to distribute a Binary Cartesian Product File on multiple disks to maximize parallel disk I/O accesses for partial match retrieval. This problem is known to be NP-hard, and heuristic approaches have been applied to obtain suboptimal solutions. Recently, efficient methods such as Binary Disk Modulo (BDM) and Error Correcting Code (ECC) methods have been proposed along with the restrictions that the number of disks in which files are stored should be a power of 2. In this paper, a new Disk Allocation method based on Genetic Algorithm (DAGA) is proposed. The DAGA does not place restrictions on the number of disks to be applied and it can allocate the disks adaptively by taking into account the data access patterns. Using the schema theory, it is proven that the DAGA can realize a near-optimal solution with high probability. Comparing the quality of solution derived by the DAGA with the General Disk Modulo (GDM), BDM, and ECC methods through the simulation, shows that 1) the DAGA is superior to the GDM method in all the cases and 2) with the restrictions being placed on the number of disks, the average response time of the DAGA is always less than that of the BDM method and greater than that of the ECC method in the absence of data skew and 3) when data skew is considered, the DAGA performs better than or equal to both BDM and ECC methods, even when restrictions on the number of disks are enforced.

Simple expressions for constriction resistance of multitude conducting spots were analytically formulated by Greenwood. These expressions, however, include some approximations. Nakamura presented that the constriction resistance of one circular spot computed using the BEM is closed to Maxwell's exact value. This relative error is only e=0. 00162 [%]. In this study, the constriction resistances of two, five and ten conducting spots are computed using the boundary element method (BEM), and compared with those obtained using Greenwood's expressions. As the conducting spots move close to each other, the numerical deviations between constriction resistances computed using Greenwood's expressions and the BEM increase. As a result, mutual resistance computed by the BEM is larger than that obtained from Greenwood's expressions. The numerical deviations between the total resistances computed by Greenwood's expressions and that by the BEM are small. Hence, Greenwood's expressions are valid for the total constriction resistance calculation and can be applied to problems where only the total resistance of two contact surfaces, such as a relay and a switch, is required. However, the numerical deviations between the partial resistances computed by Greenwood's expression and that by the BEM are very large. The partial resistance calculations of multitude conducting spots are beyond the applicable range of Greenwood's expression, since Greenwood's expression for constriction resistance of two conducting spots is obtained by assuming that the conducting spots are equal size. In particular, the deviation between resistances of conducting spots, which are close to each other, is very large. In the case of partial resistances which are significant in semiconductor devices, Greenwood's expressions cannot be used with high precision.

We developed a PC cluster system which consists of 100 PCs as a test bed for massively parallel query processing. Each PC employs the 200 MHz Pentium Pro CPU and is connected with others through an ATM switch. Because the query processing applications are insensitive to the communication latency and mainly perform integer operations, the ATM connected PC cluster approach can be considered a reasonable solution for high performance database servers with low costs. However, there has been no challenge to construct large scale PC clusters for database applications, as far as the authors know. Though we employed commodity components as much as possible, we developed the DBMS itself, because that was a key component for obtaining high performance in parallel query processing, and there seemed no system which could meet our demand. On each PC node, a server program which acts as a database kernel is running to process the queries in cooperation with other nodes. The kernel was designed to execute pipelined operators and handle voluminous data efficiently, to achieve high performance on complex decision support type queries. We used the standard benchmark, TPC-D, on a 100 GB database to verify the feasibility of our approach, through comparison of our system with commercial parallel systems. As a whole, our system exhibited sufficiently high performance which was competitive with the current TPC-D top records, in spite of not using indices. For some heavy queries in the benchmark, which have high selectivity and joinability, our system performed much better. In addition, we applied transposed file organization to the database for further performance improvement. The transposed file organization vertically partitions the tuples, enabling attribute-by-attribute access to the relations. This resulted in significant performance improvement by reducing the amount of disk I/O and shifting the bottleneck to computation.

This paper gives an overview of research activities on high performance databases in Japan. It focuses on parallel algorithms for relational databases and data mining, parallel approaches for object-oriented databases, and parallel disk systems. Studies surveyed in this paper are carried out mainly by database researchers in Japanese universities under the Grant-in-Aid for Scientific Research (1996-1998).