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[Keyword] PAR(2741hit)

2101-2120hit(2741hit)

  • A 3 V Low Power 156/622/1244 Mbps CMOS Parallel Clock and Data Recovery Circuit for Optical Communications

    Hae-Moon SEO  Chang-Gene WOO  Sang-Won OH  Sung-Wook JUNG  Pyung CHOI  

     
    PAPER-General Fundamentals and Boundaries

      Vol:
    E83-A No:8
      Page(s):
    1720-1727

    This paper presents the implementation of a 3 V low power multi-rate of 156, 622, and 1244 Mbps clock and data recovery circuit (CDR) for optical communications tranceiver using new parallel clock recovery architecture based on dual charge-pump PLL. Designed circuit recovers eight-phase clock signals which are one-eighth frequency of the input signal. While the typical system uses the method that compares the input data with recovered clock, the proposed circuit compares a 1/2-bit delayed input data with the serial data generated by the recovered eight-phase clock signals. The advantage of the circuit is that the implementation is easy, since each sub blocks have one-eighth frequency of the input data signal. Morevover, since the circuit works at one-eighth frequency of the input data, it dissipates less power than conventional CMOS recovery circuit. Simulation results show that this recovery circuit can work with power dissipation of less than 40 mW with a single 3 V supply. All the simulations are based on HYUNDAI 0.65 µm N-Well CMOS double-poly double-metal technology.

  • BPL: A Language for Parallel Algorithms on the Butterfly Network

    Fattaneh TAGHIYAREH  Hiroshi NAGAHASHI  

     
    PAPER-Algorithms

      Vol:
    E83-D No:7
      Page(s):
    1488-1496

    A number of parallel algorithms have been developed to solve large-scale real world problems. Although there has been much work on the design of parallel algorithms, there has been little on the design of languages for expressing these algorithms. This paper describes the BPL, a new parallel language designed for butterfly networks. The purpose of this language is to help designers in hiding the complexity of the algorithm and leaving details of mapping between data and processors for lower level. BPL provides a simpler virtual machine for the designer , in order to avoid thinking about control of processors and data. From another point of view, BPL helps designer to logically check the algorithm and correct any possible error in it. The paper gives some examples implemented by this language. In addition, we have also implemented a software tool which simulates the running of the algorithm on the network. The results lead us to believe that this language would be useful in representing all kinds of algorithms on this network including normal algorithms and others.

  • Fast Stereo Matching Using Constraints in Discrete Space

    Hong JEONG  Yuns OH  

     
    PAPER-Image Processing, Image Pattern Recognition

      Vol:
    E83-D No:7
      Page(s):
    1592-1600

    We present a new basis for discrete representation of stereo correspondence. This center referenced basis permits a more natural, complete and concise representation of constraints in stereo matching. In this context a MAP formulation for disparity estimation is derived and reduced to unconstrained minimization of an energy function. Incorporating natural constraints, the problem is simplified to the shortest path problem in a sparsely connected trellis structure which is performed by an efficient dynamic programing algorithm. The computational complexity is the same as the best of other dynamic programming methods, but a very high degree of concurrency is possible in the algorithm making it suitable for implementation with parallel procesors. Experimental results confirm the performance of this method and matching errors are found to degrade gracefully in exponential form with respect to noise.

  • Semi-Parallel Cyclic Type Switched-Capacitor Filter Using Unity Gain Buffer

    Toshihiro MORI  Nobuaki TAKAHASHI  Tsuyoshi TAKEBE  

     
    PAPER-Analog Signal Processing

      Vol:
    E83-A No:7
      Page(s):
    1370-1380

    Recently, we developed a low power consumption and small total capacitance switched-capacitor filter using a single operational amplifier. It is called a semi-parallel cyclic type (SPCT) filter, in which each capacitance is in proportion to the square root of a transfer function coefficient value. In this paper, we propose the SPCT filter using a single unity gain buffer (UGB). It will be referred to a UGB-SPCT filter. It is possible to use the UGB-SPCT filter over a wider frequency range than the SPCT filter since a UGB has nearly unity gain over a wide frequency range.

  • Topographical Change of Azopolymer Surface Induced by Optical Near-Field around Photo-Irradiated Nanoparticles

    Osamu WATANABE  Taiji IKAWA  Makoto HASEGAWA  Masaaki TSUCHIMORI  Yoshimasa KAWATA  Chikara EGAMI  Okihiro SUGIHARA  Naomichi OKAMOTO  

     
    LETTER-Thin Film

      Vol:
    E83-C No:7
      Page(s):
    1125-1127

    Topographical changes induced by optical near-field around photo-irradiated nanoparticles were attained using a pulsed laser with a large peak power as a light source. The arrayed structure of nanoparticles was transcribed on urethane-urea azo copolymer film as dent structure. The experiments by the pulsed laser of different wavelength showed that the topographical change was caused by the light absorption. The dent diameter and the dent depth changed depending on the diameter of nanoparticles.

  • Steady-State Response of Nonlinear Circuits Containing Parasitic Elements

    Takeshi MATSUDA  Yoshifumi NISHIO  Yoshihiro YAMAGAMI  Akio USHIDA  

     
    PAPER

      Vol:
    E83-A No:6
      Page(s):
    1023-1031

    We propose here a time-domain shooting algorithm for calculating the steady-state responses of nonlinear RF circuits containing parasitic elements that is based on both a modified Newton and a secant methods. Bipolar transistors and MOSFETs in ICs have small parasitic capacitors among their terminals. We can not neglect them because they will gives large effects to the shooting algorithm at the high frequency. Since our purpose is to develop a user friendly simulator, we mainly take into account the relatively large normal capacitors such as coupling and/or by-pass capacitors and so on, because the parasitic capacitors are usually smaller and contained in the device models. We have developed a very simple simulator only using the fundamental tools of SPICE, which can be applied to relatively large scale ICs, efficiently.

  • A Boolean Multivalued Logical Model of Varying Confirmation by Observation of Events and Hempel's Paradox of the Ravens

    Hisashi SUZUKI  

     
    LETTER-Artificial Intelligence, Cognitive Science

      Vol:
    E83-D No:6
      Page(s):
    1314-1316

    This article shows a Boolean Multivalued logical model of varying confirmation by observation of events in human inference and, as an introductory example, applies the model to solve Hempel's paradox of the ravens.

  • Development of 1D Object-Oriented Particle-in-Cell Code (1d-XOOPIC)

    Hideyuki USUI  John P. VERBONCOEUR  Charles K. BIRDSALL  

     
    LETTER-Electromagnetic Theory

      Vol:
    E83-C No:6
      Page(s):
    989-992

    For plasma simulations, we developed a one-dimensional (1d) Object-Oriented Particle-in-Cell code for X11-based Unix workstations (XOOPIC) by modifying the current two-dimensional version which was originally developed by PTSG (Plasma theory and simulation group) in the University of California at Berkeley. We implemented a simplified field solve and current deposition in the code. We retained three components of particle velocity, although the spatial variation for particle position and field components is limited to one dimension. To verify the function of the 1d code, we perform simulations with typical models such as the Child-Langmuir current model and electromagnetic wave propagation in plasma. In both cases, the simulation results quantitatively agree with the theory.

  • Parallelism-Independent Scheduling Method

    Kirilka NIKOLOVA  Atusi MAEDA  Masahiro SOWA  

     
    PAPER

      Vol:
    E83-A No:6
      Page(s):
    1138-1150

    All the existing scheduling algorithms order the instructions of the program in such a way that it can be executed in minimal time only for one fixed number of processors. In this paper we propose a new scheduling method, called Parallelism-Independent Scheduling Method, which enables the execution of the scheduled program on parallel computers with any degree of parallelism in near-optimal time. We propose three Parallelism-Independent algorithms, which have the following phases: obtaining a parallel schedule by using a list scheduling heuristics, optimization of the parallel schedule by rearranging the tasks in each level, so that they can be executed efficiently with different degrees of parallelism, serialization of the parallel schedule, and insertion of markers for the parallel execution limits. The three algorithms differ in their optimization phase. To prove the efficiency of our algorithms, we have made simulations with random directed acyclic graphs with different size and degree of parallelism. We compared the results in terms of schedule length to those obtained using the Critical Path Algorithm separately for each degree of parallelism.

  • Evaluation of PARAdeg of Acyclic SWITCH-Less Program Nets

    Qi-Wei GE  Kenji ONAGA  

     
    LETTER

      Vol:
    E83-A No:6
      Page(s):
    1186-1191

    PARAdeg has been defined to try to measure parallelism inherent in a program net. Studies on computation of PARAdeg have been done, but the quantitative evaluation, on how much PARAdeg fits parallelism of program nets, has not been studied. In this paper, we do the evaluation by applying genetic algorithm to measure firing completion times when PARAdeg processors, and less and more processors are provided for 400 program nets. Our experimental results show that the firing completion times decrease rapidly with increase of processors till PARAdeg and slowly when processors are increased to more than PARAdeg, which implies PARAdeg is a reasonable standard to measure parallelism of program nets.

  • Separation of Narrow Bandwidth Spectral Light from Femtosecond Pulses Using Optical Coupler with Fiber Grating

    Asako BABA  Hitomi MORIYA  Shin-ichi WAKABAYASHI  Yukio TOYODA  Yoshinori TAKEUCHI  

     
    PAPER-Fibers

      Vol:
    E83-C No:6
      Page(s):
    824-829

    We have developed spectral separation devices for processing femtosecond pulses. These devices are based on an optical coupler structure with fiber gratings. In a computer simulation, we confirmed that these devices could extract <1 nm bandwidth light with 80% efficiency. We fabricated the spectral separation devices using single mode fibers and highly Ge-doped fibers. These devices successfully extracted narrow spectral light of 0.3 nm bandwidth with 37% efficiency from femtosecond pulses of 40 nm bandwidth. We also fabricated 2-channel spectral separation devices, which could extract the light from each grating channel.

  • Majority Algorithm: A Formation for Neural Networks with the Quantized Connection Weights

    Cheol-Young PARK  Koji NAKAJIMA  

     
    PAPER

      Vol:
    E83-A No:6
      Page(s):
    1059-1065

    In this paper, we propose the majority algorithm to choose the connection weights for the neural networks with quantized connection weights of 1 and 0. We also obtained the layered network to solve the parity problem with the input of arbitrary number N through an application of this algorithm. The network can be expected to have the same ability of generalization as the network trained with learning rules. This is because it is possible to decide the connection weights, regardless of the size of the training set. One can decide connection weights without learning according to our case study. Thus, we expect that the proposed algorithm may be applied for a real-time processing.

  • Migration Transparency in Agent Systems

    Bruno SCHULZE  Edmundo R. M. MADEIRA  

     
    PAPER-Mobile Agents

      Vol:
    E83-B No:5
      Page(s):
    942-950

    Migration transparency is considered in the context of multi-agent systems. A mobile agent architecture is proposed with an Availability service and a Transparency interface. We define mobility as explicit (or proactive) when the agent decides when and where to move and define mobility as implicit (i. e. , transparent or reactive) when it is a consequence of changes in the environment. Implicit mobility of agents is explored in addition to the usual explicit mobility. The search for a target agent (or agency) follows a transparent location and selection. The client agent preferably moves towards the target agent. If not possible, the target agent will move towards the client agent when calling back. If both agents can not move then the execution takes place remotely or is abandoned. Transparency is goal oriented.

  • RP-Reconstructing ARP Strategy for Micro-Cellular Systems

    Hiromasa FUJII  Kouhei MIZUNO  Takahiko SABA  Iwao SASASE  

     
    PAPER-Wireless Communication Switching

      Vol:
    E83-B No:5
      Page(s):
    1122-1127

    In cellular systems, autonomous reuse partitioning (ARP) is one of the channel assignment strategy which attains the high spectral efficiency. In the strategy, the movement of mobile stations (MSs) causes the disturbance of reuse partition. Furthermore the smaller cell size causes the spectral efficiency worse. In this paper, we propose a new ARP strategy with reuse partitioning reconstructing, named RP-reconstructing ARP strategy, for microcellular systems. We evaluate the performance of the proposed strategy with blocking rate and forced call termination rate by the computer simulation. The results show that the system with the proposed strategy accommodates 1.5 times as many users as the system with ARP does.

  • On Reconfiguration Latency in Fault-Tolerant Systems

    Hagbae KIM  Sangmoon LEE  Taewha HONG  

     
    LETTER-Fault Tolerance

      Vol:
    E83-D No:5
      Page(s):
    1181-1182

    The reconfiguration latency defined as the time taken for reconfiguring a system upon failure detection or mode change. We evaluate it quantitatively for backup sparing, which is one of the most popular reconfiguration methods, by investigating the effects of key parameters.

  • Parallelizing SDP (Sum of Disjoint Products) Algorithms for Fast Reliability Analysis

    Tatsuhiro TSUCHIYA  Tomoya KAJIKAWA  Tohru KIKUNO  

     
    LETTER-Fault Tolerance

      Vol:
    E83-D No:5
      Page(s):
    1183-1186

    The SDP (Sum of Disjoint Products) approach is a well-known technique for computing network reliability measures. So far several algorithms have been developed based on this approach. In this letter, we present a general framework for parallelization of these SDP algorithms. Based on the framework, we implemented a parallel version of an SDP algorithm called CAREL on a network of workstations. Experimental results show that it works fairly well with almost linear speedups.

  • Practicability of Autonomous Decentralized Scheduling Method for a Metal Mold Assembly Process

    Hitoshi IIMA  Norihisa ICHIMI  Nobuo SANNOMIYA  Yasunori KOBAYASHI  

     
    PAPER-Novel Applications

      Vol:
    E83-B No:5
      Page(s):
    1060-1066

    In this paper, a new approach is proposed for solving a real scheduling problem in a metal mold assembly process. This process is of a job-shop type, and the problem is large-scale and has complicated constraints. In this problem precedence relations exist not only among operations but also among jobs. The system has several types of single function machines and a type of multi-function machine. Furthermore, the number of machines belonging to each type is not single but plural. Therefore the selection of machine is necessary for executing each operation. An autonomous decentralized scheduling method is applied to this problem. In this method, a number of decision makers called modules cooperate with one another in order to attain the goal of the overall system. They determine the scheduling plan on the basis of their cooperation and the satisfaction of their own objective function levels. Particularly, the practicability of this method is considered through numerical results.

  • High-Availability Scheme for Shared Servers of Cluster Systems Using Commands Transfer

    Yuzuru MAYA  Soichi ISONO  Akira OHTSUJI  

     
    PAPER-Computer Systems

      Vol:
    E83-D No:5
      Page(s):
    1073-1081

    For cluster systems consisting of multiple processing nodes and shared servers which consist of an on-line and a backup shared server, we propose a hot-standby scheme for shared servers. In this scheme for shared servers, when the on-line shared server receives a command from a node, it sends only an update command and its data identifier to the backup shared server. Both the on-line and the backup shared server execute the update command independently, and the command result of the on-line shared server is identical to that of the backup shared server. When the on-line shared server fails, the backup reconstructs the shared data by using its own shared data and the user data from each node. We evaluated the system recovery time and the performance overhead for this hot-standby scheme. It enables the performance overhead to be ignored, and the system recovery time to be shortened to 20 seconds in cluster systems.

  • Experimental Characterization and Modeling of Transmission Line Effects for High-Speed VLSI Circuit Interconnects

    Woojin JIN  Seongtae YOON  Yungseon EO  Jungsun KIM  

     
    PAPER

      Vol:
    E83-C No:5
      Page(s):
    728-735

    IC interconnect transmission line effects due to the characteristics of a silicon substrate and current return path impedances are physically investigated and experimentally characterized. With the investigation, a novel transmission line model is developed, taking these effects into account. Then an accurate signal delay on the IC interconnect lines is analyzed by using the transmission line model. The transmission line effects of the metal-insulator-semiconductor IC interconnect structure are experimentally verified with s-parameter-based wafer level signal-transient characterizations for various test patterns. They are designed and fabricated with a 0.35 µm CMOS process technology. Throughout this work, it is demonstrated that the conventional ideal RC- or RLC-model of the IC interconnects without considering these detailed physical phenomena is not accurate enough to verify the pico-second level timing of high-performance VLSI circuits.

  • Applying the Adaptive Agent Oriented Software Architecture to the Parsing of Context Sensitive Grammars

    Babak HODJAT  Makoto AMAMIYA  

     
    PAPER-Cooperation in Distributed Systems and Agents

      Vol:
    E83-D No:5
      Page(s):
    1142-1152

    Adaptive Agent Oriented Software Architecture (AAOSA) is a new approach to software design based on an agent-oriented architecture. In this approach, agents are considered adaptively communicating concurrent modules that are divided into a "white box" module responsible for communications and learning and a "black box" which is responsible for the independent specialized processes. An AAOSA system is actually parsing input in the interpretation phase. We will show that AAOSA can be applied to the parallel, and distributed parsing of context sensitive languages.

2101-2120hit(2741hit)