We describe a new multiport memory which is called Shared DRAM (SHDRAM) to overcome bus-bottle neck problem in parallel processor system with shared memory. The processors are directly connected to this SHDRAM without conventional common bus. The test chip with 32 kbit memory cells is fabricated using a 1. 5 µm CMOS technology. The basic operation is confirmed by the circuit simulation and experimental results. In addition, it is confirmed by the computer simulation that the system performance with SHDRAM is superior to that with conventional common buses.

The objective of thinning is to reduce the amount of information in image patterns to the minimum needed for recognition. Thinned image helps the extraction of important features such as end points, junction points, and connections from image patterns. The ultimate goal of parallel algorithms is to minimize the execution time while producing high quality thinned image. Though much research has been performed for parallel thinning algorithms, there has been no systematical approach for comparing the execution speed of parallel thinning algorithms. Several rough comparisons have been done in terms of iteration numbers. But, such comparisons may lead to wrong guides since the time required for iterations varies from one algorithm to the other algorithm. This paper proposes a formal method to analyze the performance of parallel thinning algorithms based on PRAM (Parallel Random Access Machine) model. Besides, the quality of skeletons, robustness to boundary noise sensitivity, and execution speed are considered. Six parallel algorithms, which shows relatively high performance, are selected, and analyzed based on the proposed analysis method. Experiments show that the proposed analysis method is sufficiently accurate to evaluate the performance of parallel thinning algorithms.

For transmission of video signals, it is important that the system allows a certain degree of flexibility in bit rate as well as quality, depending upon the requirements of media and channel conditions. In this paper, we discuss the hierarchical transmission of Huffman code using multi-code/multi-rate DS/SS system to realize flexible transmission. We first discuss and show that the structure of Huffman code tree directly expresses hierarchical structure, and that parallel transmission of Huffman code can achieve hierarchical transmission. By assigning different transmission data rate to the bits in each stratum, it is possible to transmit different amount of information from each stratum. Further, we show the quality of each of the stratum can easily controlled by an appropriate power distribution to each parallel transmission branch.

In designing ASIPs (Application Specific Integrated Processors), the papers investigated so far have almost focused on the optimization of the CPU core and did not pay enough attention to the optimization of the RAM and ROM sizes together. This paper overcomes this limitation and proposes an optimization algorithm to define the best ratio between the CPU core, RAM and ROM of an ASIP chip to achieve the highest performance while satisfying design constraints on the chip area. The partitioning problem is formalized as a combinatorial optimization problem that partitions the operations into hardware and software so that the performance of the designed ASIP is maximized under given chip area constraint, where the chip area includes the HW cost of the register file for a given application program with associated input data set. The optimization problem is parameterized so that it can be applied with different technologies to synthesize CPU cores, RAMs or ROMs. The experimental results show that the proposed algorithm is found to be effective and efficient.

Parallel multiple context-free grammar (PMCFG) and multiple context-free grammar (MCFG) were introduced to denote the syntax of natural languages. By the known fastest algorithm, the recognition problem for multiple context-free language (MCFL) and parallel multiple context-free language (PMCFL) can be solved in O(ne) time and O(ne+1) time, respectively, where e is a constant which depends only on a given MCFG or PMCFG. In this paper, we propose the following two algorithms. (1) An algorithm which reduces the recognition problem for MCFL to the boolean matrices multiplication problem. (2) An algorithm which reduces the recognition problem for PMCFL to the recognition problem for MCFL. The time complexity of these algorithms is O(ne-3i+1 M(ni)) where e and i are constants which depend only on a given MCFG or PMCFG, and M(k) is the time needed for multiplying two k k boolean matrices. The proposed algorithms are faster than the known fastest algorithms unless e=e, i=1 for MCFG, and e=e, i=0 for PMCFG.

A partial buffer sharing scheme is proposed as loss-priority control for a finite buffer with batch inputs. A partial batch acceptance strategy is used for a batch arriving at a finite buffer. Customer loss probabilities for high- and low-priority customers are derived under this batch acceptance strategy, using a supplementary variable method that is a standard tool for queueing analysis. A comparison of the partial buffer sharing scheme and a system without loss-priority control is made in terms of admissible offered load.

Backfire quadrifilar helical antennas combined with parasitic loops are investigated in detail, focusing on clarifying the function of parasitic loops. First, the basic property is examined for the case of one parasitic loop, and it is found that the loop behaves as a director when the circumferential length of the loop is nearly 0. 9λ, and a reflector when the circumferential length of the loop is nearly 1. 2λ provided the distance between the parasitic loop and the top plane of helical antennas is approximately 0. 1λ, where λ is the wavelength. Next, the function of the parasitic loop is investigated by comparing the current distributions on the helices and the loop with those on a monofilar helix with a ground plane. It is found that the function of the parasitic loop is quite different from that of the ground plane. Then, the case of two parasitic loops is examined, and it is shown that the use of two parasitic loops is very effective and simple measures to control the radiation pattern and gain of the backfire quadrifilar helical antennas. Finally, for this type of antennas with two parasitic loops, an example of structural parameters suited to the use in satellite communications is presented.

In order to enhance the energy transfer efficiency in a Cherenkov laser, we propose to use a tapered waveguide with a dielectric thickness properly varied stepwise in the longitudinal direction. With the aid of particle simulation, we investigate the nonlinear characteristics of the Cherenkov laser with the tapered waveguide, demonstrating the effectiveness of our proposal for efficiency enhancement.

Reducing communication overhead is a key goal of program optimization for current scalable multiprocessors. A well-known approach to achieving this is to map tasks (indivisible units of computation) to processors so that communication and computation overlap as much as possible. In an earlier work, we developed a look-ahead scheduling heuristic for efficiently reducing communication overhead with the aim of decreasing the completion time of a given parallel program. In this paper, we report on an extension of the algorithm, which fills in the idle time slots created by interprocessor communication without increasing the algorithm's time complexity. The results of experiments emphasize the importance of optimally filling idle time slots in processors.

This paper presents a performance comparison between the single-stream and the multi-stream approaches to lip synchronization of live media (voice and video). The former transmits a single transport stream of interleaved voice and video, while the latter treats the two media as separate transport streams. Each approach has an option not to exert the synchronization control at the destination, which leads to four basic schemes. On an interconnected ATM-wireless LAN, we implemented the four basic schemes with RTP/RTCP on top of UDP and two variants which exercise dynamic resolution control of JPEG video. Making the performance measurement of the six schemes, we compare them to identify and evaluate advantages and disadvantages of each approach. We then show that the performance difference between the two approaches is small and that the dynamic resolution control improves the synchronization quality.

In ATM Network, the VBR (Variable Bit Rate) service category is used to accommodate TCP/IP traffic. In an international ATM network with large propagation delay, higher TCP throughput can be obtained by use of window scale option. In order to accommodate TCP traffic with window scale option effectively, it is required to select appropriate values of VBR parameters, i. e. SCR (Sustainable Cell Rate) and MBS (Maximum Burst Size), and to evaluate the impact of UPC (Usage Parameter Control) function on TCP throughput. We have studied those technical issues for the conventional TCP, but the results cannot be applied to TCP traffic with the window scale option due to the TCP terminal performance and the large window size. In this paper, we proposed VBR parameter determination method for TCP with the window scale option and evaluated the values in each condition. These results show that the determined MBS is much smaller than the burst length of TCP segments especially using low performance TCP terminals. Furthermore, we also discuss some experimental results of TCP throughput degradation due to UPC function. It shows that the throughput of TCP with large window size is degraded when the SCR and MBS values used in ATM switch are smaller than the determined values.

This paper proposes a scalable multiecho cancellation system based on multiple autonomic and distributed echo canceler units. The proposed system does not have any common control section. Distributed control sections are equipped with in multiple echo cancelers operating autonomically. Necessary information is transferred from one unit to the next one. When the number of echoes to be canceled is changed, the necessary number of echo canceler units, each of which may be realized on a single chip, are simply plugged in or unplugged. The proposed system also provides fast convergence thanks to the novel coefficient location algorithm which consists of flat-delay estimation and constrained tap-position control. The input signal is evaluated at each tap to determine when to terminate flat-delay estimation. The number of exchanged taps is selected larger in flat-delay estimation than in constrained tap-position control. The convergence time with a colored-signal input is reduced by approximately 50% over STWQ, and 80% over full-tap NLMS algorithm. With a real speech input, the proposed system cancels the echo by about 20 dB. Tap-positions have been shown to be controlled correctly.

Array redistribution is required very often in programs on distributed memory parallel computers. It is essential to use efficient algorithms for redistribution, otherwise the performance of programs may degrade considerably. In this paper, we focus on automatic generation of communication routines for multi-dimensional redistribution. The principal advantage of this work is to gain the ability to handle redistribution between arbitrary source and destination processor sets and between arbitrary source and destination distribution schemes. We have implemented these algorithms using Parallelware communication library. Some experimental results show the efficiency and flexibility of our techniques compared to the other redistribution works.

In this paper, Orthogonal Multicode OFDM-DS/CDMA system using Partial Bandwidth Transmission is proposed. By using the flexible carrier allocation of OFDM, Partial Bandwidth Transmission is considered for high quality communication. Furthermore, multicode packet data transmission is presented. Multicode packet data transmission is very effective to handle variable data. Since the proposed system can detect the header information without complex control, it is also suitable for packet data transmission. The computer simulation results show that the BER performance of the proposed system with the ideal channel estimation is improved compared with the case of the conventional Orthogonal Multicode DS/CDMA system with ideal RAKE receivers. Moreover the proposed system with the channel estimation by MLS algorithm also shows the good BER performance. In packet data transmission, the delay and throughput performances are also improved in the proposed system.

In the task of forming high-level object-centered models from low-level image-based features, parts serve as an intermediate representation. A representation of parts for object recognition should be rich, stable, and invariant to changes in the viewing conditions. In addition, it should be capable of describing partially occluded shapes. This paper describes a method for decomposing shapes into parts. The method is based on pairs of negative curvature minima which have a good continuation at their boundary tangents. A measure of good continuation is proposed by using the coefficients of cocircularity, smoothness, and proximity. This method could recover parts in a direct computation, therefore efficient in calculation than the former. Currently, we assume that the shape is a closed planar curve.

Resonant properties of resistively shunted tunnel junctions dominate the high-frequency performance of Josephson array oscillators. To improve the operating frequency, we have developed resistively shunted Nb/AlOx/Nb tunnel junctions with a small parasitic inductance. The inductance was minimized by reducing the inductive length between the tunnel junction and the contact hole to be about 1µm. By fitting the measured I-V characteristics of the shunted tunnel junction to the simulated characteristics, we estimated the inductance to be about 105 fH. The analysis of resonant properties showed that the shunted tunnel junctions with the small parasitic inductance have a high-frequency performance up to the Nb gap frequency. Josephson array oscillators using 11 such junctions were designed and fabricated to operate at 650 GHz and 1 THz. Shapiro steps induced by Josephson oscillation were clearly observed up to 1 THz. By fitting the step heights to the simulated results, we estimated the output power of the Josephson oscillator delivered to the load resistor to be about 10 µW at 625 GHz and 50 nW at 1 THz.

In the commonsense reasoning, priorities among rules are often required to be found out in order to derive the desired conclusion as a theorem of the reasoning. In this paper, first we present the bottom-up and top-down abduction procedures to compute skeptical explanations and secondly show that priorities of circumscription to infer a desired theorem can be abduced as a skeptical explanation in abduction. In our approach, the required priorities can be computed based on the procedure to compute skeptical explanations provided in this paper as well as Wakaki and Satoh's method of compiling circumscription into extended logic programs. The method, for example, enables us to automatically find the adequate priority w. r. t. the Yale Shooting Problem to express a human natural reasoning in the framework of circumscription.

In general, the performance of partial response maximum-likelihood (PRML) system is degraded by nonlinear distortion and high frequency noise in high-density digital magnetic recording. Conventional PRML system for single-track recording improves the performance when high order PRML systems and high rate codes are adopted. But, in general it is difficult to realize LSI circuits for high order PRML system and high rate code. In this paper, a trellis coded class four partial response maximum-likelihood (TC-PR4ML) system for high density two-track digital magnetic recording is proposed. Our two-track recording method can increase the coding rate over 1, which contributes to a decrease in both degradation effects from partial erasure, one of nonlinear distortions, and high frequency noise in high density recording. The error rate performance of the proposed system is obtained by computer simulation taking account of the partial erasure and it is compared with that of a conventional NRZ coded class four partial response maximum-likelihood (NRZ-PR4ML) system. The results show that the proposed system is hardly affected by partial erasure and keeps good performance in high density recording.

This paper describes a new method for learning bilingual collocations from sentence-aligned parallel corpora. Our method comprises two steps: (1) extracting useful word chunks (n-grams) in each language by word-level sorting and (2) constructing bilingual collocations by combining the word-chunks acquired in stage (1). We apply the method to a two kinds of Japanese-English texts; (1) scientific articles that comprise relatively literal translations and (2) more challenging texts: a stock market bulletin in Japanese and its abstract in English. In both cases, domain specific collocations are well captured even if they were not contained in the dictionaries of specialized terms.

We describe several properties of very thin stacks of 10 to 20 intrinsic Josephson junctions fabricated on the surface of Bi2Sr2CaCu2O8+δ single crystals. We show that the Joule heating is significantly reduced in these stacks and that the gap structure is clearly observable in the quasiparticle current-voltage (I-V) characteristics. The I-V curves are characterized by a large subgap conductance and a significant gap suppression due to the injection of quasiparticle current. It is found that the IcRn product of these intrinsic Josephson junction stacks is significantly small compared with that expected from the BCS theory. It is also found that there is a tendency that IcRn decreases with increasing c-axis resistivity. Both Ic and the gap voltage exhibit unsaturated temperature dependence at low temperatures. The behavior presents a sharp contrast to that of Josephson junctions made of conventional superconductors. The characteristics are discussed in relation to the d-wave symmetry of the order parameter.