A broadband access network is required for supporting the increased Internet data traffic. One of the most cost-effective solutions is the Ethernet Passive Optical Networks (E-PONs) with the efficient bandwidth assignment function by which the upstream bandwidth can be shared among access users. To satisfy the services with heterogeneous QoS characteristics, it is very important to provide QoS guaranteed network access while utilize the bandwidth efficiently. In this paper, a dual DEB-GPS scheduler in E-PON is presented to provide delay-constraint and lossless QoS guarantee to QoS service and maximize the bandwidth to best-effort service. Simulation results show our scheme outperforms the conventional bandwidth allocation scheme in E-PON system.

To sample a band-limited analog signal directly from the high frequency down to the baseband for the digital signal processing with significantly reduced computation, several concepts of the bandpass sampling are introduced. In this paper, a robust bandpass sampling scheme when there exist frequency deviations due to the channel effect and hardware instability is proposed for practical use, and the effects of the frequency deviations are discussed to select a proper sampling frequency.

In this paper, the problem of output feedback passification for nonlinear systems is considered. Contrary to the conventional methodologies, our approach does not require the normal form representation of the system. Consequent advantages include that the system need not have a well-defined relative degree. In particular, we present a necessary and sufficient condition for output feedback passification without relying on the normal form. The proposed condition finally leads to an extension for a recent result when the system does have a normal form.

Recently, Hwang and Yeh demonstrated that Peyravian-Zunic's password authentication scheme is vulnerable to several attacks, and then proposed a modified version. In this letter, we show that Hwang-Yeh's scheme still has several weaknesses and drawbacks.

This paper presents an innovative 155Mb/s burst-mode laser transmitter chip, which was designed and successfully demonstrated, and contains several new subsystems: a digitally programmed current source, programmable up to 120mA with a resolution of 0.1mA, a fast but accurate intermittent optical level monitoring circuit, and a digital Automatic Power Control (APC) algorithm. This generic and intelligent chip was developed in a standard digital 0.35µm CMOS process. Extensive testing showed a high yield and algorithm stability, as well as excellent performance. During initialization, when the transmitter is connected to the Passive Optical Network (PON) for the first time, maximum three Laser Control Fields (LCF) are needed, with a length of 17bytes (0.88microsecond at 155Mb/s), to stabilize the laser output power. In this short time, the chip can regulate the launched optical output power of any FSAN (Full Service Access Network) compliant laser diode to the required level, even in the extreme circumstances caused by outdoor operation or by battery backup operation during power outages. Other tests show that the chip can further stabilize and track this launched optical power with a tolerance lower than 1dB over a wide temperature range, during the burst mode data transmission. The APC algorithm intermittently adjusts the optical power to be transmitted in a digital way, starting from loosely specified but safe preset values, to the required stable logic "1" and "0" level. No laborious calibration of the laser characteristic curve and storage of the calibration values in lookup tables are needed, nor any off-chip adjustable component. The power consumption is significantly reduced by disabling inactive circuitry and by gating the digital high-speed clock. Although this laser transmitter was developed for FSAN PON applications, which are standardized at a speed of 155Mb/s upstream, the design concept is quite generic and can be applied for developing a wide range of burst mode laser transmitters, such as required for Gigabit PON systems or other TDMA networks.

We will present a novel core mode blocker fabricated with hydrogen loaded Ge-B co-doped fiber exposed to the electric arc discharge using local heat exposure. Tunable bandpass filter based on cascaded LPFGs with a core mode blocker inserted between the LPFGs will be also described. The characteristics are: 6.5-nm bandwidth, 30-nm tuning range, and 15-dB dynamic range, respectively. It can be very useful for application to wavelength stabilization and physical sensors.

Following the developments in the use of ID-based schemes and smart cards, Yang and Shieh proposed two password authentication schemes to achieve two purposes: (1) to allow users to choose and change their passwords freely, and (2) to make it unnecessary for the remote server to maintain a directory of passwords or a verification table to authenticate users. Recently, Chan and Cheng showed that Yang and Shieh's timestamp-based password authentication scheme is insecure against forgery. In this paper, we point out that Chan and Cheng's forgery attack can not work. Thus, we further examine the security of Yang and Shieh's password authentication schemes and find that they are insecure against forgery because one adversary can easily pretend to be a valid user and pass the server's verification which allows the adversary to login to the the remote server.

A pass-transistor logic is enhanced with a bootstrap configuration for sub-1 V operation at high speed and low power. The bootstrap configuration drives the output to full swing, which accelerates the signal transition and cuts off the short-circuit current of subsequent CMOS logic gates. The asynchronous or synchronous timing sequence of the input (drain) and the control (gate) signals ensures bootstrap operation. A 1-b arithmetic logic unit (ALU) and an EXNOR gate built with the bootstrap pass-transistor logic outperforms those built with other types of pass-transistor logic. An experimental 16-b pass-transistor adder operates down to 0.4 V with a delay time of 4.2 ns and a power dissipation of 2.8 µ W/MHz at 0.5 V.

A four-pole quasi-elliptic function bandpass filter is designed and fabricated using a miniaturized microstrip square Stepped Impedance Resonator (SIR). The Nonuniform Finite Difference Time Domain (NUFDTD) method is used to design the resonator and to calculate the coupling coefficients of three basic structures. Theoretical and experimental results are presented. This filter is not only compact size but also has a wide upper stop band.

A high temperature superconductor (HTS) 5 GHz 10-pole bandpass filter (BPF) is designed by using coplanar waveguide (CPW) quarter-wavelength resonators. The 10-pole Chebyshev BPF has a center frequency 5.0 GHz and a fractional bandwidth 3.2%. Based on an equivalent circuit with J- and K-inverters, the filter is first designed by using an EM simulator. Next an optimization algorithm is employed to diagnose the discrepancy between the filter responses calculated by the EM simulator and the equivalent circuit. Adjustment of the dimensions of the filter is made thereby. The frequency response of the adjusted filter satisfies well the design specifications.

A design methodology of bandpass filters (BPFs) using λ/4 resonators for improving out-of-band characteristics is proposed. Firstly, the basic characteristics of various λ/4 resonators are examined. In this study, we focus on four types of λ/4 resonators, i.e., (1) direct-coupled λ/4 resonator, (2) loaded-element λ/4 resonator, (3) tapped λ/4 resonator and (4) loaded-element tapped λ/4 resonator. Secondly, the application examples of BPFs with improved out-of-band characteristics are provided. We examine the improvement of filter characteristics, i.e., sharp skirt characteristics and low spurious responses. The results of this study lead us to the conclusion that the methodology is very useful for improving the out-of-band characteristics of the BPFs using the λ/4 resonators.

Basic characteristics of a short-ended half-wavelength resonator made of a coplanar waveguide (CPW) and their applications to bandpass filters (BPFs) are discussed. The first part of this paper gives the essence for improving out-of-band characteristics of the BPF by describing the basic characteristics of a tap-coupled resonator. Secondly, a new BPF with attenuation poles using the short-ended half-wavelength CPW resonators is proposed and realized. It is confirmed that our methodology is useful for improving out-of-band characteristics of the BPF using the short-ended half-wavelength CPW resonators without complicated filter design.

This paper introduces a way to realize high-pass, band-stop and all-pass transfer functions using two-integrator loop structure consisting of loss-less and lossy integrators. The basic circuit configuration is constructed with five Operational Transconductance Amplifiers (OTAs) and two grounded capacitors. It is shown that the circuit can realize their circuit transfer functions by choosing the input terminals, and that the circuit parameters can also be independently set by the transconductance gains with the proportional block. Although the basic circuit configuration has been known, it seems that the feature for realizing the high-pass, the band-stop and the all-pass transfer functions makes the structure more attractive and useful. An example is given together with simulated results by PSPICE.

Most network systems provide an authentication mechanism based on a user identification number and a password. In such systems, it is easy to obtain a user's password using a sniffer program with illegal eavesdropping. The one-time password method and the challenge-response method are useful authentication schemes that protect a user's password against eavesdropping. In client/server environments, the one-time password scheme using time is especially useful because it solves the synchronization problem. However, it has a problem of time-slippage, and this problem causes the authentication to be failed. In this paper, we propose an effective one-time password algorithm, which solves the time-slippage problem through the use of 1-bit information, which denotes the duration in which the authentication could be failed because of time-slippage. This algorithm can be added easily and quickly to current one-time password systems using time without requiring any change of protocols.

Recently, Lin et al. addressed two weaknesses of a new strong-password authentication scheme, the SAS protocol, and then proposed an improved one called the OSPA (Optimal Strong-Password Authentication) protocol. However, we find that both the OSPA protocol and the SAS protocol are vulnerable to the stolen-verifier attack.

Using the great one-time password concept, the widely utilized one-way authentication scheme S/Key provides well protection against replay attacks. In this paper, S/key is enhanced to secure transactions in a critical environment. The proposed scheme is free from any of server spoofing attacks, preplay attacks, and off-line dictionary attacks. A session key here is also established to provide confidentiality. Moreover, simplicity and efficiency are taken into consideration from the user's point of view. A smart card is applied to simplify the user login process and only the hash function is used to keep its efficiency. Therefore, the scheme proposed hereinafter is able to build a safer shield for sensitive transactions like on-line banking or on-line trading in bonds and securities.

In this paper, we propose a pretty-simple password-authenticated key-exchange protocol, which is proven to be secure in the standard model under the following three assumptions. (1) DDH (Decision Diffie-Hellman) problem is hard. (2) The entropy of the password is large enough to avoid on-line exhaustive search (but not necessarily off-line exhaustive search). (3) MAC is selectively unforgeable against partially chosen message attacks, (which is weaker than being existentially unforgeable against chosen message attacks).

This paper proposes a design method of 2-D variable IIR digital filters with high frequency tuning accuracy. In the proposed method, a parallel complex allpass structure is used as the prototype structure of the 2-D variable digital filters in order to obtain low sensitivity characteristic. Because the proposed 2-D variable digital filter is composed of first-order complex allpass sections connected in parallel, the proposed variable digital filter possesses several advantages such as low sensitivity characteristic in the passband, simple stability monitoring and high parallelism. In order to improve the frequency tuning accuracy of the proposed variable digital filter, each first-order complex allpass section is substituted by a new first-order complex allpass section with low sensitivity characteristic. Moreover, the coefficient sensitivity analysis of a 2-D parallel complex allpass structure is presented. Numerical examples show that the proposed 2-D variable IIR digital filter has high tuning accuracy under the finite coefficient wordlength.

This paper presents a multiple-valued logic-in-memory circuit with real-time programmability. The basic component, in which a dynamic storage function and a multiple-valued threshold function are merged, is implemented compactly by using charge storage and capacitive coupling with a DRAM-cell-based circuit structure under a 0.8-µm CMOS technology. The pass-transistor network using these basic components makes it possible to realize any multiple-valued-inputs binary-outputs logic circuits compactly. As a typical example, a fully parallel multiple-valued magnitude comparator is also implemented by using the proposed DRAM-cell-based pass-transistor network. Its execution time and power dissipation are reduced to about 11 percent and 29 percent, respectively, in comparison with those of a corresponding binary implementation. A prototype chip is also fabricated to confirm the basic operation of the proposed DRAM-cell-based logic-in-memory circuit.

A novel self-alignment process using the surface tension of the liquid resin for assembly of electronic or optoelectronic devices in 3-D space has been proposed. The vertical alignment can be controlled by using of metal sphere, reducing the necessary precise process control such as solder volumes and external forces, and allowing large tolerances in liquid volume and misalignment. Lateral alignment could be also achieved by making the liquid resin constrained on the 3-dimensional pads on chip and substrate. This study focused on the principle of self-alignment and final alignment accuracy. In addition, the possibility of self-alignment process was verified by analytic numerical method and scaled-up experiment. An average alignment accuracy of less than 0.25 µm has been obtained. It is thought that this process is effective for assembly simply at low process temperature, low cost and without flux in future assembly techniques.