We propose an InGaAlAs waveguide p-i-n photodiode (WG-PD) with a thick symmetric double-core for surface-hybrid integration onto optical platforms, which can be applied to low cost optical modules for access networks. The waveguide structure is designed to efficiently couple to flat-ended single mode fibers while maintaining low-voltage (less than 2 V) operation. Crystal growth conditions and a passivation technique are also investigated for obtaining high responsivity, low dark current and highly reliable operation. Fiber-coupled responsivity as high as 0.95 A/W, at a 1.3-µm wavelength, and vertical coupling tolerance as wide as 2.6 µm are demonstrated for a dispersion-shifted fiber (DSF) coupling at an operating voltage of 2 V. Dark current is as low as 300 pA at 25 and 12 nA at 100. A temperature accelerated aging test is performed to show the feasibility of using the WG-PD in long-term practical applications.

To realize a low-cost WDM transceiver module based on a PLC-platform, simple, assembly techniques have been successfully developed. The formation of index marks with an accuracy of below 0.1 µm has made it possible to mount Opto-electronic devices on the silicon terrace of the PLC-platform by a passive alignment. A newly developed trench formation technique for inserting a 1.3/1.5 µm WDM dielectric filter enabled us not only to ensure a stable WDM function but also to prevent excess loss associated with the dielectric filter scheme. It is found that these two technologies are practically useful to achieve high-performance WDM transceiver module.

This paper describes the technological issues in achieving a low-cost hybrid WDM module for access network systems. The problems which should be resolved in developing a low-cost module are clarified from the viewpoint of the module assembly in mass production. A design concept for a low-cost module suitable for mass production is indicated, which simplifies the alignment between a laser diode and a waveguide, and reduces the number of the components such as lenses and mirrors. The low-cost module is achieved by employing a flip-chip bonding method with passive alignment using a spot-size converter integrated laser diode (SS-LD) and p-i-n waveguide photodiodes (WGPDs) on a planar lightwave circuit (PLC) platform. We confirm that the SS-LD and the WGPD provide high coupling efficiency with a large tolerance for passive alignment. To achieve a high-sensitivity receiver, the module is designed to employ an asymmetric PLC Y-splitter that prefers a PD responsivity to an LD output power because of the high-coupling efficiency of the LD, and to employ a bare preamplifier mounting to reduce the parasitic capacitance into a preamplifier. We also demonstrate the dynamic performance for a 50-Mb/s burst signal, such as a high sensitivity, an instantaneous AGC response, and a small APC deviation of the transceiver.

This paper is devoted to a new design method for infinite impulse response approximate inverse system of a nonminimum phase system. The design is carried out such that the convolution of the nonminimum phase polynomial and its approximate inverse system can be represented by an approximately linear phase all-pass filter. A method for estimating the time delay and order of an approximate inverse system is also presented. Using infinite impulse response approximate inverse systems better accuracy is achieved with reduced computational complexity. Numerical examples are included to show the effectiveness of the proposed method.

For the dependent protocols to perform the server-aided RSA secret computation, the damage caused by the active attacks is greater than that by the passive attacks. Though there are two dependent proposed protocols against active attacks, the cost of the two protocols is still high. In this paper, we propose two efficient dependent protocols. Even considering the low cost of these two protocols, they can also guard against the proposed active attacks.

Regenerative Pass-transistor Logic (RPL), a modular dual-rail circuit technique for high speed logic design that gives reasonably low power consumption, was developed. The technique can be applied to basic logic gates, full adders, multiplier units, and more complicated arithmetic logics like Conditional Carry Select (CCS) circuit. The magnitude of propagation delay time of RPL is smaller than the conventional CPL(Complementary Pass-transistor Logic), or DPL (Double Pass-transistor Logic). Low power consumption can also be achieved by reduced number of transistors and metal interconnections. Simulation and layout data also proved that RPL is advantageous over existing dual-rail logics while considering speed, power consumption and layout area.

For two devices whose quality is described by non-negative one-dimensional time-homogeneous diffusion processes of the Wiener and Ornstein-Uhlenbeck types sufficient conditions are given such that their failure times, modeled as first-passage times through the zero state, are ordered according to the likelihood ratio ordering.

This paper proposes a hierarchical parallel processing system for the multipass rendering method. The multipass rendering method based on the integration of radiosity and ray-tracing can synthesize photo-realistic images. However, the method is also computationally expensive. To accelerate the multipass rendering method, the system, called (Mπ)2, employs two kinds of parallel processing schemes. As a coarse-grain parallel processing, object-space parallel processing with multiple processing elements based on the object-space subdivision is adapted, and each processing element (PE) is equipped with multiple pipelined units for a fine-grain parallel processing. To balance load among the system, static load balancing at the PE level and dynamic load balancing at the pipelined unit level within the PE are introduced. Especially, we propose a novel static load allocation scheme, skewed-distributed allocation, which can effectively distribute a three-dimensional object space to one- or two-dimensional processor configuration of the (Mπ)2 system. Simulation experiments show that the two-dimensional (Mπ)2 systems with the skewed-distributed allocation outperform the three-dimensional systems with the non-skewed distributed allocation. Since lower dimensional systems can be built at a lower cost than higher dimensional systems, the skewed-distributed allocation will be meritorious. Besides, by the combination of static load balancing by the skewed-distributed allocation and the dynamic load balancing by dynamic ray allocation within each PE, the system performance can be further boosted. We also propose a cached frame buffer system to relieve access collision on a frame buffer.

Precise direct mounting of laser diode (LD) and photodiode (PD) chips on silica planar lightwave circuits (PLCs) has been investigated for application to transceiver modules. To achieve submicron optical alignment, self-aligned index marks on the PLCs and LDs were directly detected by transmission infrared light. The repeatability of the positioning was measured to be within 0.125 µm. The output power of the resultant module was 0.2 mW at 80 mA. A waveguide-type PD was also mounted in the same way, and module sensitivity of 0.25 A/W was demonstrated.

We proposed a new marker design for passive alignment of a laser to a fiber on a silicon waferboard. Our fiducial marker is simple form and easy to fabricate. With a unique marker design, high accurate positioning of the laser chip is easily achieved using a conventional flip-chip bonder. We have successfully fabricated laser modules with uniform coupling, within 1 dB for a flat end single-mode fiber and within 2 dB for a hemispherical end fiber. This assembly method offers the potential for low-cost optical module packaging.

The realization of scientific manufacturing of ULSIs in the 21st century will require the development of a technical infrastructure of "Ultra Clean Technology" and the firm establishment of the three principles of high performance processes. Three principles are 1)Ultra Clean Si Wafer Surface, 2)Ultra Clean Processing Environment, and 3)Perfect Parameter controlled process. This paper describes the methods of resolving the problems inherent in Ultra Clean Technology, taking as examples issues in quarter-micron or more advanced semiconductor process and manufacturing equipment, particularly when faced with the challenges of plasma dry etching. Issues indispensable to the development of tomorrow's highly accurate and reliable plasma dry etching equipment are the development of technologies for the accurate measurement of plasma parameters, ultra clean gas delivery systems, chamber cleaning technology on an in-situ basis, and simulating the plasma chemistry.This paper also discusses the standardization of semiconductor manufacturing equipment, which is considered one of the ways to reduce the steep rise in production line construction costs. The establishment of Ultra Clean Technology also plays a vital role in this regard.

This letter presents a new design method for approximate inverse systems using all-pass networks. The efficacy of approximate inverse systems for input and parameter estimation of nonminimum phase systems is well recognized. in the previous methods, only time domain design of FIR (finite impulse response) type approximate inverse systems were considered. Here, we demonstrate that IIR (infinite impulse response) type approximate inverse systems outperform the previous methods. A nonlinear optimization technique is adopted for designing the proposed system in the frequency domain. Numerical examples are also presented to show the effectiveness of the proposed method.

In arithmetic units multiplication is a very important operation. It is a common approach to use the modified Booth's algorithm to reduce the number of partial products in a multiplication and speed it up. In this letter we show two circuits that fuse the usually separate functions of generating the partial products and selecting them. The circuits designed in DPL (Double Pass-transistor Logic) are bigger in MOS transistors, but are faster and, function at higher frequencies than a typical CMOS implementation. One of our circuits also has lower power consumption.

In this paper, we propose a register file with data bypassing function. This register file bypasses data using data bypassing units instead of functional units when actual operation in functional units such as ALU is unnecessary. Applying this method to a general purpose microprocessor with benchmark programs, we demonstrate 50% power consumption reduction in functional units. Though length of bus lines increases a little due to an additional hardware in register file, as buses are not driven when data is bypassed, power consumption in bus lines is also reduced by 40% compared with the conventional architecture.

To connect among many radio base stations by using optical fiber bus link in microcellular system, subcarrier multiplexing (SCM) is excellent in simplicity and flexibility. But performance degradation due to optical beat noises is severe problem. To solve this problems, this paper proposes a new type of intercell connection bus fiber-optic link (ICBL) using time division multiplexing, called TDM-ICBL. This paper also analyzes transmission performance of TDM-ICBL theoretically and compares with SCM-ICBL. The analysis clarifies that while the number of RBSs connected to SCM-ICBL is severely restricted by beat noises, TDM-ICBL is more useful than SCM-ICBL when there are many number of connected RBSs.

This paper proposes a high throughput small latent IP packet delivery architecture using ATM technology in a large scaled internet. Data-link network segments, including ATM network segments, are interconnected through routers. A connection oriented IP packet delivery will be provided by IP (including both IPv4 and IPv6) with a certain resource reservation protocol (e.g. RSVP). When the router attached to ATM network segment has a mapping function between the flow-ID (e.g. in the SIPP header) and the VPI/VCI value, the small latent connection oriented IP forwarding can be provided. Also, when the router has cell-relaying functionality, the small latent connectionless IP forwarding can be provided, even in IPv4. The source router, where the source end-station belongs to, will be able to transfer the connectionless IP packet to the destination router, where the destination end-station belongs to, through the concatenated ATM connections (ATM-VCCs) without any ATM-VCC termination point. When all of the network segments are ATM-LAN, the proposed architecture can accommodate about up to 222 (4106) end-stations with two network layer processing points. And when the network is scaled up hierarchally, we can accommodate larger number of end-stations. For example, we can accommodate 1015 end-stations by a three layered network. Then the maximum number of actual network layer processing points between source and destination end-stations can be ten. Here, 1015 is the maximum number of end-stations in ISDN and also it is the target number of accommodated end-stations for IPv6.

In this paper, we discuss design of quadrature mirror filter (QMF) banks using digital allpass networks in the frequency domain. In the QMF banks composed of a parallel connection of two allpass networks, both aliasing error and amplitude distortion are always completely canceled. Therefore, we only need to design the analysis filters and eliminate phase distortion of the overall transfer function. We consider design of the QMF banks in two cases where phase responses of the filters are repuired or not required. In the case where the phase responses are not required, the design problem can be reduced to design of phase difference of two allpass networks. In the case where the phase responses are required, we present a procedure for designing the QMF banks with both equiripple magnitude and phase responses.

The fundamental TE10 mode in a rectangular waveguide of a square cross section is degenerate with TE01 mode. A quarter wavelength resonator made of a dielectric square waveguide is, therefore, applied for a small-sized bandpass filter, just like dual mode filters for base stations in the mobile communication. In this paper, the methods to couple the two modes are first studied, including cutting a corner of the resonator and adding some metal electrodes on its end face. Both methods help to flow the rf current of the odd mode at the corner, resulting in decrease of the series inductance and thus increase of the resonant frequency. The coupling constant, that is proportional to the difference of the odd and even-mode's resonant frequency, can be controlled by the perturbations mentioned above. The coupling to the external circuit is adjusted by an electrode fabricated also on the end face. It is connected to a microstrip line and capacitively couples to the resonant modes. The coupling strength increases with the dimension of the electrode. The adjustment of the resonant frequency is carried out by the similar electrode on the end face and connected to the center of the side of the square cross section. The frequency decreases with the length of the electrode. The unloaded Q is measured to be of around 500 for 5510 mm resonator of εr=93. The optimum aspect ratio for the resonator is found in terms of the Q value. The simplest bandpass filter, i.e., a two-stage bandpass filter is designed and fabricated using 5510 mm resonator. It is mounted in a square hole made in a printed circuit board and excited by a microstrip line. The frequency characteristics are in good agreement with the expected values.

This paper describes newly developed miniaturized stepped impedance resonators with a double coaxial structure (DC-SIR's) and their application to bandpass filters. The new DC-SIR's using dielectric material are devised for more compact and lower frequency bandpass filters. Fundamental characteristics such as resonance properties and unloaded-Q make it clear that DC-SIR's have attractive features that miniaturization can be achieved without Q-factor degradation. Trial 400 MHz bandpass filters incorporating DC-SIR's are also made. Experimental results of bandpass filters proved that DC-SIR's are applicable to lower frequency band radio equipment and able to contribute to the expansion of applicable frequency ranges of dielectric coaxial resonators.

The investigation of device functions required from the systems point of view will be important for the development of the next generation of VLSI devices and systems. In this paper, a super pass transistor (SPT) model is presented as a quantum device candidate for future VLSI systems based on multiple-valued logic. A possible quantum device structure for the SPT model is also described, which employs the concepts of a lateral-resonant-tunneling quantum-dot transistor and a heterostructure field-effect transistor. Since it has the powerful capability of detecting multiple signal levels, the SPT will be useful for the implementation of highly compact multiple-valued VLSI systems. To exploit the functionality of the SPT, a super pass gate (SP-gate) corresponding to a single SPT is proposed as a multiple-valued universal logic module. The mathematical properties of the SP-gate are discussed. A design method for a multiple-valued SP-gate network is presented. An application of SP-gates to a multiple-valued image processing system is also demonstrated. The SP-gate network for the multiple-valued image processing system is evaluated in comparison with the corresponding NMOS implementation in terms of the number of transistors, interconnections and cascaded transistor stages. The size of a generalized series-parallel SP-gate network is also evaluated in comparison with a functionally equivalent multiple-valued series-parallel MOS pass transistor network. The results show that highly compact multiple-valued VLSI systems can be achieved if the SPT-model can be realized by an actual quantum device.