The Heart Rate Variability (HRV) analysis has become vigorous these days. One reason for this is that the HRV analysis investigates the dynamics of the autonomic nervous system activities which control the HRV. The Integral Pulse Frequency Modulation (IPFM) model is a pulse generating mechanism model in the nervous system, that is one of the models which connects the HRV to the autonomic nervous system activities. The IPFM model is a single frequency component model; however, the real HRV has multiple frequency components. Moreover, there are refractory periods after generating action potentials are initiated. Nevertheless, the IPFM model does not consider refractory periods. In order to make sure of the accuracy and the effectiveness of the integral function (IF) method applied to the real data, we consider the absolute refractory periods and two frequency components. In this investigation, the simulated HRV was made with a single and double frequency component using the IPFM model with and without absolute refractory periods. The original generating function of the IPFM model was demodulated by using the instantaneous heart rate tachogram. The power of the instantaneous pulse rate per minute was analyzed by the direct FFT method, the IF FFT method without the absolute refractory periods, and the IF FFT method with the absolute refractory periods. It was concluded that the IF FFT method can demodulate the original generating function accurately.

A password authentication method PERM has been developed for application to e-mail forwarding. This method is suitable for communications in insecure network environments such as the Internet. In particular, it can be adapted to Internet appliances and Java applets which have limited performance. The PERM method does not require password resettings and enables high-speed authentication processing with a small-sized program. Moreover, it does not use facilities or mechanisms for generating random numbers and writing them into and reading them out of an IC card or similar storage medium on the user's side.

2-pole band-pass filters (BPFs) with tap-excitation are prepared by using high temperature superconductors (HTS). The possibility of realizing superconducting coplanar filters with attenuation poles is revealed.

In this paper a new general method for approximation of arbitrary multiband filter loss specifications, including all classical, maximally flat and equiripple approximations as special cases, is proposed. It is possible to specify different magnitude behavior (flat or equiripple of given degree) and different maximal losses in the different passbands and to optimize all transmission and attenuation zeroes positions or to have some of them fixed. The optimization procedures for adjustment of the filter response are based on modified Remez algorithm and are performed in s-domain what is regarded since recently as an advantage in the case of design of parallel allpass structures based IIR digital filters. A powerful algorithm and appropriate software are developed following the method and their efficiency is verified through design examples.

Solder joint reliability was studied for hybrid ICs, in which chip components such as FETs, resistors and capacitors were mounted with Sn-Sb solder on an insulated Al substrate and transfer-molded with epoxy resin. Suitable resin selection for molding was also studied. The structure was estimated to have a lifetime of more than ten thousand cycles in the thermal cycling test under the condition of -55/150, for FETs and passive elements. Equivalent plastic strains generated in the soldering layer for the non-molded structure were 4. 6% for the FETs and 3.5% for the passive elements. But, these strains were approximately 1/3 to 1/2 and 1/10 for the molded structure, respectively. This was the main reason for high reliability of the molded structure. Resins with a wide range of thermal expansion coefficient(8-26 ppm/)could be put to practical use, because of the higher reliability of the molded structure. However, a thermal expansion coefficient of about 15 ppm/ was prefered to decrease stress at the interface between the substrate and the molding resin.

A family of nonce-based authentication and key distribution protocols based on the trusted third-party model are proposed which are not only efficient on the view points of computation and communication, but also secure against on-line and off-line password guessing attacks. A new concept of implicit or indirect challenge-response authentication which can be used to combine the processes of identify authentication and data integrity assurance during key distribution and to make the entire protocol be more concise and efficient is introduced in this paper. In the proposed family of protocols, specific protocol can be chosen such that the secure session key to be distributed is selected by specific participant in the protocol. Detailed security analyses of every protocols are given.

After analyzing the limitations of the traditional description of CMOS circuits at the gate level, this paper introduces the notions of switching and signal variables for describing the switching states of MOS transistors and signals in CMOS circuits, respectively. Two connection operations for describing the interaction between MOS transistors and signals and a new description for MOS circuits at the switch level are presented. This new description can be used to express the functional relationship between inputs and the output at the switch level. It can also be used to describe the circuit structure composed of MOS switches. The new description can be effectively used to design both CMOS circuits and nMOS pass transistor circuits.

The construction of fault-tolerant processor arrays with interconnections of cube-connected cycles (CCCs) by using an advanced spare-connection scheme for k-out-of-n redundancies called "generalized additional bypass linking" is described. The connection scheme uses bypass links with wired OR connections to spare processing elements (PEs) without external switches, and can reconfigure complete arrays by tolerating faulty portions in these PEs and links. The spare connections are designed as a node-coloring problem of a CCC graph with a minimum distance of 3: the chromatic numbers corresponding to the number of spare PE connections were evaluated theoretically. The proposed scheme can be used for constructing various k-out-of-n configurations capable of quick broadcasting by using spare circuits, and is superior to conventional schemes in terms of extra PE connections and reconfiguration control. In particular, it allows construction of optimal r-fault-tolerant configurations that provide r spare PEs and r extra connections per PE for CCCs with 4x PEs (x: integer) in each cycle.

The multipass rendering method based on the global illumination model can generate the most photo-realistic images. However, since the multipass rendering method is very time consuming, it is impractical in the industrial world. This paper discusses a massively parallel processing approach to fast image synthesis by the multipass rendering method. Especially, we focus on the performance evaluation of the view-dependent object-space parallel processing on the (Mπ)2 which has been proposed in our previous paper. We also propose two kinds of distributed frame buffer system named cached frame buffer and multistage-interconnected frame buffer. These frame buffer systems can solve the access conflict problem on the frame buffer. The simulation results show that the (Mπ)2 has a scalable performance. For example, the (Mπ)2 with more than 4000 processing elements can achieve an efficiency of over 50%. We also show that both of the proposed distributed frame buffer systems can relieve the overhead due to frame buffer access in the (Mπ)2 in the case that a large number of high-performance processing elements are adopted in the system.

The cell structure of surface discharge ACPDPs with a long gap between the sustaining electrodes achieves high luminous efficiency. However, the long gap cell structure causes high firing voltage and thus makes driving more difficult than with the conventional gap cell structure. The rise in firing voltage in the long gap cell structure could not be explained by Paschen's scaling law. We derived a new governing equation for firing voltage, involving the influence of a non-uniform electric field, to investigate this deviation from Paschen's law. From the calculated results we found that changing the gap length corresponds to the change in the degree of distortion of the electric field between the sustaining electrodes.

This paper explores the potential of multiwave interconnectionsoptical interconnections that employ wavelength components as multiplexable information carriersfor constructing next-generation multiprocessor systems using MCM technology. A hypercube-based multiprocessor network called the multiwave hypercube (MWHC) is proposed, where multiwave interconnections provide highly-flexible dynamic communication channels among processing elements. A performance analysis shows that the use of multiwavelength optics makes possible the reduction of network complexity on an MCM substrate, while supporting low-latency message routing.

In this paper a novel narrow-band bandpass filter with an output pair of analytic signals is presented. Since it is based on the complex analog filter, both synthesis and response characteristics of this filter are different from conventional bandpass filters. In the design of this filter, the frequency shift method is employed and the conventional lowpass to bandpass frequency transformation is not required. The analysis and examples show that the output signal pair of the proposed filter possesses same filtering characteristics and a 90 degree phase shifting characteristics in the passband. Therefore, the proposed filter will be used for a single sideband (SSB) signal generator without quadrature generator.

Analog inverter is one of the most useful building blocks in analog circuits. This paper proposes an analog inverter consisting of a p-channel MOS (PMOS) and an n-channel MOS (NMOS) inverter and presents an application to all-pass filter realizations. The proposed circuit has a wide dynamic range by combining PMOS and NMOS inverters. When the proposed analog inverter is applied to an all-pass filter, the circuit configuration becomes simpler and occupies less chip area and power consumption.

We conducted research and development of Distributed Supercomputing Environment (DSE) based on distributed shared memory model to serve as a cluster computing environment to provide parallel processing facilities. Shared memory model and message passing model are well-known typical models of parallel processing. It is desired that hybrid programming environment will make the best use of the prominent features of both models. Consequently, we add a new message passing mechanism to present DSE, and create a prototype called Hybrid DSE as a hybrid model based cluster computing environment. In this paper, we describe the implementation of a message passing mechanism on DSE and performance evaluation of Hybrid DSE.

An ultra low voltage CMOS pass-gate logic using body-bias controlled SOI MOSFETs has been developed. The logic is composed of gate-body connected SOI pass-gates and a CMOS buffer with the body-bias controlled by the complementary double-rail input. The full-adder using the proposed logic improved the lowest operation voltage by 27%, compared with the SOI CPL (Complementary Pass-Gate Logic). For a 16 16 bit multiplier, the power-delay product achieved 70 pJ (including 50 pF I/O) at 0.5 V power supply, which was more than 1 order of magnitude improvement over the bulk CPL.

Regenerative Pass-transistor Logic (RPL), a modular dual-rail circuit technique for high speed logic design that gives reasonably low power consumption, was discussed in previous work [1]. RPL combines advantages of both the compact size of CPL and the full voltage-swing of DPL, and gives reasonably high performance concerning both speed and power consumption. In this paper, the application and design technique of RPL on larger logic circuits and systems are reported. Parallel adders and Booth multipliers with different sizes and structures are used as examples to evaluate the functionality of the RPL gates and full adder. In addition, there is less signal skew in RPL circuits than in conventional CPL circuits when an arrangement of single-rail to dual-rail signal conversion is performed. And, RPL is found to be useful in design of high speed and high density parallel adders and multipliers.

An insertion loss, branching deviation and polarization dependent loss (PDL) as to a 2 N optical splitter using silica-based planar lightwave circuits has been investigated. New key technologies such as (1) a novel wedge type Y-branch, (2) an offset waveguide at the junction between the curved input waveguide and the Y-branch, and (3) low birefringence waveguides due to the appropriate dopant concentration of a cladding, have been devised and incorporated into the splitter. As a result, 2 N optical splitters with low average insertion loss ( 13.2 dB), low branching deviation ( 0.4 dB) and low PDL ( 0.2 dB) have been successfully developed.

Laser module fabricated with silicon platform technology is very attractive for low-cost modules. The technology enables passive optical alignment of an LD to an optical fiber. Our marker design for passive alignment allows positioning accuracy within 1 µm of LD. However, coupling efficiency is a key issue because that by conventional butt coupling scheme is low with about 10 dB coupling loss. We investigated optical coupling characteristics in various types of coupling scheme: conventional flat end fibers, cone fibers, integrated GRIN rod lenses on the platform and the coupling with new-type LDs integrated with spot size transformer. Improvement of coupling efficiency with 3 dB and 7.5 dB compared to flat-end fiber is achieved by using the cone fiber and the GRIN rod lens, respectively, although 1-dB coupling tolerances for alignment deteriorated with these schemes. We obtained high efficient coupling with 3.5 dB coupling loss and wide alignment tolerance of 2.3 µm simultaneously with a new-type LD integrated with spot size transformer owing to its expanded spot size characteristics.

At present, the widespread use of optoelectronic components is restricted by their high cost. Up to 90% of the cost of a semiconductor laser is in the packaging, with the fibre-chip alignment the major part. In this paper, an approach to low cost packaging is described, which uses an integrated mode size transformer to match the laser output to the fibre mode. This improves the alignment tolerance of the laser-fibre coupling by more than a factor of three, allowing simple passive alignment approaches to be used. It requires only minor modification to the processing of a standard buried heterostructure laser, and allows the coupling efficiency to be optimised without compromising the performance of the laser. The design of a silicon submount for passive laser-fibre alignment is described and coupling losses as low as 1.2 dB to standard cleaved single mode fibre are reported. The technology that has been developed is generic and its successful application to other optoelectronic devices such as fibre grating lasers, semiconductor optical amplifiers and laser arrays is described.

This paper describes packaging techniques based on a novel passive alignment technique as key techniques for module assembly. A laser diode (LD) is passively positioned by detecting a pair of alignment marks located on the LD and Si substrate. A single-mode fiber is self aligned on a Si V groove. A simple receptacle structure for the module output port is also newly designed. This structure is more suitable for the automatic assembly line as well as the module mounting process on circuit board. In this paper, an advanced module applications such as a hybrid integrated wave guide module and a surface mountable (SMT) LD module is introduced.