This paper describes a flexible point-to-multipoint access protocol for the fiber-optic passive double star (PDS) system. To provide various types of services, and permit flexibility in changing transport capacity, a time division multiple access (TDMA) scheme for the PDS system is considered. Dynamic time slot multiplexing based on TDMA is proposed to provide required time slots efficiently according to service changes. The effectiveness of dynamic time slot multiplexing is calculated and compared to fixed time slot multiplexing for telephony services. A TCM/TDMA frame structure and an access protocol enabling dynamic time slot multiplexing are proposed. ONU bandwidth is dynamically assigned by using a set of pointers. The ONU access protocol causes no interruption to operating ONUs on the same PDS system during the configuration or reconfiguration of an ONU. The access time is analyzed to estimate the performance of the access protocol. The probability density of access time is calculated for the number of ONUs connected. The calculation results indicate that a PDS system can accommodate up to around 60 ONUs within the maximum access time specified by ITU-T. The experimental results also agree fairly well with the theoretical values.

In this paper we present a design method for all-pass networks with consideration of the stability. It is based on the eigen filter method and Remez exchange algorithm is used to obtain the equiripple phase error solution. In the iteration of the proposed algorithm, the eigen values besides maximum eigen value are used in order to obtain a stable all-pass networks.

A noise cancelling sonar-ranging system based on the adaptive filtering technique, which can automatically adapt itself to the changes in environmental noise-field and improve the passive sonar-ranging/goniometric precision, was introduced by this paper. In the meantime, the software and hardware design principle of the system using high speed VLSI (Very Large Scale Integrated) DSP (Digital Signal Processing) chips, and the practical test results were also presented. In comparison with the traditional ranging system, the system not only enhanced obviously the ranging precision but also possessed some more characteristics such as simple structure, rapid operation, large data-storage volume, easy programming, high reliability and so on.

Password checking schemes are human identification methods commonly adopted in many information systems. One of their disadvantages is that an attacker who correctly observed an input password can impersonate the corresponding user freely. To overcome it there have been proposed interactive human identification schemes. Namely, a human prover who has a secret key is asked a question by a machine verifier, who then checks if an answer from the prover matches the question with respect to the key. This letter examines such a scheme that requires relatively less efforts to human provers. By computer experiments this letter evaluates its resistance against a type of attack; after observing several pairs of questions and correct answers how successfully can an attacker answer the next question?

This paper surveys low-power circuit techniques for CMOS ULSIs. For many years a power supply voltage of 5 V was employed. During this period power dissipation of CMOS ICs as a whole increased four-fold every three years. It is predicted that by the year 2000 the power dissipation of high-end ICs will exceed the practical limits of ceramic packages, even if the supply voltage can be feasibly reduced. CMOS ULSIs now face a power dissipation crisis. A new philosophy of circuit design is required. The power dissipation can be minimized by reducing: 1) supply voltage, 2) load capacitance, or 3) switching activity. Reducing the supply voltage brings a quadratic improvement in power dissipation. This simple solution, however, comes at a cost in processing speed. We investigate the proposed methods of compensating for the increased delay at low voltage. Reducing the load capacitance is the principal area of interest because it contributes to the improvement of both power dissipation and circuit speed. Pass-transistor logic is attracting attention as it requires fewer transistors and exhibits less stray capacitance than conventional CMOS static cicuits. Variations in its circuit topology as well as a logic synthesis method are presented and studied. A great deal of research effort has been directed towards studying every portion of LSI circuits. The research achievements are categorized in this paper by parameters associated with the source of CMOS power dissipation and power use in a chip.

The validity of numerical design scheme of CP-PASS (Circularly Polarized Printed Array antenna composed of Strips and Slots) is considered. The strip element of CP-PASS is composed of a strip dipole and a window which increases the frequency bandwidth of the strip element. With the window, however, analysis of the antenna becomes difficult if a simple analytical model is used. The previous design procedure requierd an experimental procedure. By using modern computers, the FDTD (finite-difference time-domain) method becomes powerful tool for the analysis of 3D-structured antennas. In this paper, numerical results of the FDTD analysis for CP-PASS is compared with results from experiments. The characteristics of the unit-radiator of CP-PASS are demonstrated numerically. This paper shows that CP-PASS can be designed numerically and a new path has opened in the study of CP-PASS.

This paper describes a newly developed 22 liquid crystal optical switch for 1.3µm single-mode fiber use. This switch state can be freely set at either the cross or the bar state. The measured performance of two prototype 22 liquid crystal optical switches is given. Tests confirm that the 3 values are a maximum insertion loss of 1.5dB, a crosstalk attenuation of more than 26.1dB, and a return loss of more than 28.9dB. Requirements for optical switches for fault isolation are theoretically clarified from a LAN system view point.

In this paper, we first discuss on a framework for a 3D image display system which is the combination of passive sensing and active display technologies. The passive sensing enables to capture real scenes under natural condition. The active display enables to present arbitrary views with proper motion parallax following the observer's motion. The requirements of passive sensing technology for 3D image displays are discussed in comparison with those for robot vision. Then, a new stereo algorithm, called SEA (Stereo by Eye Array), which satisfies the requirements is described in detail. The SEA uses nine images captured by a 33 camera array. It has the following features for depth estimation: 1) Pixel-based correspondence search enables to obtain a dense and high-spatial-resolution depth map. 2) Correspondence ambiguity for linear edges with the orientation parallel to a particular baseline is eliminated by using multiple baselines with different orientations. 3) Occlusion can be easily detected and an occlusion-free depth map with sharp object boundaries is generated. The feasibility of the SEA is demonstrated by experiments by using real image data.

We propose a new structure of antenna system to enhance the horizontal plane gain and control the antenna pattern, using passive loading. Our proposed structure can be applied to various kinds of antennas on a handset. We discuss the case of a λ/4 monopole antenna on a handset in this paper. In a new structure of λ/4 monopole antenna system, we show that, 1) the increase of the average gain about 5dB in the horizontal plane can be realized by an optimum load, 2) the antenna pattern can be controlled by changing the value of the passive load so as to have some desirable shapes, and 3) the antenna size can be made smaller by about 6% than the one with no loading because the optimum loading makes the resonant frequency lower. These results were confirmed by the calculations using the method of moments for the EFIE and the measurements.

New detection method of passivation defect was studied. The method was the Cu decoration method without bias (bias-free Cu decoration). As the result of comparison with conventional method, it was found that a bias-free Cu decoration method was effective, sensitive and simple. In this method, the difference of humidity resistance induced by poor passivation coverage could be evaluated.

This report describes 4-2 compressors composed of Complementary Pass-Transistor Logic (CPL). We will show that circuit designs of the 4-2 compressors can be optimized for high speed and small size using only exclusive-OR's and multiplexers. According to a circuit simulation with 0.8µm CMOS device parameters, the maximum propagation delay and the average power consumption per unit adder are 1.32 ns and 11.6 pJ, respectively.

The timing jitter reductions with differently shaped optical bandpass filters are discussed and the transmission distance achievable against the timing jitter is evaluated using optical bandpass filters in several tens of Gb/s soliton transmission. Experimental confirmation of timing jitter reduction with optical bandpass filters is demonstrated in 10Gb/s optical soliton recirculating loop experiments by measuring the timing jitter and the bit error rates.

This paper discusses the design of an ITS to realize a load-oriented tutoring to enhance the student's explanation understanding. In the explanation understanding, it is to be hoped that a student not only memorizes the new information from an explanation, but also relates the acquired information with his/her own knowledge to recognize what it means. This relating process can be viewed as the one in which the student structures his/her knowledge with the explanation. In our ITS, we regard the knowledge-structuring activities as the explanation understanding. In this paper, we propose an explanation, called a load-oriented explanation, with the intention of applying a load to the student's knowledge-structuring activities purposefully. If the proper load is applied, the explanation can induce the student to think by himself/herself. Therefore he/she will have a chance of gaining the deeper understanding. The important point toward the load-oriented explanation generation is to control the load heaviness appropriately, which a student will bear in understanding the explanation. This requires to estimate how an explanation promotes the understanding activities and how much the load is applied to the activities. In order to provide ITS with the estimation, we have built an Explanation Effect Model, EEM for short. Our ITS consists of an explanation planner and a self-explanation environment. The planner generates the load-oriented explanation based on EEM. The system also makes a student explain the explanation understanding process to himself/herself. Such self-explanation is useful to let the student be conscious of the necessity of structuring his/her knowledge with the explanation. The self-explanation environment supports the student's self-explanation. Furthermore, if the student reaches an impasse in self-explaining, the planner can generate the supporting explanation for the impasse.

We propose a third-order low-pass notch filter realized by a single operational amplifier and a minimum number of equal-valued capacitors. As a design example we realize a Chebyshev filter with a ripple of 0.5 dB and it is shown that the experiment result is very good.

Fiber-optic passive double star (PDS) network is described as an access network for microcellular radio communication systems. The intrinsic characteristics of the PDS network, reduction in the optical fiber count and flexible access capability, are examined. A unit cell structure is introduced which enables the PDS network to be effectively incorporated into the access portion of microcellular radio communication systems. The reduced total fiber length in the unit cell structure based on the PDS network is discussed in comparison with the conventional architecture. Calculations show that there is an optimum splitting ratio that minimizes the total fiber length. When the microcell radius and service area radius are 100m and 10km, respectively, the total fiber length of the PDS network is reduced to only about 9% of that of the conventional single star (SS) network for a splitting ratio of 34. Resource sharing and handover between microcells in a unit cell are performed by using the dynamic channel allocation function of the PDS system. Substantial performance improvement for loaded traffic can be obtained by resource sharing. When the splitting ratio is 32, the available traffic of a base station (BS) increases from 0.9 [erl/BS] to 3.4 [erl/BS] by adopting dynamic channel allocation for the lost call probability of 0.01.

Novel three-dimensional structures for passive elements--inductors, capacitors, transmission lines, and airbridges--have been developed to reduce the area they consume in GaAs MMICs. These structures can be formed with a simple technology by electroplating along the sidewalls of a photoresist. Adopting the new structures, most passive elements in MMICs have been shrunk to less than 1/4 the size of conventional ones.

This paper describes bandpass filters using linear tapered transmission line resonators (LTLR's). Bandpass filters are designed on the basis of the approximate description of LTLR's with cascaded multi-sections of uniform transmission lines whose widths are slightly different. By this design method, the fundamental characteristics of LTLR's and filter design parameters can be easily obtained using a general-purpose microwave circuit simulator. Trial LTLR bandpass filters showed excellent performance such as low insertion losses and the ability to control spurious responses, then their measured responses indicated close correspondence with the design results.

A wideband high power amplifier design using a novel band-pass filter with FET's parasitic reactances has been developed. The feature of this design is in that it can provide wide bandwidth and high gain of high power amplifiers. Furthermore, the lower cutoff frequency and bandwidth can be varied independently. With the use of this design, a Ku-band two-stage high power amplifier having a bandwidth of 18% has achieved a linear gain of 9.751.75 dB, a saturated output power of greater than 37 dBm, and a power-added efficiency of greater than 10.4%.

This letter presents a technique to cancel the parasitic effects of operational amplifier (op amp) in active filter design. To minimize the effects, an op amp model considering the parasitics (i.e. both parasitic poles and zeros) is utilized. It is shown that undesirable factors in the transfer function due to the parasitics can be canceled well by predistorting the passive element values of the circuit. As an example, an active-R highpass filter is evaluated both theoretically and numerically. In this way, the proposed technique can be effectively incorporated into the design of active filters.

With increases in frequency and density of RISC microprocessors due to rapid advances in architecture, circuit and fine device technologies, power consumption becomes a bigger concern. Supply voltage should be reduced from 5 V to 3.3 V. In this paper, several novel circuits using 0.5µm BiCMOS technology are proposed. These can be applied to a superscalar RISC microprocessor at 3.3 V power supply or below. High speed and low power consumption characteristics are achieved in a floating-point data path, an integer data path and a TLB by using the proposed circuits. The three concepts behind the proposed high speed circuit techniques at low voltage are summarized as follows. There are a number of heavy load paths in a microprocessor, and these become critical paths under low voltage conditions. To achieve high speed characteristics under heavy load conditions without increasing circuit area, low voltage swing operation of a circuit is effective. By exploiting the high conductance of a bipolar transistor, instead of using an MOS transistor, low swing operation can be got. This first concept is applied to a single-ended common-base sense circuit with low swing data lines in the register file of a floating and an integer data path. Both multi-series transistor connections and voltage drops by Vth of MOS transistors and Vbe of bipolar transistors also degrade the speed performance of a circuit. Then the second concept employed is a wired-OR logic circuit technique using bipolar transistors which is applied to a comparator in the TLB instead of multi-series transistor connections of CMOS circuits. The third concept to overcome the voltage drops by Vth and Vbe is addition of a pull up PMOS to both the path logic adder and the BiNMOS logic gate to ensure the circuits have full swing operation.