We investigate a sparsely encoded Hopfield model with unit replacement by using a statistical mechanical method called self-consistent signal-to-noise analysis. We theoretically obtain a relation between the storage capacity and the number of replacement units for each sparseness a. Moreover, we compare the unit replacement model with the forgetting model in terms of the network storage capacity. The results show that the unit replacement model has a finite value of the optimal sparseness on an open interval 0 (1/2 coding) < a < 1 (the limit of sparseness) to maximize the storage capacity for a large number of replacement units, although the forgetting model does not.

Current collapse of AlGaN/GaN heterostructure field-effect transistors (HFETs) formed on qualified epitaxial layers on Si substrates was successfully suppressed using graded field-plate (FP) structures. To improve the reproducibility of the FP structure manufacturing process, a simple process for linearly graded SiO2 profile formation was developed. An HFET with a graded FP structure exhibited a significant decrease in an on-resistance increase ratio of 1.16 even after application of a drain bias of 600 V.

Template matching for image sequences captured with a moving camera is very important for several applications such as Robot Vision, SLAM, ITS, and video surveillance systems. However, it is difficult to realize accurate template matching using only visual feature information such as HSV histograms, edge histograms, HOG histograms, and SIFT features, because it is affected by several phenomena such as illumination change, viewpoint change, size change, and noise. In order to realize robust tracking, structure information such as the relative position of each part of the object should be considered. In this paper, we propose a method that considers both visual feature information and structure information. Experiments show that the proposed method realizes robust tracking and determine the relationships between object parts in the scenes and those in the template.

In this paper, a fast and automated method of counting pedestrians in crowded areas is proposed along with three contributions. We firstly propose Local Empirical Templates (LET), which are able to outline the foregrounds, typically made by single pedestrians in a scene. LET are extracted by clustering foregrounds of single pedestrians with similar features in silhouettes. This process is done automatically for unknown scenes. Secondly, comparing the size of group foreground made by a group of pedestrians to that of appropriate LET captured in the same image patch with the group foreground produces the density ratio. Because of the local scale normalization between sizes, the density ratio appears to have a bound closely related to the number of pedestrians who induce the group foreground. Finally, to extract the bounds of density ratios for groups of different number of pedestrians, we propose a 3D human models based simulation in which camera viewpoints and pedestrians' proximity are easily manipulated. We collect hundreds of typical occluded-people patterns with distinct degrees of human proximity and under a variety of camera viewpoints. Distributions of density ratios with respect to the number of pedestrians are built based on the computed density ratios of these patterns for extracting density ratio bounds. The simulation is performed in the offline learning phase to extract the bounds from the distributions, which are used to count pedestrians in online settings. We reveal that the bounds seem to be invariant to camera viewpoints and humans' proximity. The performance of our proposed method is evaluated with our collected videos and PETS 2009's datasets. For our collected videos with the resolution of 320 × 240, our method runs in real-time with good accuracy and frame rate of around 30 fps, and consumes a small amount of computing resources. For PETS 2009's datasets, our proposed method achieves competitive results with other methods tested on the same datasets [1],[2].

We present the theory and experiment of metal-cavity nanolasers and nanoLEDs flip-chip bonded to silicon under electrical injection at room temperature. We first review the recent progress on micro- and nanolasers. We then present the design rule and our theoretical model. We show the experimental results of our metal-cavity surface-emitting microlasers and compare with our theoretical results showing an excellent agreement. We found the important contributions of the nonradiative recombination currents including Auger recombination, surface recombination, and leakage currents. Finally, experimental demonstration of electrical injection nanoLEDs toward subwavelength nanoscale lasers is reported.

A novel fabrication approach for electrochemical sensing of nicotinamide adenine dinucleotide (NADH) using neutral red (NR) functinalized carbon nanotube/plasma-polymerized film composite electrode is reported. The configuration of sensing electrode was NR-functionalized CNTs sandwiched between two acetonitrile PPFs on sputtered gold thin film. The NR as an electron transfer mediator shuttles the electron from the CNT to gold electrode. Due to the synergistic effect between NR and CNT, the resulting electrode showed the lower detection potential and the larger sensitivity (current) than that of NR or CNT alone. The sensor revealed a sensitivity of 29 µA mM-1 cm-2 at +0.15 V vs. Ag/AgCl, linear dynamic range of 0.08–4.2 mM, a detection limit of 18 µM at S/N=3, and a response time of 7 s.

The existing routing protocols for the interplanetary backbone network did not consider future link connection and link congestion. A novel routing protocol named CAMARP for the interplanetary backbone network is proposed in this letter. We use wait delay to consider future link connection and make the best next hop selection. A load balancing mechanism is used to avoid congestion. The proposed method leads to a better and more efficient distribution of traffic, and also leads to lower packet drop rates and higher throughput. CAMARP demonstrates good performance in the experiment.

Although the effect of electromagnetic interference on an implanted cardiac pacemaker due to a nearby mobile phone has been investigated, there have been few studies on the enhancement of the specific absorption rate (SAR) around an implanted cardiac pacemaker due to a nearby mobile phone. In this study, the SAR distribution around a pacemaker model embedded in a parallelepiped torso phantom when a mobile phone was nearby was numerically calculated and experimentally measured. The results of both investigations showed a characteristic SAR distribution. The system presented can be used to estimate the effects of electromagnetic interference on implanted electric circuits and thus could lead to the development of guidelines for the safe use of mobile radio terminals near people with medical implants.

The Liquid-crystal display (LCD) overdrive technique has been utilized to reduce motion blur on a display via a reduction in the response time. However, to measure the variation of the pixel amplitudes, it is necessary to store the previous frame using a large frame memory. To downscale the frame memory, block truncation coding (BTC) is commonly employed due to the simplicity of its implementation, even if some visual artifacts may occur for image blocks with high frequency components. In this paper, we present a multimode-multilevel BTC (MBTC) technique that improves performance while maintaining simplicity. To improve the visual quality, we uniquely determine the quantization level and coding mode of each block according to the distribution of the luminance and chrominance amplitudes. For a compression ratio of 6:1, the proposed method demonstrates higher coding efficiency and overdrive performance by up to 3.81 dB in the PSNR compared to other methods.

The performances of the conventional planar type 1T DRAM and the Vertical type 1T DRAM are compared based on structure difference using a fully-consistent device simulator. We discuss the structural advantage of the Vertical type 1T-DRAM in comparison with the conventional planar type 1T-DRAM, and evaluate their performance in each operating mode such as write, erase, read, and hold; and discuss its cell performances such as Cell Current Margin and data retention. These results provide a useful guideline designing the high performance Vertical type 1T-DRAM cell.

This paper presents a new common-mode stabilization method for a CMOS differential cascode Class-E power amplifier with LC-tank based driver stage. The stabilization method is based on the identification of the poles and zeros of the closed-loop transfer function at a critical node. By adding a series resistor at the common-gate node of the cascode transistor, the right-half-plane poles are moved to the left half plane, improving the common-mode stability. The simulation results show that the new method is an effective way to stabilize the PA.

A Drude-critical points (D-CP) model for considering metal dispersion is newly incorporated into the frequency-dependent FDTD method using the simple trapezoidal recursive convolution (TRC) technique. Numerical accuracy is investigated through the analysis of pulse propagation in a metal (aluminum) cladding waveguide. The TRC technique with a single convolution integral is found to provide higher accuracy, when compared with the recursive convolution counterpart. The methodology is also extended to the unconditionally stable FDTD based on the locally one-dimensional scheme for efficient frequency-dependent calculations.

In this paper, we propose a synthesis method for asynchronous circuits with bundled-data implementation. The proposed method iteratively applies behavioral synthesis and floorplanning to obtain a near optimum circuit in the term of latency under given design constraints. To improve latency, behavioral synthesis and floorplanning are carried out so that the delay of the control circuit is minimized and the addition of delay elements to satisfy timing constraints is minimized. We evaluate the effectiveness of the proposed method in terms of latency, area, and the number of timing violations while synthesizing several benchmarks. Experimental results show that the proposed method synthesizes faster circuits compared to the circuit synthesized without the proposed method. Also, the proposed method is effective to reduce the number of timing violations.

The cause-and-effect relation between plasmon-resonance absorption and surface wave in a sinusoidal metal grating is investigated. By introducing an equivalent impedance model, similar to an equivalent circuit on an electric circuit, which is an impedance boundary value problem on the fictitious surface over the grating, we estimate the surface wave from the eigen field of the model by using the resonance property of the scattered field. Through numerical examples, we illustrate that the absorption in the grating occurs in the condition of exciting the surface wave along the model, and the real part of the surface impedance is negative on about half part of the fictitious surface in the condition.

Network-on-Chips (NoCs) have been proposed as a solution for addressing the global communication challenges in System-on-Chip (SoC) architectures that are implemented in nanoscale technologies. For the use of NoCs to be feasible in today's industrial designs, a custom-tailored, power- efficient NoC topology that satisfies the application characteristics is required. In this work, we present a design methodology that automates the synthesis of such application-specific NoC topologies. We present a method which integrates partitioning into floorplanning phase to explore optimal clustering of cores during floorplanning with minimized link and switch power consumption. Based on the size of applications, we also present an Integer Linear Programming and a heuristic method to place switches and network interfaces on the floorplan. Then, a power and timing aware path allocation algorithm is carried out to determine the connectivity across different switches. We perform experiments on several SoC benchmarks and present a comparison with the latest work. For small applications, the NoC topologies synthesized by our method show large improvements in power consumption (27.54%), hop-count (4%) and running time (66%) on average. And for large applications, the synthesized topologies result in large power (31.77%), hop-count (29%) and running time (94.18%) on average.

Let G be a connected graph in which we designate a vertex or a block (a biconnected component) as the center of G. For each cut-vertex v, let Gv be the connected subgraph induced from G by v and the vertices that will be separated from the center by removal of v, where v is designated as the root of Gv. We consider the set R of all such rooted subgraphs in G, and assign an integer, called an index, to each of the subgraphs so that two rooted subgraphs in R receive the same indices if and only if they are isomorphic under the constraint that their roots correspond each other. In this paper, assuming a procedure for computing a signature of each graph in a class of biconnected graphs, we present a framework for computing indices to all rooted subgraphs of a graph G with a center which is composed of biconnected components from . With this framework, we can find indices to all rooted subgraphs of a outerplanar graph with a center in linear time and space.

The wear leveling is a critical factor which significantly impacts the lifetime and the performance of flash storage systems. To extend lifespan and reduce memory requirements, this paper proposed an efficient wear leveling without substantially increasing overhead and without modifying Flash Translation Layer (FTL) for huge-capacity flash storage systems, which is based on selective replacement. Experimental results show that our design levels the wear of different physical blocks with limited system overhead compared with previous algorithms.

In this paper, we propose a placement and routing method for a new memory-based programmable logic device (MPLD) and confirm its capability by placing and routing benchmark circuits. An MPLD consists of multiple-output look-up tables (MLUTs) that can be used as logic and/or routing elements, whereas field programmable gate arrays (FPGAs) consist of LUTs (logic elements) and switch blocks (routing elements). MPLDs contain logic circuits more efficiently than FPGAs because of their flexibility and area efficiency. However, directly applying the existing placement and routing algorithms of FPGAs to MPLDs overcrowds the placed logic cells and causes a shortage of routing domains between logic cells. Our simulated annealing-based method considers the detailed wire congestion and nearness between logic cells based on the cost function and reserves the area for routing. In the experiments, our method reduced wire congestion and successfully placed and routed 27 out of 31 circuits, 13 of which could not be placed or routed using the versatile place and route tool (VPR), a well-known method for FPGAs.

This paper addresses stereo matching under scenarios of smooth region and obviously slant plane. We explore the flexible handling of color disparity, spatial relation and the reliability of matching pixels in support windows. Building upon these key ingredients, a robust stereo matching algorithm using local plane fitting by Confidence-based Support Window (CSW) is presented. For each CSW, only these pixels with high confidence are employed to estimate optimal disparity plane. Considering that RANSAC has shown to be robust in suppressing the disturbance resulting from outliers, we employ it to solve local plane fitting problem. Compared with the state of the art local methods in the computer vision community, our approach achieves the better performance and time efficiency on the Middlebury benchmark.

We investigated optical transmission characteristics of aluminum thin films with periodic hole arrays in sub-wavelength. We divided white light into several color spectra using a color filter based on the surface plasmon resonance (SPR) utilizing aluminum showing high plasma frequency. By optimizing a hole-array period, hole shape, polarization and index difference of two surface, transmittance of 30% and full-width at half-maximum of around 100 nm were achieved.