We developed piezoresistors with an intrinsic compensation of the offset temperature characteristics. High energy ion implantation was applied to fabricate this type of piezoresistor. The dopant profile of the buried piezoresistor resembles to that of the junction gate field effect transistor (JFET). The buried layer corresponds to a channel of JFET, and the substrate bias corresponds to the gate voltage. Owing to the independent temperature varying parameters, i.e., width of the depletion layer and carrier mobility in the channel, the drain current of the JFET has a temperature independent point at an appropriate gate source voltage. The effect was used in the new type of buried piezoresistor which has a driving point of zero temperature coefficient of resistance at an appropriate gate source voltage.

Memory type polymer dispersed liquid crystal (PDLC) can be applied to a thermal addressing display device cell. Making use of its easy fabrication of large area display using flexible film substrate, the PDLC film can be used as reusable paper for direct-view mode display. In this study, memory type PDLC cells are prepared with an aluminum reflector deposited onto one side of the substrate and the reflection property in the PDLC cell with the reflector is clarified and compared to that without the reflector in the off-, on- and memory-states. The increase of contrast ratio and the decrease of driving voltage can be concurrently realized by decreasing the cell thickness by attaching the reflector. In addition, the reflected light in the off-state is bright and colorless due to the reflector, as compared with the weak, bluish reflected light in the cell without the reflector. Reflected light in the on-state and the memory-state are tinged with blue.

Most current management systems employ graphic-user-interface displays to visualize the networks being managed. Some networks are so large that it is difficult to display all network elements in a single window alone, and therefore, the hierarchical multi-window style presentation is commonly used. This form of presentation has disadvantages, however, including the fact that window manipulations are complex. Our approach (bifocal network visualization) is able to display both the context and any detail of a network within a single window, and overcomes the disadvantages of hierarchical multi-window presentation. We implemented this bifocal network visualization on a workstation using a frame buffer memory called DUALQUEST that is able to generate images in real-time and is simple to operate. This paper describes bifocal network visualization and its implementation. Furthermore, we present an experiment to compare our interface with conventional hierarchical multi-window presentation.

This paper presents a heuristic floorplanning method that improves the method proposed by Vijayan and Tsay. It is based on tentative insertion of constraints, that intentionally produces redundant constraints to make it possible to search in a wide range of solution space. The proposed method can reduce the total area of blocks with the removal and insertion of constraints on the critical path in both horizontal and vertical constraint graphs. Experimental results for MCNC benchmarks showed that the quality of solutions of the proposed method is better than [7],[8] by about 15% on average, and even for the large number of blocks, the proposed method keeps the high quality of solutions.

Electromagnetic plane wave scattering by a loaded trough on a ground plane has been analyzed by Kobayashi and Nomura's method. The field in each region is expressed first in terms of appropriate eigen functions, whose excitation coefficients are determined by the continuity condition across the aperture of the trough. Simple far field expression which is suitable for numerical calculation for small aperture cases has been derived. Scattering far field patterns and radar cross section are calculated and compared with those obtained by other methods. Good agreements have been observed for all incident angles.

This paper describes a new clustering approach for VLSI placement, which is based on a fractal dimension analysis for the topological structure of modules in a logic diagram. A distinctive feature of this approach is that a measure of the 'fractal dimension' has been introduced into a logic diagram in such a way that the clustering of modules is iterated while the fractal dimension among clustered modules is retained in a prescribed range. A part of experimental results is also shown, which demonstrates that our clustering approach raises the placement performance much higher than the conventional clustering methods.

We have developed a Virtual Playground," which allows various activities such as virtual playground and virtual visiting areas for hospitalized children who can not usually go outside. A Virtual Playground system is composed of TV monitors, joysticks, cameras, video transmission devices, and a graphics workstation. In a Virtual Playground environment, children can experience what is impossible or difficult during their stay in a hospital. We have completed a couple of experiments already and discussed its effects.* In our recent work, we also introduced a simple version of the Cave display to the Virtual Playground system.

Technology mapping algorithms for LUT (Look Up Table) based FPGAs have been proposed to transfer a Boolean network into logic-blocks. However, since those algorithms take no layout information into account, they do not always lead to excellent results. In this paper, a simultaneous technology mapping, placement and global routing algorithm for FPGAs, Maple, is presented. Maple is an extended version of a simultaneous placement and global routing algorithm for FPGAs, which is based on recursive partition of layout regions and block sets. Maple inherits its basic process and executes the technology mapping simultaneously in each recursive process. Therefore, the mapping can be done with the placement and global routing information. Experimental results for some benchmark circuits demonstrate its efficiency and effectiveness.

In this letter we propose an interpolation technique for low-quality fingerprint images for highly reliable feature extraction. To improve the feature extraction rate, we extract fingerprint features by referring to both the interpolated image obtained by using a directional Laplacian filter and the high-contrast image obtained by using histogram equalization. Experimental results show the applicability of our method.

This paper describes a new method for pose estimation of human face moving abruptly in real world. The virtue of this method is to use a very simple calculation, disparity, among multiple model images, and not to use any facial features such as facial organs. In fact, since the disparity between input image and a model image increases monotonously in accordance with the change of facial pose, view direction, we can estimate pose of face in input image by calculating disparity among various model images of face. To overcome a weakness coming from the change of facial patterns due to facial individuality or expression, the first model image of face is detected by employing a qualitative feature model of frontal face. It contains statistical information about brightness, which are observed from a lot of facial images, and is used in model-based approach. These features are examined in everywhere of input image to calculate faceness" of the region, and a region which indicates the highest faceness" is taken as the initial model image of face. To obtain new model images for another pose of the face, some temporary model images are synthesized through texture mapping technique using a previous model image and a 3-D graphic model of face. When the pose is changed, the most appropriate region for a new model image is searched by calculating disparity using temporary model images. In this serial processes, the obtained model images are used not only as templates for tracking face in following image sequence, but also texture images for synthesizing new temporary model images. The acquired model images are accumulated in memory space and its permissible extent for rotation or scale change is evaluated. In the later of the paper, we show some experimental results about the robustness of the qualitative facial model used to detect frontal face and the pose estimation algorithm tested on a long sequence of real images including moving human face.

The methodology for latchup-free design in bipolar and PMOS merged gates, so-called BiPMOS gates, is considered. Although BiPMOS gates can provide higher switching characteristics than conventional, individually drawn, BiCMOS gates even when the supply voltage is reduced, the general methodology to prevent latchup has been lacking. This paper presents an approximate, but sufficiently correct, mathematical technique to solve the Laplace equation, which gives the distribution of latchup trigger current for the given BiPMOS drawings. It is shown that the resistances of the collector plug and the spreading resistance under the base-collector junction greatly influence latchup, and that the well-emitter overlapping space becomes a problem in the case of a single collector. The distribution of latchup triggering current for the double-emitter double collector NPN transistor indicates the optimum position of the source diffusion area.

A radial line slot antenna (RLSA) is a slotted waveguide planar array for the direct broadcast from satellite (DBS) subscriber antennas. A single-layered RLSA (SL-RLSA) is excited by a radially outward traveling wave. The antenna efficiency of more than 85% has already been realized. These antennas are designed on the assumption of perfectly rotationally symmetrical traveling wave excitation; the slot design is based upon the analysis of a slot pair on the rectangular waveguide model with periodic boundary walls. However, the slots perturb the inner field and the actual antenna operation is not perfectly symmetrical. This causes the efficiency reduction especially for very small size antenna. This paper presents a fundamental analysis of the inner field of the radial waveguide. It is impossible to analyze all the slot pairs in the aperture as it is and only the slots in the inner few turns are considered since these provide dominant perturbation. The calculated results are verified by the experiments and reasonable agreement is demonstrated. Some design policies are suggested for enhancing the rotational symmetry.

Plating is applied to protect contact surfaces of contact devices such as switch, relay and connector from contaminations of oxidization and sulfuration etc. Furthermore it is known that the contact resistance can be reduced when there exist plated layers on the contact surfaces which have enough thickness and low resistivity compared with substratum materials. In this paper, contact resistance between plated conductors are calculated using three dimensional finite element method. Similariry, current density distribution in a contact spot with various resistivity of plated layers are shown and relative conductance depends on the contact area fraction with thickness of plated layers are presented.

We can understand and recover a scene even from a picture or a line drawing. A number of methods have been developed for solving this problem. They have scarcely aimed to deal with scenes of multiple objects although they have ability to recognize three-dimensional shapes of every object. In this paper, challenging to solve this problem, we describe a method for deciding configurations of multiple objects. This method employs the assumption of coplanarity and the constraint of occlusion. The assumption of coplanarity generates the candidates of configurations of multiple objects and the constraint of occlusion prunes impossible configurations. By combining this method with a method of shape recovery for individual objects, we have implemented a system acquirig a three-dimensional information of scene including multiple objects from a monocular image.

This paper describes small AlGaAs/GaAs HBT's for low-power and high-speed integrated circuits. The device fabrication is based on a new bridged base electrode technology that permits emitter width to be defined down to 1 µm. The new technology features oxygen-ion implantation for emitter-base junction isolation and zinc diffusion for extrinsic base formation. The oxygen-ion implanted emitter-base junction edge has been shown to provide a periphery recombination current much lower than that for the previous proton implanted edgs, the result being a much higher current gain particularly in small devices. The zinc diffusion offers high device yield and good uniformity in device characteristics even for a very thin (0.04 µm) base structure. An HBT with emitter dimensions of 12.4 µm2 yields an fT of 103 GHz and an fmax of 62 GHz, demonstrating that the new technology has a significant advantage in reducing the parasitic elements of small devices. Fabricated one-by-eight static frequency dividers and one-by-four/one-by-five two-modulus prescalers operate at frequencies over 10 GHz. The emitters of HBT's used in the divider are 12.4 µm2 in size, which is the smallest ever reported for AlGaAs/GaAs HBT IC's. These results indicate that the bridged base electrode technology is promising for developing a variety of high-speed HBT IC's.

Three-dimensional display technologies that require special glasses are not suitable for telecommunications because wearing glasses is inconvenient and it is defficult to observe facial expressions. Our previous 6.3-inch 3D display was inadequate for presenting images with realistic sensation. In this paper, a direct view 15-inch 3D display is described. The display is made up of a l5-inch TFT LCD and a composite lenticular sheet (LS), and uses the head tracking technique. Quantitative evaluation of the stereoscopic sensation of the display was studied using the 3D display, and better stereoscopic sensation values were obtained compared with a 2D display mode, thus comfirming the display's usefulness.

In this paper, we first discuss on a framework for a 3D image display system which is the combination of passive sensing and active display technologies. The passive sensing enables to capture real scenes under natural condition. The active display enables to present arbitrary views with proper motion parallax following the observer's motion. The requirements of passive sensing technology for 3D image displays are discussed in comparison with those for robot vision. Then, a new stereo algorithm, called SEA (Stereo by Eye Array), which satisfies the requirements is described in detail. The SEA uses nine images captured by a 33 camera array. It has the following features for depth estimation: 1) Pixel-based correspondence search enables to obtain a dense and high-spatial-resolution depth map. 2) Correspondence ambiguity for linear edges with the orientation parallel to a particular baseline is eliminated by using multiple baselines with different orientations. 3) Occlusion can be easily detected and an occlusion-free depth map with sharp object boundaries is generated. The feasibility of the SEA is demonstrated by experiments by using real image data.

This paper presents an approach for assembly plan generation from an assembly illustration. Previously, we have already proposed an approach for the assembly plan related information acquisition from an assembly illustration, in which auxiliary lines were taken as clues. However, some ambiguity remains in dynamic information such as assembly operations and their execution order. We have verified through experiments that the ambiguity could be made clear by referring to the feedback information from the completed assemblage after the assembly operations shown in the current illustration. But in fact, in an assembly illustration there are not only the figures of mechanical parts and the auxiliary lines for visualizing their assembly relations, but explanatory words and explanatory lines as well. Explanatory words can basically be classified into two categories: instructions on assembly operations and mechanical part names. The former explicitly describes dynamic information such as the details of assembly operations. The latter also implies dynamic information such as the function of a mechanical part. Explanatory lines are usually drawn for making clear the explanatory relations. Naturally we consider that to integrate the information from explanatory words with that already obtained through the extraction of auxiliary lines will probably enable us to generate an unambiguous assembly plan from the currently observing illustration.

We report the development of high-performance small-scale AlGaAs/GaAs collector-up heterojunction bipolar transistors (C-up HBT) with a carbon (C)-doped base layer. Oxygen-ion (O+) implantation is used to define their intrinsic emitter/base junctions and zinc (Zn)-diffusion is used to lower the resistivity of their O+-implanted extrinsic base layers. The highly resistive O+-implanted AlGaAs layer in the extrinsic emitter region sufficiently suppresses electron injection even under high-forward-bias conditions, allowing high collector current densities. The use of a C-doped base is especially effective for small-scale C-up HBT's because it suppresses the undesirable turn-on voltage shift caused by base dopant diffusion in the intrinsic area around the collector-mesa perimeter that occurs during the high-temperature Zn-diffusion process after implantation. Even in a small-scale trasistor with a 2 µm2 µm collector, a current gain of 15 is obtained. A microwave transistor with a 2 µm10 µm collector has a cutoff frequency fT of 68 GHz and a maximum oscillation frequency fmax of 102 GHz. A small-scale C-up HBT with a 2 µm2 µm collector shows a higher fmax of 110 GHz due to reduced base/collector capacitance CBC and its fmax remains above 100 GHz, even at a low collector current of 1 mA. The CBC of this device is estimated to be as low as 2.2 fF. Current gain dependence on collector size is also investigated for C-up HBT's and it is found that the base recombination current around the collector-mesa perimeter reduces the current gain.

This paper presents a low-power 8-valued cellular array VLSI for high-speed image processing based on logical neighborhood operations with 33 windows. This array is useful for performing low-level image processing such as noise removal and edge detection, in intelligent integrated systems where immediate response to input change as well as high throughput is needed. In order to achieve high-speed image processing, template matching for neighborhood operations can be performed in parallel on each row. Each row of the image is operated in a pipelining manner. The direct 8-valued encoding of the matched results for three different 33 masks makes it possible to reduce the number of operations by one-third. In the hardware implementation, the matching cell for logical neighborhood operations can be implemented compactly using MOS transistors with different threshold voltage, which are programmed by multiple ion implants. Moreover, a new literal circuit for detecting multiple-valued signals using a dynamic design style eliminates hazards due to timing skews in the difference of various input voltage levels, so that the dynamic power dissipation of the proposed circuit is greatly reduced. Finally, it is demonstrated that the processing time of the proposed cellular array is reduced to about 40 percent in comparison with that of a corresponding binary circuit when power dissipation/area = 0.3 W/100 mm2.