This paper discusses and elaborates an analytical model of a multi-stage switched-capacitor (SC) voltage boost converter (VBC) for low-voltage and low-power energy harvesting systems, because the output impedance of the VBC, which is derived from the analytical model, plays an important role in the VBC's performance. In our proposed method, we focus on currents flowing into input and output terminals of each stage and model the VBCs using switching frequency f, charge transfer capacitance CF, load capacitance CL, and process dependent parasitic capacitance's parameter k. A comparison between simulated and calculated results showed that our model can estimate the output impedance of the VBC accurately. Our model is useful for comparing the relative merits of different types of multi-stage SC VBCs. Moreover, we demonstrate the performance of a prototype SC VBC and energy harvesting system using the SC VBC to show the effectiveness and feasibility of our proposed design guideline.

This paper presents two ultra-low voltage and high performance VCO ICs with two novel transformer-based harmonic tuned tanks. The first proposed harmonic tuned tank effectively shapes the pseudo-square drain-node voltage waveform for close-in phase noise reduction. To compensate the voltage drop caused by the transformer, an improved second tank is proposed. It not only has tuned harmonic impedance but also provides a voltage gain to enlarge the output voltage swing over supply voltage limitation. The VCO with second tank exhibits over 3 dB better phase noise performance in 1/f2 region among all tuning range. The two VCO ICs are designed, fabricated and measured on wafer in 45-nm SOI CMOS technology. With only 0.3 V supply voltage, the proposed two VCO ICs exhibit best phase noise of -123.3 and -127.2 dBc/Hz at 10 MHz offset and related FoMs of -191.7 and -192.2 dBc/Hz, respectively. The frequency tuning ranges of them are from 14.05 to 15.14 GHz and from 14.23 to 15.68 GHz, respectively.

Recently, GaN devices are often adopted in microwave power amplifiers to improve the performances. And many new design methods of microwave power amplifier were proposed. As a result, a high-efficiency and super compact microwave signal source has become easily available. It opens up the way for new microwave heating systems. In this paper, the recent progress on design methods of microwave power amplifier and the applications for microwave heating are described. In the first, a device model of GaN transistor is explained. An equivalent thermal model is introduced into the electrical non-linear equivalent device model. In the second, an active load-pull (ALP) measurement system to design a high-efficiency power amplifier is explained. The principle of the conventional closed-loop ALP system is explained. To avoid the risk of oscillation for the closed-loop ALP system, novel ALP systems are proposed. In the third, a microwave heating system is explained. The heating system monitors the reflection wave. Then, the frequency of the signal source and the phase difference between antennas are controlled to minimize the reflection wave. Absorption efficiency of more than 90% was obtained by the control of frequency and phase. In the last part, applications for a medical instrument is described.

Modern deep learning has significantly improved performance and has been used in a wide variety of applications. Since the amount of computation required for the inference process of the neural network is large, it is processed not by the data acquisition location like a surveillance camera but by the server with abundant computing power installed in the data center. Edge computing is getting considerable attention to solve this problem. However, edge computing can provide limited computation resources. Therefore, we assumed a divided/distributed neural network model using both the edge device and the server. By processing part of the convolution layer on edge, the amount of communication becomes smaller than that of the sensor data. In this paper, we have evaluated AlexNet and the other eight models on the distributed environment and estimated FPS values with Wi-Fi, 3G, and 5G communication. To reduce communication costs, we also introduced the compression process before communication. This compression may degrade the object recognition accuracy. As necessary conditions, we set FPS to 30 or faster and object recognition accuracy to 69.7% or higher. This value is determined based on that of an approximation model that binarizes the activation of Neural Network. We constructed performance and energy models to find the optimal configuration that consumes minimum energy while satisfying the necessary conditions. Through the comprehensive evaluation, we found that the optimal configurations of all nine models. For small models, such as AlexNet, processing entire models in the edge was the best. On the other hand, for huge models, such as VGG16, processing entire models in the server was the best. For medium-size models, the distributed models were good candidates. We confirmed that our model found the most energy efficient configuration while satisfying FPS and accuracy requirements, and the distributed models successfully reduced the energy consumption up to 48.6%, and 6.6% on average. We also found that HEVC compression is important before transferring the input data or the feature data between the distributed inference processes.

Nurimisaki and Sashigane are Nikoli's pencil puzzles. We study the computational complexity of Nurimisaki and Sashigane puzzles. It is shown that deciding whether a given instance of each puzzle has a solution is NP-complete.

In this paper, we propose a secure computation of sparse coding and its application to Encryption-then-Compression (EtC) systems. The proposed scheme introduces secure sparse coding that allows computation of an Orthogonal Matching Pursuit (OMP) algorithm in an encrypted domain. We prove theoretically that the proposed method estimates exactly the same sparse representations that the OMP algorithm for non-encrypted computation does. This means that there is no degradation of the sparse representation performance. Furthermore, the proposed method can control the sparsity without decoding the encrypted signals. Next, we propose an EtC system based on the secure sparse coding. The proposed secure EtC system can protect the private information of the original image contents while performing image compression. It provides the same rate-distortion performance as that of sparse coding without encryption, as demonstrated on both synthetic data and natural images.

This paper proposes a technique that increases the lifetime of large scale integration (LSI) devices. As semiconductor technology improves at miniaturizing transistors, aging effects due to bias temperature instability (BTI) seriously affects their lifetime. BTI increases the threshold voltage of transistors thereby also increasing the delay of an electronics device, resulting in failures due to timing violations. To compensate for aging-induced timing violations, we exploit configurable approximate computing. Assuming that target circuits have exact and approximate modes, they are configured for the approximate mode if an aging sensor predicts violations. Experiments using an example circuit revealed an increase in its lifetime to >10 years.

Approximate multiplier design is an effective technique to improve hardware performance at the cost of accuracy loss. The current approximate multipliers are mostly ASIC-based and are dedicated for one particular application. In contrast, FPGA has been an attractive choice for many applications because of its high performance, reconfigurability, and fast development round. This paper presents a novel methodology for designing approximate multipliers by employing the FPGA-based fabrics (primarily look-up tables and carry chains). The area and latency are significantly reduced by applying approximation on carry results and cutting the carry propagation path in the multiplier. Moreover, we explore higher-order multipliers on architectural space by using our proposed small-size approximate multipliers as elementary modules. For different accuracy-hardware requirements, eight configurations for approximate 8×8 multiplier are discussed. In terms of mean relative error distance (MRED), the error of the proposed 8×8 multiplier is as low as 1.06%. Compared with the exact multiplier, our proposed design can reduce area by 43.66% and power by 24.24%. The critical path latency reduction is up to 29.50%. The proposed multiplier design has a better accuracy-hardware tradeoff than other designs with comparable accuracy. Moreover, image sharpening processing is used to assess the efficiency of approximate multipliers on application.

Although the classical vector median filter (VMF) has been widely used to suppress the impulse noise in the color image, many thin color curve pixels aligned in arbitrary directions are usually removed out as impulse noise. This serious problem can be solved by the proposed method that can protect the thin curves in arbitrary direction in color image and remove out the impulse noise at the same time. Firstly, samples in the 3x3 filter window are considered to preliminarily detect whether the center pixel is corrupted by impulse noise or not. Then, samples outside a 5x5 filter window are conditionally and partly considered to accurately distinguish the impulse noise and the noise-free pixel. At last, based on the previous outputs, samples on the processed positions in a 3x3 filter window are chosen as the samples of VMF operation to suppress the impulse noise. Extensive experimental results indicate that the proposed algorithm can be used to remove the impulse noise of color image while protecting the thin curves in arbitrary directions.

Simultaneous multithreading technology (SMT) can effectively improve the overall throughput and fairness through improving the resources usage efficiency of processors. Traditional works have proposed some metrics for evaluation in real systems, each of which strikes a trade-off between fairness and throughput. How to choose an appropriate metric to meet the demand is still controversial. Therefore, we put forward suggestions on how to select the appropriate metrics through analyzing and comparing the characteristics of each metric. In addition, for the new application scenario of cloud computing, the data centers have high demand for the quality of service for killer applications, which bring new challenges to SMT in terms of performance guarantees. Therefore, we propose a new metric P-slowdown to evaluate the quality of performance guarantees. Based on experimental data, we show the feasibility of P-slowdown on performance evaluation. We also demonstrate the benefit of P-slowdown through two use cases, in which we not only improve the performance guarantee level of SMT processors through the cooperation of P-slowdown and resources allocation strategy, but also use P-slowdown to predict the occurrence of abnormal behavior against security attacks.

A method of determining emission limits was studied by using the amplitude probability distribution (APD) for low-probability pulsed electromagnetic disturbances due to discharge. The features of this method are 1) without using the previously reported relationship between APD and bit error rate, the limits are derived using the measured impact of a pulsed disturbance on various wireless communication systems having different bandwidths, and 2) disturbances caused by discharge with poor reproducibility are simulated by regularly repeated pulse-modulated sine waves to enable stable evaluation of the communication quality. APD-based limits are determined from the pulse repetition frequency of the simulated disturbance such that the block error rate (BLER) is less than a certain limit in wireless systems that are most sensitive to the pulsed disturbance. In the international standard CISPR 32 regulating electromagnetic disturbance, radiated disturbance due to discharge is excluded from the application of peak detection limits because of its low occurrence probability. In this paper we quantitatively determine appropriate criteria of the probability for the exclusion. Using the method, we measured the impact of low-probability pulsed interference on major wireless systems and found that GSM and Wi-Fi systems were the most sensitive. New APD-based limits were derived on the basis of these findings. The APD-based limits determined by the proposed method enable a valid evaluation of low-occurrence-probability pulsed disturbances without unconditionally excluding the measurement.

Wireless full duplex (FD) communication can double the point-to-point throughput. To fully realize the benefits of the FD technique in wireless local area networks (WLANs), it is important to design the medium access control (MAC) protocols for FD communications. In FD MAC protocols, when a node wins the channel contention and transmits a primary transmission, its destination node can start a secondary transmission triggered by the primary transmission. Each secondary transmitter transmits a data frame even if its backoff timer is not zero. However, the backoff scheme in the FD MAC protocols follows the conventional scheme based on the distributed coordination function (DCF). Therefore, the nodes with FD MAC initialize the contention window (CW) size to minimum CW (CWmin) after their successful secondary transmissions. Therefore, CW initialization in the FD MAC causes further collisions at stations (STAs), which degrades network throughput. This paper proposes a novel backoff scheme for FD MAC protocols. In the proposed scheme, the CW size and backoff timer are not initialized but kept the current value after secondary transmissions. The proposed scheme can mitigate frame collisions at STAs and increase FD-transmission opportunity in the network, and then enhance the throughput significantly. This paper presents comprehensive performance evaluation in simulations, including non-saturation and saturation conditions, and co-existence conditions with legacy half duplex (HD) STAs. For performance analysis, this paper establishes Markov-chain models for the proposed scheme. The analytical results show theoretically that the operation of the proposed scheme enhances network throughput. The simulation results and analytical results show the effectiveness of the proposed scheme.

This paper proposes a computational complexity-reduced algorithm for an adaptive peak-to-average power ratio (PAPR) reduction method previously developed by members of our research group that uses the null space in a multiple-input multiple-output (MIMO) channel for MIMO-orthogonal frequency division multiplexing (OFDM) signals. The proposed algorithm is an extension of the peak cancellation (PC) signal-based method that has been mainly investigated for per-antenna PAPR reduction. This method adds the PC signal, which is designed so that the out-of-band radiation is removed/reduced, directly to the time-domain transmission signal at each antenna. The proposed method, referred to as PCCNC (PC with channel-null constraint), performs vector-level signal processing in the PC signal generation so that the PC signal is transmitted only to the null space in the MIMO channel. We investigate three methods to control the beamforming (BF) vector in the PC signal, which is a key factor in determining the achievable PAPR performance of the algorithm. Computer simulation results show that the proposed PCCNC achieves approximately the same throughput-vs.-PAPR performance as the previous method while dramatically reducing the required computational cost.

Fast computation of singular value decomposition (SVD) is of great interest in various machine learning tasks. Recently, SVD methods based on randomized linear algebra have shown significant speedup in this regime. For processing large-scale data, computing systems with accelerators like GPUs have become the mainstream approach. In those systems, access to the input data dominates the overall process time; therefore, it is needed to design an out-of-core algorithm to dispatch the computation into accelerators. This paper proposes an accurate two-pass randomized SVD, named block randomized SVD (BRSVD), designed for matrices with a slow-decay singular spectrum that is often observed in image data. BRSVD fully utilizes the power of modern computing system architectures and efficiently processes large-scale data in a parallel and out-of-core fashion. Our experiments show that BRSVD effectively moves the performance bottleneck from data transfer to computation, so that outperforms existing randomized SVD methods in terms of speed with retaining similar accuracy.

Blockchain is a distributed ledger system composed of a P2P network and is used for a wide range of applications, such as international remittance, inter-individual transactions, and asset conservation. In Blockchain systems, tamper resistance is enhanced by the property of transaction that cannot be changed or deleted by everyone including the creator of the transaction. However, this property also becomes a problem that unintended transaction created by miss operation or secret key theft cannot be corrected later. Due to this problem, once an illegal transaction such as theft occurs, the damage will expand. To suppress the damage, we need countermeasures, such as detecting illegal transaction at high speed and correcting the transaction before approval. However, anomaly detection in the Blockchain at high speed is computationally heavy, because we need to repeat the detection process using various feature quantities and the feature extractions become overhead. In this paper, to accelerate anomaly detection, we propose to cache transaction information necessary for extracting feature in GPU device memory and perform both feature extraction and anomaly detection in the GPU. We also propose a conditional feature extraction method to reduce computation cost of anomaly detection. We employ anomaly detection using K-means algorithm based on the conditional features. When the number of users is one million and the number of transactions is 100 millions, our proposed method achieves 8.6 times faster than CPU processing method and 2.6 times faster than GPU processing method that does not perform feature extraction on the GPU. In addition, the conditional feature extraction method achieves 1.7 times faster than the unconditional method when the number of users satisfying a given condition is 200 thousands out of one million.

This paper proposes an efficient server selection scheme in successive participation scenario with participating-domain segmentation. The scheme is utilized by distributed processing systems for real-time interactive communication to suppress the communication latency of a wide-area network. In the proposed scheme, users participate for server selection one after another. The proposed scheme determines a recommended server, and a new user selects the recommended server first. Before each user participates, the recommended servers are determined assuming that users exist in the considered regions. A recommended server is determined for each divided region to minimize the latency. The new user selects the recommended available server, where the user is located. We formulate an integer linear programming problem to determine the recommended servers. Numerical results indicate that, at the cost additional computation, the proposed scheme offers smaller latency than the conventional scheme. We investigate different policies to divide the users' participation for the recommended server finding process in the proposed scheme.

Previously, dynamic multi-hop shortcut (DMHS) communications to improve packet delivery rate and reduce end-to-end transmission delay was proposed. In this letter, we theoretically derive the end-to-end throughput of DMHS considering the retransmission at each node for a simple network model without considering collision. Moreover, we show the validity of the derived expression using computer simulations, and we clarify the effect of various parameters on the throughput using DMHS.

In this paper, we explore the security of single-key Even-Mansour ciphers against key-recovery attacks. First, we introduce a simple key-recovery attack using key relations on an n-bit r-round single-key Even-Mansour cipher (r-SEM). This attack is feasible with queries of DTr=O(2rn) and $2^{rac{2r}{r + 1}n}$ memory accesses, which is $2^{rac{1}{r + 1}n}$ times smaller than the previous generic attacks on r-SEM, where D and T are the number of queries to the encryption function EK and the internal permutation P, respectively. Next, we further reduce the time complexity of the key recovery attack on 2-SEM by a start-in-the-middle approach. This is the first attack that is more efficient than an exhaustive key search while keeping the query bound of DT2=O(22n). Finally, we leverage the start-in-the-middle approach to directly improve the previous attacks on 2-SEM by Dinur et al., which exploit t-way collisions of the underlying function. Our improved attacks do not keep the bound of DT2=O(22n), but are the most time-efficient attacks among the existing ones. For n=64, 128 and 256, our attack is feasible with the time complexity of about $2^{n} cdot rac{1}{2 n}$ in the chosen-plaintext model, while Dinur et al.'s attack requires $2^{n} cdot rac{{ m log}(n)}{ n} $ in the known-plaintext model.

Aiming at the problem of low accuracy of target selection in indirect touch input, an indirect multi-touch input device was designed and built. We explored here four indirect touch input techniques which were TarConstant, TarEnlarge, TarAttract, TarEnlargeAttract, and investigated their performance when subjects completing the target selection tasks through comparative experiments. Results showed that TarEnlargeAttract enabled the shortest movement time along with the lowest error rate, 2349.9ms and 10.9% respectively. In terms of learning effect, both TarAttract and TarEnlargeAttract had learning effect on movement time, which indicated that the speed of these two techniques can be improved with training. Finally, the strategy of improving the accuracy of indirect touch input was given, which has reference significance for the interface design of indirect touch input.

Full duplex (FD) communication can potentially double the throughput of a point-to-point link in wireless communication. Additionally, FD communication can mitigate the hidden node collision problem. The MAC protocols for FD communications are classified into two types; synchronous FD MAC and asynchronous one. Though the synchronous FD MAC mitigates hidden node collisions by using control frame, overhead duration for each data frame transmission may be a bottleneck for the networks. On the other hand, the asynchronous FD MAC mitigates the hidden node collisions by FD communication. However, it wastes more time due to transmission failure than synchronous FD MAC. Clarifying the effect of two major FD MAC types on networks requires a quantitative evaluation of the effectiveness of these protocols in networks with hidden node collisions. This paper proposes performance analysis of FD MAC protocols for wireless local area networks with hidden node collisions. Through the proposed analytical model, the saturated throughputs in FD WLANs with both asynchronous and synchronous FD MAC for any number of STAs and any payload size can be obtained.