In this paper, a method is proposed to construct a visual secret sharing (VSS) scheme for multiple secret images in which each share can be rotated with 180 degrees in decryption. The proposed VSS scheme can encrypt more number of secret images compared with the normal VSS schemes. Furthermore, the proposed technique can be applied to the VSS scheme that allows to turn over some shares in decryption. From the theoretical point of view, it is interesting to note that such VSS schemes cannot be obtained from so-called basis matrices straightforwardly.

Based on recent results for 2-D continuous-discrete systems, this paper develops 2-D Laplace-z transform, which can be used to analyze 2-D continuous-discrete signals and system in Laplace-z hybrid domain. Current 1-D Laplace transformation and z transform can be combined into the new 2-D s-z transform. However, 2-D s-z transformation is not a simple extension of 1-D transform, in 2-D case, we need consider the 2-D boundary conditions which don't occur in 1-D case. The hybrid 2-D definitions and theorems are given in the paper. To verify the results of this paper, we also derived a numerical inverse 2-D Laplace-z transform, applying it to show the 2-D pulse response of a stable 2-D continuous-discrete system.

Researchers have proposed numerous approaches to providing Quality-of-Service (QoS) across the Internet. The IETF has proposed two reservation approaches: hop-by-hop bandwidth reservation (IntServ); and per-hop behaviour bandwidth reservation (DiffServ). An edge router generates traffic, accepts per-flow reservation and classifies them into predetermined service class; while a core router ensures different QoS guarantees for each service class. We propose an Edge-to-Edge Quality-of-Service Domain in which packet trains with the same service requirements aggregated using packet deadline at edge router. The properties of a packet train like Inter-Packet Departure Time, Inter-flow Departure Time and accumulated packet delay are embedded and used by our quantum-based scheduler and QoS packet forwarding scheme in core routers. Thus, we are able to extract per-queue and per-flow information. Each queue is reconstructed at core router with packets having an expected departure time that is relative to the ingress router. Useful functions like instantaneous service rate and fine granular dropping scheme can be derived with a combination of embedded information and relative virtual clock technique. The encapsulation of our packet train information converges mathematically. Through simulations, we show that our architecture can provide delay and rate guarantees and minimise jitter for QoS-sensitive flows that requires LR-coupled or LR-decoupled reservations.

This paper presents a test input data compression technique, Selective Low-Care Coding (SLC), which can be used to significantly reduce input test data volume as well as the external test channel requirement for multiscan-based designs. In the proposed SLC scheme, we explored the linear dependencies of the internal scan chains, and instead of encoding all the specified bits in test cubes, only a smaller amount of specified bits are selected for encoding, thus greater compression can be expected. Experiments on the larger benchmark circuits show drastic reduction in test data volume with corresponding savings on test application time can be indeed achieved even for the well-compacted test set.

As data integration over the Web has become an increasing demand, there is a growing desire to use XML as a standard format for data exchange. For sharing their grammars efficiently, most of the XML documents in use are associated with a document structure description, such as DTD or XML schema. However, the document structure information is not utilized efficiently in previously proposed techniques of XML query processing. In this paper, we present a novel technique that reduces the disk I/O complexity of XML query processing. We design a schema-based numbering scheme called SPAR that incorporates both structure information and tag names extracted from DTD or XML schema. Based on SPAR, we develop a mechanism called VirtualJoin that significantly reduces disk I/O workload for processing XML queries. As shown by experiments, VirtualJoin outperforms many prior techniques.

The characteristics of various techniques, including some new techniques, in mitigating wavelength contention in optical path setups were compared by simulations. The assumed network here is a WDM photonic network in which each node is equipped with a limited number of wavelength-tunable optical transceivers. In the photonic network, the frequency of optical path setups and releases is very high, because optical path lifetime is short and optical transceivers are time-shared, and therefore, the wavelength contention becomes a serious problem. In this paper, we propose four new techniques to mitigate the phenomenon. In those techniques, a new small-sized parameter, the history number, was introduced based on the conceptual requirements of the assumed network, namely, low-cost and low additional control load. The four proposed techniques are history recording (HR), history notifying (HN), conditional random selection (CRS), and HN with dithering target (HNDT). We have evaluated the characteristics of those techniques along with those of two conventional techniques: no mitigation and random selection (RS). The simulations were carried out while varying four parameters: the maximum generation number, the optical path lifetime, the number of wavelengths, and the number of optical transceivers per node. Consequently, it is clarified that for a sufficient number of wavelengths, namely, almost no limitation on number of wavelengths, the CRS technique is advantageous, and for a small number of wavelengths the HNDT technique is advantageous.

In this paper, we treat a design problem for IIR digital filters described by rational transfer function in discrete space. First, we form the filter design problem using the modified least-squares (MLS) criterion and express it as the quadratic form with respect to the numerator and denominator coefficients. Next, we show the relaxation method using the Lagrange multiplier method in order to search for the good solution efficiently. Additionally we can check the filter stability when designing the denominator coefficients. Finally, we show the effectiveness of the proposed method using a numerical example.

The Reliability-Based Hybrid ARQ (RB-HARQ) scheme, which can be used with error correcting codes using soft-input soft-output (SISO) decoders such as convolutional codes and turbo codes has been proposed. In the RB-HARQ scheme, the error rate performance is improved by selecting the retransmission bits based on Log Likelihood Ratio (LLR) of each bit in the receiver. However, the receiver has to send the bit positions of retransmission bits to the transmitter. Therefore, the RB-HARQ scheme requires a great number of feedback bits. On the other hand, Low Density Parity Check (LDPC) codes are attracting a lot of interest, recently. Because LDPC codes can achieve near Shannon limit performance and be decoded easily compared to turbo code. In this paper, we evaluate the RB-HARQ scheme using LDPC code. Moreover, we propose a RB-HARQ scheme that requires a fewer feedback bits by utilizing a code structure of LDPC code. We refer to the scheme as the RB-HARQ (row base) scheme. We show that the RB-HARQ and RB-HARQ (row base) schemes using LDPC code have better error rate performance than the scheme without ARQ. We also show that the RB-HARQ (row base) scheme has a good trade-off between error rate performance and the number of feedback bits compared to the RB-HARQ scheme.

Scenarios that describe concrete situations of software operation play an important role in software development, especially in requirements engineering. Since scenarios are informal, the correctness of scenarios is hard to be verified. The authors have developed a language for describing scenarios in which simple action traces are embellished. The purposes are to include typed frames based on a simple case grammar of actions and to describe the sequence among events. Based on this scenario language, this paper describes both (1) a correctness-checking method using rules to detect errors (lack of events, extra events, and wrong sequence among events) in a scenario and (2) a retrieval method of rules from rule DB that applicable to scenarios using pre and post- conditions.

In this brief, a chaotic Jerk system is presented. This was obtained by converting the Van der Pol architecture into a third order differential equation, and, after the state-space representation was obtained, adding one innovation term and modifying some proportional parameters. Using Lyapunov exponents, Poincare maps, Fourier spectrum analysis and numerical experiments, we confirm the chaotic nature of the proposed Jerk system. Experimental results are also included.

In software development, comprehensive software reviews and testings are important activities to preserve high quality and to control maintenance cost. However it would be actually difficult to perform comprehensive software reviews and testings because of a lot of components, a lack of manpower and other realistic restrictions. To improve performances of reviews and testings in object-oriented software, this paper proposes a novel model for detecting cost-prone classes; the model is based on Mahalanobis-Taguchi method--an extended statistical discriminant method merging with a pattern recognition approach. Experimental results using a lot of Java software are provided to statistically demonstrate that the proposed model has a high ability for detecting cost-prone classes.

A planar composite right/left-handed leaky wave antenna which operates at W-band is fabricated and its backward to forward beam scanning operation including broadside direction is confirmed experimentally. The scanning angle from 61 to 114 degrees with a frequency scanning range of 76 to 79 GHz is achieved.

In recent years, digital watermarking has become a popular technique for labeling digital images by hiding secret information which can protect the copyright. The goal of this paper is to develop a DCT-based watermarking algorithm for low power and high performance. Our energy-efficient technique focuses on reducing computation required on block-based permutation. Instead of using spacial coefficients proposed by Hsu and Wu's algorithm [1], we use DCT coefficients to pair blocks directly. The approach is implemented by C language and estimated power dissipation using Wattch toolset. The experimental results show that our approach not only reduces 99% energy consumption of pairing mechanism, but also increase the PSNR by 0.414 db for the best case. Moreover, the proposed approach is robust to a variety of signal distortions, such as JPEG, image cropping, sharpening, blurring, and intensity adjusting.

In this paper, a practical clock-scheduling engine is introduced. The minimum feasible clock-period is obtained by using a modified Bellman-Ford shortest path algorithm. Then an optimum cost clock-schedule is obtained by using a bipartite matching algorithm. It also provides useful information to circuit synthesis tools. The experiment to a circuit with about 10000 registers and 100000 signal paths shows that a result is obtained within a few minutes. The computation time is almost linear to the circuit size in practice.

Because of the data correlation in the motion estimation (ME) algorithm of H.264/AVC reference software, it is difficult to implement an efficient ME hardware architecture. In order to make parallel processing feasible, four modified hardware friendly ME workflows are proposed in this paper. Based on these workflows, a scalable full search ME architecture is presented, which has following characteristics: (1) The sum of absolute differences (SAD) results of 44 sub-blocks is accumulated and reused to calculate SADs of bigger sub-blocks. (2) The number of PE groups is configurable. For a search range of MN pixels, where M is width and N is height, up to M PE groups can be configured to work in parallel with a peak processing speed of N16 clock cycles to fulfill a full search variable block size ME (VBSME). (3) Only conventional single port SRAM is required, which makes this architecture suitable for standard-cell-based implementation. A design with 8 PE groups has been realized with TSMC 0.18 µm CMOS technology. The core area is 2.13 mm1.60 mm and clock frequency is 228 MHz in typical condition (1.8 V, 25).

Ants-based routing algorithms have attracted the attention of researchers because they are more robust, reliable, and scalable than other conventional routing algorithms. Since they do not involve extra message exchanges to maintain paths when network topology changes, they are suitable for mobile ad-hoc networks where nodes move dynamically and topology changes frequently. As the number of nodes increases, however, the number of ants (i.e., mobile agents or control messages) also increases, which means that existing algorithms have poor scalability. In this paper, we propose a scalable ant-based routing algorithm that keeps the overhead low while keeping paths short. Our algorithm uses a multistep TTL (Time To Live) scheme, an effective message migration scheme, and an efficient scheme for updating the probability of packet forwarding. Simulation experiments have confirmed that our proposed algorithm can establish shorter paths than the conventional ant-based algorithm with the same signaling overhead.

In this paper, two new modulation schemes, Multi-Pulse Modulation (MPM) and Differential Multi-Pulse Modulation (DMPM) have been proposed in order to increase the total data rate and improve the error performance. By these schemes, the modulated pulse that had been used for transmitting only one data bit in each pulse-pair in conventional TR-UWB system, can be used for transmitting more than one bit data depending on the level of modulation. Moreover, the error performance has been improved by these new modulation schemes because for the same Eb/N0, the energy per pulse has increased. In addition, these new modulation schemes are applied to a multiple access system. The simulation results show that the total throughput performance of the proposed system has been improved, nearly 2-4 times when compared to the conventional TR-UWB communication system.

With the increasing demand for SoCs to include rich functionality, SoCs are being designed with hundreds of small memories with different sizes and frequencies. If memory BIST logics were individually added to these various memories, the area overhead would be very high. To reduce the overhead, memory BIST logic must therefore be shared. This paper proposes a memory-grouping method for memory BIST logic sharing. A memory-grouping problem is formulated and an algorithm to solve the problem is proposed. Experimental results show that the proposed method reduced the area of the memory BIST wrapper by up to 40.55%. The results also show that the ability to select from two types of connection methods produced a greater reduction in area than using a single connection method.

We propose optical wireless multiple-input multiple-output (OMIMO) communications to achieve high speed transmission with a compact transmitter and receiver. In OMIMO, by using zero forcing (ZF), minimum mean square error (MMSE) or other detection techniques, we can eliminate the interference from the other optical transmit antennas. In this paper, we employ ZF as the detection technique. We analyze the signal-to-interference-plus-noise ratio (SINR) and the bit error rate (BER) of the proposed OMIMO with a linear array and a square array of optical transmit and receive antennas, where we employ subcarrier multiplexing (SCM) for each optical transmit antenna. Note that the proposed OMIMO is applicable to other arrangements of optical transmit and receive antennas. We show that the proposed OMIMO system can realize MIMO multiplexing and achieve high speed transmission by correctly aligning the optical transmit and receive antennas and the transmitter semiangle.

This paper shows that the Surrounding Gate Transistor (SGT) can be scaled down to decananometer gate lengths by using an intrinsically-doped body and gate work function engineering. Strong gate controllability is an essential characteristics of the SGT. However, by using an intrinsically-doped body, the SGT can realize a higher carrier mobility and stronger gate controllability of the silicon body. Then, in order to adjust the threshold voltage, it is necessary to adopt gate work function engineering in which a metal or metal silicide gate is used. Using a three-dimensional (3D) device simulator, we analyze the short-channel effects and current characteristics of the SGT. We compare the device characteristics of the SGT to those of the Tri-gate transistor and Double-Gate (DG) MOSFET. When the silicon pillar diameter (or silicon body thickness) is 10 nm, the gate length is 20 nm, and the oxide thickness is 1 nm, the SGT shows a subthreshold swing of 63 mV/dec and a DIBL of -17 mV, whereas the Tri-gate transistor and the DG MOSFET show a subthreshold swing of 71 mV/dec and 77 mV/dec, respectively, and a DIBL of -47 mV and -75 mV, respectively. By adjusting the value of the gate work function, we define the off current at VG = 0 V and VD = 1 V. When the off current is set at 1 pA/µm, the SGT can realize a high on current of 1020 µA/µm at VG = 1 V and VD = 1 V. Moreover, the on current of the SGT is 21% larger than that of the Tri-gate transistor and 52% larger than that of the DG MOSFET. Therefore, the SGT can be scaled reliably toward the decananometer gate length for high-speed and low-power ULSI.