Target reconstruction algorithm from its monostatic radar cross section (RCS) has been proposed for polygonal cylinders with curved surfaces. This algorithm is based on our previous finding that the main contribution to the back scattering is due to edge diffracted fields excited at a facet of nearly specular reflection direction. Dimension of this constitutive facet of the target is estimated from the local maxima and its lobe width in the angular RCS variation. Half and quarter circular cylinders are used as canonical scattering objects, and their measured and numerically simulated monostatic RCS values have been studied extensively to find scattering pattern characteristic difference between flat and circularly curved surfaces. Thus estimated constitutive facets are connected in order, and this procedure will be continued until the distance between the first and the final edges would be minimized. Our algorithm has been tested for other targets, and it is found that it works well for predicting metal convex targets with flat and curved facets.

There are three well-known approaches to using scan design to apply two-pattern testing: broadside testing (functional justification), skewed-load testing and enhanced scan testing. The broadside and skewed-load testing use the standard scan design, and thus the area overheads are not high. However fault coverage is low. The enhanced scan testing uses the enhanced scan design. The design uses extra latches, and allows scan-in any two-pattern testing. While this method achieves high fault coverage, it causes high area overhead because of extra latches. This paper presents a new scan design where two-pattern testing with high fault coverage can be performed with area overhead as low as the standard scan design. The proposed scan-FFs are based on master-slave FFs. The input of each scan-FF is connected to the output of the master latch and not the slave latch of the previous FF. Every scan-FF maintains the output value during scan-shift operations.

The authors propose the simple and efficient method based on the shooting and bouncing rays (SBR) method in order to evaluate multi-reflection effects inside a radome. In this paper, we show the analysis procedure of the proposed method. Next, we compare calculated data with some measured data in order to verify the proposed method. We confirmed that the proposed method is effective for the objects with radome except the areas where strong edge diffraction appears.

Gossip-based reliable broadcast protocols with reasonably weak reliability properties scale well to large groups and degrade system performance gracefully even if node failure or message loss rates increase compared with traditional protocols. However, although many distributed applications require highly steady performance only by allowing causality to be used asynchronously, there is no existing gossip-based protocol offering causally ordered delivery property more lightweight than totally ordered delivery one. This paper presents an application-level broadcast algorithm to guarantee causally-ordered delivery semantics based on peer to peer interaction models for scalability, reasonable reliability and stable throughput. Processes propagate each message with a vector time stamp much like the spread of rumor in society for a fixed number of rounds. Upon receipt of these messages, correct processes immediately deliver the corresponding messages to the application layers in a causal order. Simulation results show that the proposed algorithm outperforms the existing ones in terms of delivery throughput.

It has been observed in the literature that the characteristic polynomial of a discrete system can be computed from the characteristic impulse response Gramian. In this letter it is shown that a given characteristic impulse response Gramian, in fact, contains information on two characteristic polynomials. The importance of this result is illustrated through an application to model reduction of discrete systems.

With VLSI design development, the increasingly severe power problem requests to minimize clock routing wirelength so that both power consumption and power supply noise can be alleviated. In contrast to most of traditional works that handle this problem only in clock routing, we propose to navigate standard cell register placement to locations that enable further less clock routing wirelength and power. To minimize adverse impacts to conventional cell placement goals such as signal net wirelength and critical path delay, the register placement is carried out in the context of a quadratic placement. The proposed technique is particularly effective for the recently popular prescribed skew clock routing. Experiments on benchmark circuits show encouraging results.

This paper presents a processor architecture for high-speed and reliable stereo matching based on adaptive window-size control of SAD (Sum of Absolute Differences) computation. To reduce its computational complexity, SADs are computed using images divided into non-overlapping regions, and the matching result is iteratively refined by reducing a window size. Window-parallel-and-pixel-parallel architecture is also proposed to achieve to fully exploit the potential parallelism of the algorithm. The architecture also reduces the complexity of an interconnection network between memory and functional units based on the regularity of reference pixels. The stereo matching processor is implemented on an FPGA. Its performance is 80 times higher than that of a microprocessor (Pentium4@2 GHz), and is enough to generate a 3-D depth image at the video rate of 33 MHz.

This work presents a frequency-scaling low-power (FSLP) design methodology for managing power consumption of cores in the tile-based network-on-chip (NOC) architecture. A moving picture experts group (MPEG) core is tested using the field-programmable gate array (FPGA) implementation to verify the feasibility of the proposed method. Measurement results show that about 30% power consumption can be saved in the MPEG core and reveal that the proposed FSLP design method can be suitable for cores in the tile-based NOC applications.

A low-power field-programmable VLSI (FPVLSI) is presented to overcome the problem of large power consumption in field-programmable gate arrays (FPGAs). To reduce power consumption in routing networks, the FPVLSI consists of cells that are based on a bit-serial pipeline architecture which reduces routing block complexity. Moreover, a level-converter-less multiple-supply-voltage scheme using dynamic circuits is proposed, where the cells in non-critical paths use a low supply voltage for low power under a speed constraint. The FPVLSI is evaluated based on a 0.18-µm CMOS design rule. The power consumption of the FPVLSI using multiple supply voltages is reduced to 17% or less compared to that of the static-circuit-based FPVLSI using multiple supply voltages.

This paper shows a design method for a sequential circuit by using a Look-Up Table (LUT) ring. The method consists of two steps: The first step partitions the outputs into groups. The second step realizes them by LUT cascades, and allocates the cells of the cascades into the memory. The system automatically finds a fast implementation by maximally utilizing available memory. With the presented algorithm, we can easily design sequential circuits satisfying given specifications. The paper also compares the LUT ring with logic simulator to realize sequential circuits: the LUT ring is 25 to 237 times faster than a logic simulator that uses the same amount of memory.

In this paper, a new method based on the mode-matching method in the sense of least squares is presented for analyzing the two dimensional scattering problem of TE plane wave incidence to the infinite plane surface with an arbitrary imperfection of finite extent. The semi-infinite upper and lower regions of that surface are a vacuum and a perfect conductor, respectively. Therefore the discussion of this paper is developed about the Dirichlet boundary value problem. In this method, the approximate scattered wave is represented by the integral transform with band-limited spectrum of plane waves. The boundary values of those scattered waves are described by only abscissa z and Fourier spectra are obtained by applying the ordinary Fourier transform. Moreover, new approximate functions are made by inverse Fourier transform of band-limited those spectra. Consequently, the integral equations of Fredholm type of second kind for spectra of approximate scattered wave functions are derived by matching those new functions to exact boundary value in the sense of least squares. Then it is shown analytically and numerically that the sequence of boundary values of approximate wave functions converges to the exact boundary value, namely, the boundary value of the exact scattered wave in the sense of least squares when the profile of imperfection part is described by continuous and piecewise smooth function at least. Moreover, it is shown that this sequence uniformly converges to exact boundary value in arbitrary finite region of the boundary and the sequence of approximate wave functions uniformly converges to the exact scattered field in arbitrary subdomain in the upper vacuum domain of the boundary in wider sense when the uniqueness of the solution of the Helmholtz equation is satisfied with regard to the profile of the imperfection parts of the boundary.

In this paper, we propose a voltage controlled oscillator (VCO) with up mode type Miller-integrator. The controlled voltage of this VCO can continuously change 0 V center in the positive and negative bidirection. Also, the relationship between control voltage and oscillating frequency shows the good linearity, and the calculated and the measured values agree well.

This paper presents a standard cell-based frequency synthesizer with dynamic frequency counting (DFC) for multiplying input reference frequency by N times. The dynamic frequency counting loop uses variable time period to estimate and tune the frequency of digitally-controlled oscillator (DCO) which enhances frequency detection's resolution and loop stability. Two ripple counters serve as frequency estimator. Conventional phase-frequency detector (PFD) thus is replaced with a digital arithmetic comparator to yield a divider-free circuit structure. Additionally, a 15 bits DCO with the least significant bit (LSB) resolution 1.55 ps is designed by using the gate capacitance difference of 2-input NOR gate in fine-tuning stage. A modified incremental data weighted averaging (IDWA) circuit is also designed to achieve improved linearity of DCO by dynamic element matching (DEM) skill. Based on the proposed standard cell-based frequency synthesizer, a test chip is designed and verified on 0.35-µm complementary metal oxide silicon (CMOS) process, and has a frequency range of (18-214) MHz at 3.3 V with peak-to-peak (Pk-Pk) jitter of less than 70 ps at 192 MHz/3.3 V.

This paper presents a fuzzy optimization based scheduling method for the manufacturing systems with uncertain production capacities. To address the uncertainties efficiently, the fuzzy optimization technique is used in defining the scheduling problem. Based on the symmetric approach of fuzzy optimization and Lagrangian relaxation technique, a practical fuzzy-optimization based algorithm is developed. The computational experiments based on the real factory data demonstrate that the proposed method provides robust scheduling to hedge against uncertainties.

Design of portable battery operated multimedia devices requires energy-efficient multiplication circuits. This paper proposes a novel architectural technique to reduce power consumption of digital multipliers. Unlike related approaches which focus on multiplier transition activity reduction, we concentrate on dynamic reduction of supply voltage. Two implementation schemes capable of dynamically adjusting a double voltage supply to input data variation are presented. Simulations show that using these schemes we can reduce energy consumption of 1616-bit multiplier by 34% and 29% on peak and by 10% and 7% on average with area overhead of 15% and 4%, respectively, while maintaining the performance of traditional multiplier.

A supervisor proposed by Ramadge and Wonham controls a discrete event system (DES) so as to satisfy logical control specifications. However a precise description of both the specifications and the DES is needed for the control. This paper proposes a synthesis method of the supervisor for decentralized DESs based on reinforcement learning. In decentralized DESs, several local supervisors exist and control the DES jointly. Costs for disabling and occurrence of events as well as control specifications are considered. By using reinforcement learning, the proposed method is applicable under imprecise specifications and uncertain environment.

A batch process is a discontinuous and concurrent process which is suitable for multi-product, small-sized production. The distinctive feature of a batch process is that various decision making processes, such as scheduling, design, operation, etc. are strongly connected with each other. Interaction among these processes is necessary to dynamically and flexibly cope with a variety of unplanned events. This paper aims at presenting a batch scheduling technique based on Petri net models and showing the possibilities of integration between scheduling and design of batch processes. For this purpose, it first views the behavior of a batch operating system as a discrete event system and presents a Petri net model to be used for scheduling, design and operation. It next formulates batch scheduling problems based on Petri net partial languages, proposes their solution technique and last discusses the integration between scheduling and design of batch systems.

This paper develops an efficient multi-user bit and power allocation algorithm in an iterative fashion for discrete multi-tone systems. The model of the interference channel is considered, where the transmit signal from each user causes interference to the other users. The scheme aims to minimize the total transmit power while satisfying the required data rate of each user. The proposed algorithm is shown to greatly reduce the computational complexity of the existing algorithm with negligible amount of transmit power increment as demonstrated in the simulation results. The proposed methodology can be applied to the DMT-based system, but is also feasible for either wired or wireless communication systems with the model of the interference channel and another type of modulation scheme.

This paper considers the low-frequency scattering by a circular dielectric cylinder and modifies the exact polarizability tensor to extend the valid region of the known low-frequency solution. When compared to the traditional formulation, the proposed solution is shown to be valid for cylinders with a higher dielectric constant and larger radius.

Frequency-domain and time-domain novel uniform asymptotic solutions for the scattered fields by an impedance cylinder and a dielectric cylinder, with a radius of curvature sufficiently larger than the wavelength, are presented in this paper. The frequency-domain novel extended UTD and the modified UTD solutions, derived by retaining the higher-order terms in the integrals for the scattered fields, may be applied in the deep shadow region in which the conventional UTD solutions produce the substantial errors. The novel time-domain uniform asymptotic solutions are derived by applying the saddle point technique in evaluating the inverse Fourier transform. We have confirmed the accuracy and validity of the uniform asymptotic solutions both in the frequency-domain and in the time-domain by comparing those solutions with the reference solutions calculated from the eigenfunction expansion (frequency-domain) and from the hybrid eigenfunction expansion and fast Fourier transform (FFT) method (time-domain).