This paper is consisting of the two novel EMC technologies that we have been developed in our laboratory. The first is the technology for measuring the RF (Radio Frequency) nearby magnetic field and estimation of the RF current in the printed circuit board (PCB) by using the small loop antenna with multi-layer PCB structure developed by our laboratory. I introduce the application of our small loop antenna with its physical structure and the analysis of the nearby magnetic field distribution of the printed circuit board applying the discrete Wavelet analysis. We can understand the behavior of the digital circuit in detail, and we can also take measures to meet the specification about the electromagnetic radiation from the digital circuit from the higher order of priority by using these technologies. The second is our proposing novel technology for reducing the electromagnetic radiation from the digital equipment by taking notice of the improvement of the de-coupling in the PCB. We confirmed the remarkable effect of this technology by redesigning the motherboard of the small-sized computer.

In Adleman's Function Field Sieve algorithm solving the discrete logarithm problem in a finite field, it is assumed that a random bivariate polynomial in the certain class is absolutely irreducible with high probability. In this letter we point out that if we use Cab type random polynomials then we always get absolutely irreducible polynomials. We can also simplify the calculation of a product of many rational functions on a curve that belongs to the field of definition by the use of a Cab curve.

In this paper, the generalized learning vector quantization (GLVQ) algorithm is applied to design a hand-written Chinese character recognition system. The system proposed herein consists of two modules, feature transformation and recognizer. The feature transformation module is designed to extract discriminative features to enhance the recognition performance. The initial feature transformation matrix is obtained by using Fisher's linear discriminant (FLD) function. A template matching with minimum distance criterion recognizer is used and each character is represented by one reference template. These reference templates and the elements of the feature transformation matrix are trained by using the generalized learning vector quantization algorithm. In the experiments, 540100 (5401 100) hand-written Chinese character samples are used to build the recognition system and the other 540100 (5401 100) samples are used to do the open test. A good performance of 92.18 % accuracy is achieved by proposed system.

A novel method for the radiated immunity test is proposed. The method is to generate controlled electromagnetic fields applying in arbitrary directions to an under test. The fields rotate at a low speed controlled electrically so that the immunity characteristics may be known in more detail. The primal characteristics of the fields generated by a trial benchtop setup are investigated.

In this paper we introduce a CMOS low voltage/low power (LV/LP) voltage controlled oscillator (VCO). It includes a simple V-I converter, a current controlled ring oscillator based on new differential delay cells, and a source-coupled differential pair to convert differential signal to single-ended signal. The V-I converter is implemented as a source follower type, exhibiting excellent linearity of transconductance with low power consumption. The new delay cell employs local positive feedback to increase its DC gain, achieving stable oscillation at low supply voltage. The simulation and measurement results are given to show the linearity between the input (control voltage) and the output (frequency) in the frequency range of 100 MHz to 400 MHz with 1. 2 V power supply. The VCO only consumes power of 2.25 mW at operating frequency of 400 MHz and 1.2 V supply.

In this article we present a survey of medical image processing with the stress on applications of image generation and pattern recognition / understanding to computer aided diagnosis (CAD) and surgery (CAS). First, topics and fields of research in medical image processing are summarized. Second the importance of the 3D image processing and the use of virtualized human body (VHB) is pointed out. Thirdly the visualization and the observation methods of the VHB are introduced. In the forth section the virtualized endoscope system is presented from the viewpoint of the observation of the VHB with the moving viewpoints. The fifth topic is the use of VHB with deformation such as the simulation of surgical operation, intra-operative aids and image overlay. In the seventh section several topics on image processing methodologies are introduced including model generation, registration, segmentation, rendering and the use of knowledge processing.

This paper describes a flip-flop circuit using a directly controlled emitter-follower with a diode-feedback level stabilizer (DC-DF) and a resistor-feedback level stabilizer (DC-RF) for low-power multi-GHz prescalers. The new flip-flop circuit reduces the emitter-follower current and gains both high-frequency operation and low-power. A dual modulus (4/5) prescaler using this circuit technology was fabricated with a 0.35 µm BiCMOS process. The current draw of the prescaler using the DC-RF is 34% smaller than conventional LCML circuits. The DC-RF prescaler operates at 2.11 GHz with a total current consumption of 1.03 mA. In addition, the circuit operates with a supply voltage of down to 2.4 V by using the resistor level-shift clock-driver.

An extended version of weighted round robin scheduling algorithm for variable length packets is discussed. This can serve each flow fairly even if the length of packets varies. Further, an adaptive scheduling algorithm for bursty traffic is added to better treat multimedia sources. In this paper, an overview of the algorithm is described. Subsequently the throughput, latency, work complexity and elasticity for the algorithm are systematically defined and analyzed. These results show advantages of the algorithm compared with a normal or packet-based weighted round robin algorithm.

The authors report on a 22-Gbit/s static decision IC fabricated with 0. 12-µm GaAs MESFETs. The key to attaining high-speed decision IC is the employment of a novel high-speed D-type flip-flop (D-FF). The D-FF succeeds in faster operation through the simplification of the circuitry and the reduction of the transition time of the output voltages.

In a mobile computing environment, in which communication channels are limited and have low-bandwidths, mobile transactions are long-lived and frequently disconnected with their wireless network in processing. Such peculiarities of mobile transactions make existing transaction scheduling schemes inadequate and raise new challenging research problems. In this paper, we propose a new scheduling scheme called OTS/MT (Optimistic Timestamp Scheme for Mobile Transactions) for mobile transaction scheduling. OTS/MT is based on an optimistic approach that is suitable for low data contention, and prevents indefinite postponement and cascading delay which are major drawbacks of the existing optimistic concurrency control scheme and the timestamp ordering scheme. In addition, the OTS/MT algorithm is inherently a deadlock-free scheduling scheme. In order to schedule mobile transactions, OTS/MT postpones the detection of conflict between mobile transactions until transaction commit time to improve the performance deterioration of TO. In this paper, we attempt to show that this application of optimism to TO is justified by way of simulation.

The conventional synthesis procedure of discrete time sparsely interconnected neural networks (DTSINNs) for associative memories may generate the cells with only self-feedback due to the sparsely interconnected structure. Although this problem is solved by increasing the number of interconnections, hardware implementation becomes very difficult. In this letter, we propose the DTSINN system which stores the 2-dimensional discrete Walsh transforms (DWTs) of memory patterns. As each element of DWT involves the information of whole sample data, our system can associate the desired memory patterns, which the conventional DTSINN fails to do.

In this paper, we present an efficient approach for technology scaling of MOS analog circuits by using circuit optimization techniques. Our new method is based on matching equivalent circuit parameters between a previously designed circuit and the circuit undergoing redesign. This method has been applied to a MOS operational amplifier. We were able to produce a redesigned circuit with almost the same performance in under 4 hours, making this method 5 times more efficient than conventional methods

This paper proposes a 3-stage ATM switch architecture that uses optical WDM (wavelength division multiplexing) grouped links and dynamic bandwidth sharing. The proposed architecture has two features. The first is the use of WDM technology which makes the number of cables used in the system proportional to system size. The second is the use of dynamic bandwidth sharing among WDM grouped links. This prevents the statistical multiplexing gain offered by WDM from falling even if switching system becomes large. A performance evaluation confirms the scaleability and cost-effectiveness of the proposed architecture. It is scaleable in terms of the number of cables and admissible load. We show how the appropriate wavelength signal speed can be determined to implement the switch in a cost-effective manner. Therefore, the proposed architecture will suit future high-speed multimedia ATM networks.

Crosstalk from digital to analog circuits can be causative of operation fails in analog-digital mixed LSIs. This paper describes modeling techniques and simulation strategies of the substrate coupling noise. A macroscopic substrate noise model that expresses the noise as a function of logic state transition frequencies among digital blocks is proposed. A simulation system based on the model is implemented in the mixed signal simulation environment, where performance degradation of the 2nd order ΔΣADC coupled to digital noise sources is clearly simulated. These results indicate that the proposed behavioral modeling approach allows practicable full chip substrate noise simulation measures.

This paper describes the implementation and demonstration of local networks for the hyper-media photonic information network (HM-PIN), a candidate for the information service platform offering broadcast and telecommunication services. In addition, the feasibility of the HM-PIN is also demonstrated using prototype local network systems. This local network adopts architecture based on wavelength-division-multiplexing (WDM) and broadcast-and-select (B&S) switching, and supports all HM-PIN services except inter-local-network communication. The major issues of this proposed network are the technologies that support many broadcast channels and reduce channel selection cost. This paper also considers the combination of WDM technology and three alternatives: electrical TDM, subcarrier multiplexing (SCM or electrical FDM), and optical TDM (O-TDM). Three 128 ch (8 wavelengths 16 channels) WDM B&S prototype systems are built to demonstrate the feasibility of the proposed HM-PIN. In WDM/SCM, 30 and 20 Mb/s channels are realized as 16-QAM and 64-QAM, and 155 Mb/s channels are realized by WDM/TDM. Moreover, these three prototypes were connected to form a small HM-PIN and applications such as video distribution and IP datagram cut-through are demonstrated. Furthermore, the delay and throughput of the HM-PIN are evaluated by connecting a local network to a 200-km WDM-ring backbone network. Our discussions and demonstrations confirm the impact and feasibility of the proposed hyper-media photonic information network.

This paper proposes a 3-stage ATM switch architecture that uses optical WDM (wavelength division multiplexing) grouped links and dynamic bandwidth sharing. The proposed architecture has two features. The first is the use of WDM technology which makes the number of cables used in the system proportional to system size. The second is the use of dynamic bandwidth sharing among WDM grouped links. This prevents the statistical multiplexing gain offered by WDM from falling even if switching system becomes large. A performance evaluation confirms the scaleability and cost-effectiveness of the proposed architecture. It is scaleable in terms of the number of cables and admissible load. We show how the appropriate wavelength signal speed can be determined to implement the switch in a cost-effective manner. Therefore, the proposed architecture will suit future high-speed multimedia ATM networks.

This paper describes the implementation and demonstration of local networks for the hyper-media photonic information network (HM-PIN), a candidate for the information service platform offering broadcast and telecommunication services. In addition, the feasibility of the HM-PIN is also demonstrated using prototype local network systems. This local network adopts architecture based on wavelength-division-multiplexing (WDM) and broadcast-and-select (B&S) switching, and supports all HM-PIN services except inter-local-network communication. The major issues of this proposed network are the technologies that support many broadcast channels and reduce channel selection cost. This paper also considers the combination of WDM technology and three alternatives: electrical TDM, subcarrier multiplexing (SCM or electrical FDM), and optical TDM (O-TDM). Three 128 ch (8 wavelengths 16 channels) WDM B&S prototype systems are built to demonstrate the feasibility of the proposed HM-PIN. In WDM/SCM, 30 and 20 Mb/s channels are realized as 16-QAM and 64-QAM, and 155 Mb/s channels are realized by WDM/TDM. Moreover, these three prototypes were connected to form a small HM-PIN and applications such as video distribution and IP datagram cut-through are demonstrated. Furthermore, the delay and throughput of the HM-PIN are evaluated by connecting a local network to a 200-km WDM-ring backbone network. Our discussions and demonstrations confirm the impact and feasibility of the proposed hyper-media photonic information network.

In this paper, the computational issue in the problem of learning Bayesian belief networks (BBNs) based on the minimum description length (MDL) principle is addressed. Based on an asymptotic formula of description length, we apply the branch and bound technique to finding true network structures. The resulting algorithm searches considerably saves the computation yet successfully searches the network structure with the minimum value of the formula. Thus far, there has been no search algorithm that finds the optimal solution for examples of practical size and a set of network structures in the sense of the maximum posterior probability, and heuristic searches such as K2 and K3 trap in local optima due to the greedy nature even when the sample size is large. The proposed algorithm, since it minimizes the description length, eventually selects the true network structure as the sample size goes to infinity.

This paper describes an algorithm and its prototype system--VeriProc/1. 1--which can prove the correctness of pipelined and superscalar processor controls automatically without a pipeline invariant, human interaction, or additional information. This algorithm is based on behavior-covering and partial unfolding. No timing relations such as an abstract function or β-relation is required. The only information required is to specify the location of the selectors in the design. Partial unfolding makes it possible to derive superscalar specifications from conventional specifications. Correctness proof of the partial unfolding is given. The prototype system can verify various superscalar control designs of simple processors.

Recent work in the area of ultrafast optical time-division multiplexed (OTDM) networking at MIT Lincoln Laboratory is presented. A scalable helical local area network or HLAN architecture, presented elsewhere as an architecture well-suited to ultrafast OTDM LANs and MANs, is considered in the context of wide area networking. Two issues arise in scaling HLAN to the wide area. The first is protocol extension, and the second is supporting the required bandwidth on the long-haul links. In this paper we discuss these challenges and describe progress made in both architecture and technologies required for scaling HLAN to the wide area.