With the foreseen growth of communication capacity, further capacity and flexibility enhancements are required for future transport networks. Photonic switching is expected to be a key technology to solve the potential bottleneck, which could be found in transport network nodes. This paper first explains the "Optical Fiber Freeway" concept, as an example of future transport networks. Following this, the possible optical transport network structure using photonic switching technologies, for realizing the Optical Fiber Freeway concept, is explained. An Optical CrossConnect (OXC) and optical Add/Drop Multiplexer (ADM) are key components. Examples of recent development of photonic switching systems toward these targets are also reviewed. An OXC using photonic Space-Division (SD) switching technology has been proposed and demonstrated. This type of OXC will realize flexible reconfiguration and optical hitless switching, and it can meet the introduction of Wavelength Division Multiplexing (WDM) technique. Line failure restoration operation at 2.4Gb/s has been successfully demonstrated. An optical packet network with a slotted ring/bus structure using a wavelength address technique has been proposed as a packet/cell based optical ADM. The experimental system employs a practical media access control system as well as a fast-wavelength switched transmitter suppressing thermally induced wavelength drift. Cell communication at 622Mb/s has been demonstrated with the experimental system. These results show that hardware technologies have been developed steadily. With a future study on an all optical network management scheme, a high capacity and flexible optical network would be realized.

In this study, a ring of simple chaotic circuits coupled by inductors is investigated. An extremely simple three-dimensional autonomous circuit is considered as a chaotic subcircuit. By carrying out circuit experiments and computer calculations for two, three or four subcircuits case, various synchronization phenomena of chaos are confirmed to be stably generated. For the three subcircuits case, two different synchronization modes coexist, namely in-phase synchronization mode and three-phase synchronization mode. By investigating Poincar map, we can see that two types of synchronizations bifurcate to quasi-synchronized chaos via different bifurcation route, namely in-phase synchronization undergoes period-doubling route while three-phase synchronization undergoes torus breakdown. Further, we investigate the effect of the values of coupling inductors to bifurcation phenomena of two types of synchronizations.

This letter addresses stability problems of interval matrices stemming from robustness issues in control theory. A quick overview is first made pertaining to methods to obtain stability conditions of interval matrices, putting particular emphasis upon one of them, regularity condition approach. Then, making use of this approach, several new stability criteria, for both Hurwitz and Schur stability, are derived.

A problem of obtaining an optimal file transfer on a file transmission net N is to consider how to distribute, with a minimum total cost, copies of a file with some information from a vertex of N to all vertices of N by the respective vertices' copy demand numbers (i.i., needed numbers of copies). The maximum number of copies of file which can be made at a vertex is called the copying number of the vertex. In this paper, we consider as N an arborescence-net with constraints on copying numbers, and give a necessary and sufficient condition for a file transfer to be optimal on N, and furthermore propose an O(n2) algorithm for obtaining an optimal file transfer on N, where n is the number of vertices of N.

This paper deals with an efficient radix-2 divider design theory that uses carry-propagation-free adders based on redundant binary{1, 0, 1} representation. In order to compute the division fast, we look ahead to the next step quotient-digit selection embedded in the current partial remainder calculation. The solution is a function of the four most significant digits of the current partial remainder, when scaling the divisor in the range [1, 9/8). In gate depth, this result is better than the higher radix-4 case without the look-ahead quotient-digit selection and the design is simple.

Circuit design techniques for linearizing adaptively biased differential pairs are described. An emitter-and source-coupled pair is adaptively biased by a squaring circuit to linearize its transconductance, one of whose inputs is divided by resistors. An input signal for a differential pair or a squaring circuit is set to an adequate amplitude by a resistive divider without sacrificing linearity. Therefore, a differential pair is biased by the output current of a squaring circuit and they are coupled directly. There are three design techniques for squaring circuits. One is the transistor-size unbalance technique. Another is the bias offset technique. A third is the multitail technique. The bipolar and MOS squaring circuits discussed in this paper were proposed by the author previously, and consist of transistor-pairs with different transistor size (i.e., the emitter areas or gate W/L values are different), transistor-pairs with the same bias offset, or a multitail cell(i.e., a triple-tail cell or quadritail cell). Several kinds of squaring circuits consisting of such transistor-pairs are applied to produce the quadratic bias currents for compensating the nonlinearity of an emitter-and source-coupled pair. Therefore, four circuits using emitter-coupled pairs with adaptive-biasing current and four circuits using source-coupled pairs with adaptive-biasing current are proposed and analyzed in depth. Furthermore, a circuit configuration for low voltage operation is also introduced and verified with bipolar transistor-arrays on a breadboard.

Some CMOS gates are topologically asymmetric in inputs, even though they are logically symmetric. It implies a possibility to reduce power consumption by optimizing signal assignment to the inputs. In this study we theoretically derive power consumption of 2-input NAND gate based on transition probability of input signals, with taking into account charging current due to an internal node. We also propose a signal assignment method to input terminals for reducing power consumption reduction by extending our method for large circuits, and demonstrate the effect of power consumption reduction by the present method.

In this letter we propose a stabilizing method of phase control for resistively coupled oscillator networks. To demonstrate the effect of the control, we consider the coupled oscillator system containing only voltage type of connections. A state feedback technique to resistor sub-network is used to control the phase of synchronized oscillation. The technique is applied to two and three coupled oscillator cases. Finally we present experimental results, which agree well with the theory.

This paper reports an overload control method for the Intelligent Network (IN). The IN, which is being investigated as a future communication network, facilitates both rapid introduction of new services and easy modification of existing services. In the IN, the call processing functions and data needed to achieve IN services are distributed over several nodes. Therefore, traffic demand for the various services may cause varying patterns of node overloads. It is therefore important to develop effective overload control methods and to evaluate their characteristics. We propose an overload control method and evaluate its characteristics in comparison with other methods under various overload traffic patterns with a network simulator that models all nodes and their relationships in the IN. In particular, we focus on three aspects of overload control: how can high throughput be maintained, how can an overloaded node be stabilized, and how can fair access be guaranteed.

A 32-bit RISC microprocessor "V810" that has 5-stage pipeline structure and a 1 Kbyte, direct-mapped instruction cache realizes 2.5 MHz operation at 0.9 V with 2.0 mW power consumption. The supply voltage can be reduced to 0.75 V. To overcome narrow noise margin, all the signals are set to have rail-to-rail swing by pseudo-static circuit technique. The chip is fabricated by a 0.8 µm double metal-layer CMOS process technology to integrate 240,000 transistors on a 7.4 mm7.1 mm die.

Recent advances of processing speed and window systems in computers, especially workstations, accelerate multi-media data processing (MMDP). Then, a variety of data such as numerics, characters, voice, video, animation and so on, are processed concurrently in a workstation. In data processings, concurrent execution of transactions is a key to improve through-puts. However, concurrent execution without concurrency control may cause inconsistent results. Thus, the concurrency control must be introduced in such systems. However, in MMDP it is ineffective to adopt previous concurrency control methods for ordinal databases since multi-media data are huge and possess a real-time property. This paper discusses concurrency control for MMDP. We propose some new concepts for MMDP, and define a new serializability class called Permissible Serializability which provides high concurrency in MMDP compared with ordinal classes. Then, we propose a concurrency control algorithm TYPE for the Permissible Serializability, and show some simulation results.

In this study, we investigate the synchronization phenomena of coupled Wien bridge oscillators. The oscillator is characterized by a voltage controlled resistor with saturation. We use linear resistance to couple the oscillators. Two different kinds of coupling techniques, called current and voltage connections are proposed and they show completely opposite mode of synchronized oscillations. The dynamics of the two circuits are also derived to study the amplitude and phase dynamics of the synchronized state. The current connection has a simple resistive effect but stable phase mode is opposite to that of the voltage connection. The voltage connection has the coupling effect which is a combination of resistive and reactive couplings. Coupled three oscillators with current and voltage connection are also studied and stable tri-phase and in-phase synchronizations are observed, respectively. Averaging method is used to investigate the stability of synchronized mode of oscillations. Experimental results are also stated which agree well with the theory.

It has become more important to reduce the protocol implementation costs as the functions of protocols have become more abundant. The protocol implementation tools which automatically generate a protocol program from a specification described by an FDT (Formal Description Technique) are very promising. Selecting SDL as a target FDT, we have developed an SDL-based protocol implementation tool which consists of a process scheduler and a compiler. Since the efficient SDL process execution is a key to generating the high-speed program, the scheduler is introduced. It provides the mechanism which executes SDL processes concurrently as light-weight-processes. It optimizes so that as few context switches take places as possible. The compiler converts as many kinds of SDL functions whose behaviors can be determined at compile time into programming language statements as possible. These elaborations are so successful that the tool can generate an efficient program. The OSI Transport protocol class 0 program generated by the compiler can process more than 500 packets per second on a 6MIPS workstation.

This paper describes an optimal scheduling approach which finds the scheduling result of the minimum functional unit cost under the given timing constraint. In this method, a well-defined search space is constructed incrementally and traversed in a branch-and-bound manner. During the traversal, tighter lower bounds are estimated and utilized coupled with the upper bound on the optimal solution in pruning the search space effectively. This method is extended to support multi-cycling operations, operation chaining, pipelined functional units, and pipelined data paths. Experimental results on some benchmarks show the efficiency of the proposed approach.

In this paper, bifurcation and chaotic behavior which occur in simple looped MOS inverters with high speed operation are described. The most important point in this work is to change a nonlinear transfer characteristic of a MOS inverter to the nonlinearity generating a chaos. Three types of circuits which include four, three and one MOS inverters, respectively, are proposed. A switched capacitor (SC) circuit to operate sampling holding is added in the loop in each of the circuits. The bifurcation and chaotic behavior have been found along with a variation of an external input, and/or a sampling clock frequency. The bifurcation and chaotic behavior of the proposed simple looped MOS inverters are verified by employing SPICE circuit simulator as well as the experiments. For the first type of four looped CMOS inverters, Lyapunov exponent λ which has the positive regions for the chaotic behavior can be calculated by use of the fitting nonlinear function synthesized from two sigmoid functions. For the second type of three looped CMOS inverters and the third type of one looped MOS inverter, the nonlinear charge/discharge characteristics of the hold capacitor in the SC circuit is utilized efficiently for forming the nonlinearity generating the bifurcation and chaotic behavior. Their bifurcation can be generated by the sampling clock frequency parameter which is controlled easily.

Carrier mobility is one of the most fundamental parameters in semiconductor device modeling, and many mobility models have already been reported. Especially for numerical device simulators, many local models which are functions of impurity concentration and electric field at each local point have been studied. However, concerning their dependence on impurity concentration including carrier screening effects, these models suffer parameter fitting procedure because of their empirical formulation. In such models, carrier screening effects to the Coulomb potential of ionized impurity are not sufficiently considered, although we can find some models which treat the effects as only a small perturbation term. According to the simple theory of Brooks and Herring, carrier screening effects should be included in strong combination with impurity concentration terms and cannot be treated as additional perturbations. Although Brooks-Herring theory is successful, it also suffers from overestimation of the mobility values at concentration higher than 1018 cm-3 which causes some other complicated phenomena. Therefore there have been no models which directly use Brooks-Herring formula. But it is true that such screening effects should be considered when carrier concentration differs from impurity concentration as in the inversion layers of MOSFETs. We have developed a new mobility model for its dependence of impurity and carrier concentration based on the theory of Brooks-Herring. Brooks-Herring theory is based on simple physics of screened Coulomb potential, and therefore makes the model to include effects of free carriers without an artifitial formula. For high doping regime, an additional term has been introduced in Brooks-Herring formula to correct the high doping effects. Except for this term, the model should be most appropriate for including the carrier screening effects upto the concentration of 1018 cm-3. The new model is implimented in a device simulator, and is applied to the evaluation of MOSFETs especially for the universal curves of inversion layer mobility. Moreoever, the applications to the depletion-type MOSFET confirm the validity of the screening effects. The purpose of this paper is to propose the new mobility model and to show its validity through these applications to MOSFETs.

Degradation of metal-oxide-semiconductor field-effect transistors (MOSFETs) reliability such as the relative transconductance reduction by plasma exposure is evaluated. The linear region peak transconductance (gm) decreases with antenna ratio (exposed antenna area/gate area) due to the plasma-induced Si-SiO2 interface state generation. The Si-SiO2 interface-related gm reduction which is defined as (gm0gm)/gm, where gm0 is the initial value of gm, decreases as the gate oxide thickness decreases. It is also found that the decreasing amount of gm depends on the conduction current from the plasma. The correlation between the (gm0gm)/gm and the plasma-induced reduction of charge-to-breakdown of the gate oxide with a constant current stress (ΔQBD) is observed, and the result shows that the gm reduction of nMOSFET during the plasma process is severe to the plasma-induced damage compared with the gate oxide breakdown.

In this paper we describe the formal conditions to detect and resolve all kinds of pipeline data hazards and propose a scheduling algorithm for pipelined instruction set processor synthesis. The algorithm deals with multi cycle operations and tries to minimize the pipeline execution cycles under a given hardware configuration with/without hardware interlock. The main feature that makes the proposed algorithm different from existing ones is the algorithm is for estimating the performance in HW/SW partitioning, with capability of handling a module library of different FUs and dealing with multi cycle operations to be implemented in software. Experimental results of application to ASIP HW/SW codesign show that the proposed algorithm is effective and considerable pipeline execution cycle reduction rates can be achieved. The time complexity of the scheduing algorithm is of O(n2) in the worst case, where n is the number of instructions in a given basic block.

In this paper, we propose the media scheduler employing an adaptive estimator, which uses a posteriori information of data traffic characteristics to facilitate scheduling, when available, to provide on-line scheduling of dynamic scene change based on its statistical characteristics. Especially, a new adaptive scheduling scheme showed good persistent to the arrival message with bursty characteristics. And we confirmed the performance through the computer simulation when QOS requirements are given.

A novel delivery management system using a new lot sampling scheduling (LSS) method has been developed. The method involves the concepts of "virtual line" and "marker lot," and the system consists of an on-line scheduler executing short-period scheduling for lot-tracking and an off-line scheduler executing long-period scheduling for delivery date simulation. The LSS method can hugely increase the maximum number of lots to simulate the delivery date and also control TAT more effectively compared to conventional dynamic scheduling. Lot progress is controlled by varying the resource allocation ratio for each virtual line. This method is effective for precise delivery date control of lots with various priorities in ASIC production or development lines.