We can understand and recover a scene even from a picture or a line drawing. A number of methods have been developed for solving this problem. They have scarcely aimed to deal with scenes of multiple objects although they have ability to recognize three-dimensional shapes of every object. In this paper, challenging to solve this problem, we describe a method for deciding configurations of multiple objects. This method employs the assumption of coplanarity and the constraint of occlusion. The assumption of coplanarity generates the candidates of configurations of multiple objects and the constraint of occlusion prunes impossible configurations. By combining this method with a method of shape recovery for individual objects, we have implemented a system acquirig a three-dimensional information of scene including multiple objects from a monocular image.

The paper discusses properties of YBaCuO thick films produced by screen printing method and followed sintering of a paste made from pre-annealed powder on Yttrium Stabilized Zirconia (YSZ) and MgO substrates. The prepared films have been studied by X-ray diffraction, scanning electron microscopy (SEM) and resistance vs. temperature measurements.

Three-dimensional display technologies that require special glasses are not suitable for telecommunications because wearing glasses is inconvenient and it is defficult to observe facial expressions. Our previous 6.3-inch 3D display was inadequate for presenting images with realistic sensation. In this paper, a direct view 15-inch 3D display is described. The display is made up of a l5-inch TFT LCD and a composite lenticular sheet (LS), and uses the head tracking technique. Quantitative evaluation of the stereoscopic sensation of the display was studied using the 3D display, and better stereoscopic sensation values were obtained compared with a 2D display mode, thus comfirming the display's usefulness.

We report the development of high-performance small-scale AlGaAs/GaAs collector-up heterojunction bipolar transistors (C-up HBT) with a carbon (C)-doped base layer. Oxygen-ion (O+) implantation is used to define their intrinsic emitter/base junctions and zinc (Zn)-diffusion is used to lower the resistivity of their O+-implanted extrinsic base layers. The highly resistive O+-implanted AlGaAs layer in the extrinsic emitter region sufficiently suppresses electron injection even under high-forward-bias conditions, allowing high collector current densities. The use of a C-doped base is especially effective for small-scale C-up HBT's because it suppresses the undesirable turn-on voltage shift caused by base dopant diffusion in the intrinsic area around the collector-mesa perimeter that occurs during the high-temperature Zn-diffusion process after implantation. Even in a small-scale trasistor with a 2 µm2 µm collector, a current gain of 15 is obtained. A microwave transistor with a 2 µm10 µm collector has a cutoff frequency fT of 68 GHz and a maximum oscillation frequency fmax of 102 GHz. A small-scale C-up HBT with a 2 µm2 µm collector shows a higher fmax of 110 GHz due to reduced base/collector capacitance CBC and its fmax remains above 100 GHz, even at a low collector current of 1 mA. The CBC of this device is estimated to be as low as 2.2 fF. Current gain dependence on collector size is also investigated for C-up HBT's and it is found that the base recombination current around the collector-mesa perimeter reduces the current gain.

A Wavelength Division Multiaccess (WDMA) network with buffer sharing among stations is studied. All stations in the network are connected to a passive optical star coupler and each station has a different fixed wavelength laser for transmitting packets. Each station in the network reports its packet backlog to a scheduler which computes and then broadcasts a transmission schedule to all the stations through a control channel in each time slot. A transmission schedule includes two types of assignments: 1) assign a maximum number of stations for conflict-free transmissions, and 2) assign the relocation of packets from congested stations to uncongested relaying stations through idling transceivers for distributed buffer sharing. The first assignment aims at maximizing throughput and the second assignment aims at minimizing packet loss. Simulation results show that as much as 75% of the buffers can be saved with the use of buffer sharing when 50% of the packets are of the non-sequenced type.

This paper propeses a new motion compensation (MC) technique which reduces blurring called drift in moving pictures down-scaled with layered coding system. Encoder of the system compresses large amounts of digital video data in the same way of MPEG (Moving Picture Experts Group) algorithm. Decoder, on the other hand, expands a part of the compressed data and reconstructs down scaled pictures. The purpose of this paper is to reduce blurring which is observed in the reconstructed pictures. In this paper, cause of the blurring is analyzed and the method is introduced as a solution to the problem. The new method is implemented by a little modification of motion compensation (MC) of the decoder, namely increasing the number of tap of interpolation fillters of the MC. Compressing moving pictures, its effectiveness is also confirmed by means of not only subjective test but also signal to noise ratio.

We compare interfaces of Nb/AlOx-Al/Nb and Nb/ZrOx-Zr/Nb junctions using secondary ion mass spectroscopy and cross-sectional transmission electron microscopy. We have clarified that an interface of the Nb/AlOx-Al/Nb junction is drastically different from that of the Nb/ZrOxZr/Nb junction. An adsorbed water vapor layer plays an important role in suppressing grain boundary diffusion between Nb and Al at the interface of the Nb/AlOxAl/Nb junction. In depositing Nb and Al at low power and cooling the substrate, it is important to control the formation of the adsorbed water vapor layer for fabricating Nb/AlOx-Al/Nb junctions exhibiting excellent current-voltage characteristics.

Go-Back-N automatic repeat request (GBN ARQ) and Stop-and wait (SW) ARQ schemes are one of fundamental and widely used error control procedures for data communication and computer communication systems. The throughput and delay performances of these ARQ schemes have been analyzed for a random error channel, which could not applicable for a radio channel, for example. In this paper, considering the correlated, noisy channel, we derive the exact formula for the delay of a frame in GBN and SW ARQ schemes. First, the delay formula for the discrete time M[x]/G/1 queueing system with starter. Next, the virtual service time of a frame is found in terms of the decay factor of a two-state Markov chain. As a result, it is shown that the performance of the delay is improved with the larger decay factor.

In this paper, we proposes a novel fuzzy control for parameter scheduling of the Hopfield neural network. When a combinatorial optimization problem, such as the traveling salesman problem, is solved by Hopfield neural network, it is efficient to adaptively change the parameters of the energy function and sigmoid function. By changing the parameters on purpose, this network can avoid being trapped at a local minima. Since there exists complex relations among these parameters, it is difficult to analytically determine the ideal scheduling. First, we investigate a bad scheduling to change parameters by simple experiments and find several rules that may lead to a good scheduling. The rules extracted from the experimental results are then realized by fuzzy control. By using fuzzy control, we can judge bad scheduling from vague network stages, and then correct the relations among the parameters. Computer simulation results of the Traveling Salesman Problem (TSP) is considered as an example to demonstrate its validity.

This paper proposes a dynamically randomized version of DES (called RDES) in which a input-dependent swapping Sk(X) is added onto the right half of the input in each round of DES. This new scheme decreases the probability of success in differential cryptanalysis because it decreases the characteristic probability. Each "best" two-round characteristic probability is analyzed for typical schemes of the RDES: (i) RDES-1 with a simple one-level swapping, (ii) RDES-1' with an optimal one-level swapping, (iii) RDES-2 with a simple two-level swapping, and (iv) RDES-2' with an optimal two-level swapping. The main results are as follows. (a) The differential attacks on the 16-round RDES-1' and the 16-round RDES-2 require more computational time than the exhaustive search. (b) A differential attack is substantially inapplicable to the 16-round RDES-2' because more than 263 chosen plaintext pairs are required. (c) The encryption/decryption speed of the n-round RDES is almost the same as that of the n-round DES.

Recent achievements in low-voltage and low-power circuit techniques are reported in this paper. DC current in low-voltage CMOS circuits stemming from the subthreshold current in MOS transistors, is effectively reduced by applying switched-power-line schemes. The AC current charging the capacitance in DRAM memory arrays is reduced by a partial activation of array blocks during the active mode and by a charge recycle during the refresh mode. A very-low-power reference-voltage generator is also reported to control the internal chip voltage precisely. These techniques will open the way to using giga-scale LSIs in battery-operated portable equipment.

A new recursive method for obtaining the mean waiting time in a polling system with general service order and gated service discipline is proposed. The analytical approach used to obtain the mean waiting time is via an imbedded Markov chain and a new recursive method is used to obtain the moments of pseudocycle time which are parameters in the formula for the mean waiting time. This method is computationally tractable, so the analytical results can cover a wide range of applications. Simulations are also conducted to verify the validity of the analysis.

An adaptive LMS filtering system is proposed for computing the Discrete Walsh Transform (DWT). The signal to be transformed serves as the 'desired signal' for the adaptive filter, while a set of periodic Walsh sequences serve as the input signal vector for the adaptive filter. The weights of the adaptive filter provide the DWT. The given approach is more efficient in terms of the required computations and memory locations compared with the direct approach. In contract with existing Fast DWT algorithm, the proposed solution provides more flexibility as far as the signal block length is concerned. In other words, the proposed approach is not restricted to a block length N to be of power 2.

The issue about document structure recognition and document understanding is today one of interesting subjects from a viewpoint of practical applications. The research objective is to extract the meaningful data from document images interpretatively and also classify them as the predefined item data automatically. In comparison with the traditional image-processing-based approaches, the knowledge-based approaches, which make use of various knowledge in order to interpret structural/constructive features of documents, have been currently investigated as more flexible and applicable methods. In this paper, we propose a totally integrated paradigm for understanding table-form documents from a viewpoint of the architectural framework.

In this letter, we compare the three compound methods of the Multiple-scale technique to improve the quality of the scale values estimated by the method of fuzzy categories. The results show that the maximum compound method brings higher ability to estimate the scale values than the other methods despite categories used in the scale.

This paper presents a discrete Fourier analyzer using analog VLSI technology. An analog current-mode technique is employed for implementing it by a regular array structure based on the straight-forward discrete Fourier transform (DFT) algorithm. The basic components are 1-dimensional (1-D) analog current-mode multiplier array for fixed coefficient multiplication, two-dimensional (2-D) analog switch array and wired summations. The proposed scheme can process speedily N-point DFT in a time proportional to N. Possibility of the realization of the analog DFT VLSI based on 1 µm technology is discussed from the viewpoints of precision, speed, area, and power dissipation. In the case of 1024-point DFT, the standard deviation of the total error is estimated to be about 2%, the latency, or processing time is about 110 µs, and the signal sample rate based on a pipeline manner is about 4.7 MHz. A prototype MOS integrated circuit of the 16-point multiplier array has been implemented and a typical operation using the multiplier array has been confirmed.

The ultimate minimum energy of switching mechanism for MOS integrated circuits have been studied. This report elucidates the evaluation methods for minimum switching energy of instantaneous discharged mechanism after charging one, namely, recycled energy of the MOS device. Two approaches are implemented to capture this concept. One is a switching energy by the time-dependent gate capacitance (TDGC) model ; the other one by results developed by transient device simulation, which was implemented using Finite Element Method (FEM). It is understood that the non-recycled minimum swhiching energies by both approaches show a good agreement. The recycled energies are then calculated at various sub-micron gate MOS/SOI devices and can be ultra-low power of the MOS integrated circuits, which may be possible to build recycled power circuitry for super energy-saving in the future new MOS LSI. From those results, (1) the TDGC is simultaneously verified by consistent match of the non-recycled minimum switching energies; (2) the recycled switching energy is found to be the ultimate lower bound of power for MOS device; (3) the recycled switching energy can be saved up to around 80% of that of current MOS LSI.

In intelligent integrated systems such as robotics for autonomous work, it is essential to respond to the change of the environment very quickly. Therefore, the development of special-purpose VLSI processors for intelligent integrated systems with small latency becomes an very important subject. In this paper, we present a scheduling algorithm for high-level synthesis. The input to the scheduler is a behavioral description which is viewed as a data flow graph (DFG). The scheduler minimizes the latency, which is the delay of the critical path in the DFG, and minimizes the number of functional units and buses by improving the utilization rates. By using an integer linear programming, the scheduler optimally assigns nodes and arcs in the DFG into steps.

Net theory originated by Dr. Petri in 1962 is now indispensable key concept in the analysis and design of concurrent systems. In Japan, since late seventies the net theory has attracted attention among computer scientists. This paper reviews the historical aspect of the net theory developed in Japan during the last two decades.

This paper proposes a semi-autonomous frame synchronization scheme for a TDMA (Time Division Multiple Access)-TDD (Time Division Duplexing) personal communication system to realize accurate frame synchronization in a simple manner. The proposed scheme selects specific adjacent base stations by the station indicator (SID), carries out high resolution frame timing control, and compensates the propagation delay between base stations by using geographical data. This autonomously synchronizes all base stations to each other. Computer simulation and analysis results confirm the accurate and stable TDMA frame synchronization of all base stations even in fading environments.