Blood pressure measurement by auscultatory method is a compulsory skill that is required by all healthcare practitioners. During the measurement, they must concentrate on recognizing the Korotkoff sounds, looking at the sphygmomanometer scale, and constantly deflating the cuff pressure simultaneously. This complex operation is difficult for the new learners and they need a lot of practice with the supervisor in order to guide them on their measurements. However, the supervisor is not always available and consequently, they always face the problem of lack of enough training. In order to help them mastering the skill of measuring blood pressure by auscultatory method more efficiently and effectively, we propose using a sensor device to capture the signals of Korotkoff sounds and cuff pressure during the measurement, and display the signal changes on a visualization tool through wireless connection. At the end of the measurement, the learners can verify their skill on deflation speed and recognition of Korotkoff sounds using the graphical view, and compare their measurements with the machine instantly. By using this device, the new learners do not need to wait for their supervisor for training but can practice with their colleagues more frequently. As a result, they will be able to acquire the skill in a shorter time and be more confident with their measurements.

In transcoding, it is well known that refinement of the motion vectors is critical to enhance the quality of transcoded video while significantly reducing transcoding complexity. This paper proposes a novel cost model to estimate the rate-distortion cost of motion vector composition in order to develop a reliable motion vector re-estimation method that has reasonable computation cost. Based on a statistical analysis of motion compensated prediction errors, we design a basic form of the proposed cost model as a function of distance from the optimal motion vector. Simulations with a transcoder employing the proposed cost model demonstrate a significant quality gain over representative video transcoding schemes with no complexity increase.

The memory issue plays a very important role for the performance evaluation of a design of 2-Dimensional Discrete Wavelet Transform (2DDWT). A traditional 2DDWT architecture generally needs DRAM to store the input pixel and memory to store temporary results between the row and column processors. In this article, we present a system on a chip (SoC) for video/image processing. The chip integrates an analog-to-digital converter (ADC) with a highly efficient-memory 2DDWT. The latter one contains two main components only: a row processor and a column processor. With this integrated chip plus the use of feedback shift registers (FSR) in the column processor, the architecture we propose can disuse the DRAM and reduce the memory. The pipelined technique is also utilized in the proposed 2DDWT to shorten the critical path to an adder delay. Our architecture outperforms the existing architectures in that it uses less memory size and has low control complexity. It needs only a 2N register instead of a 3.5N register of traditional architectures for a one-level 2DDWT of the 5/3 Lifting-based Discrete Wavelet Transform (LDWT) in an N x N image. Our 2DDWT architecture is coded in VerilogHDL and the Synopsys Design Compiler is employed to synthesize the design with the standard-cell from TSMC 0.18 µm cell library for verification. The ADC is designed by a full-custom methodology, plays as an IP of the SoC. With the integrated SoC, based on the mix-mode design flow, the proposed work requires no external memory, which accordingly reduces the power consumption by memory access and 20 I/O PADs, it also reduces the printed circuit board (PCB) size. Moreover, the proposed SoC supports the resolution of 10 bits and can easily integrate further with the CMOS image sensor (CIS) or other IPs. This, then, completes a single chip and which is ready for a real-time wavelet-based video coding.

Negative electron affinity (NEA) surfaces can be formed by alternating supply of alkali metals (e.g. Cs, Rb, K) and oxygen on semiconductor surfaces. We have studied adsorption structures of Cs on an As-terminated (2×4) (001) GaAs surface using scanning tunneling microscopy (STM). We found that the initial adsorption of Cs atoms occurs around the step sites in the form of Cs clusters and that the size of clusters is reduced by successive exposure to O2, indicating that As-terminated (2×4) surfaces are relatively stable compared to Ga-terminated surfaces and are not broken by the Cs clusters adsorption.

A projective Reed-Muller (PRM) code, obtained by modifying a Reed-Muller code with respect to a projective space, is a doubly extended Reed-Solomon code when the dimension of the related projective space is equal to 1. The minimum distance and the dual code of a PRM code are known, and some decoding examples have been presented for low-dimensional projective spaces. In this study, we construct a decoding algorithm for all PRM codes by dividing a projective space into a union of affine spaces. In addition, we determine the computational complexity and the number of correctable errors of our algorithm. Finally, we compare the codeword error rate of our algorithm with that of the minimum distance decoding.

To improve the performance of capsule endoscope, it is important to add location information to the image data obtained by the capsule endoscope. There is a disadvantage that a lot of existing localization techniques require to measure channel model parameters in advance. To avoid such a troublesome pre-measurement, this paper pays attention to capsule endoscope localization based on an electromagnetic imaging technology which can estimate not only the location but also the internal structure of a human body. However, the electromagnetic imaging with high resolution has huge computational complexity, which should prevent us from carrying out real-time localization. To ensure the accurate real-time localization system without pre-measured model parameters, we apply genetic algorithm (GA) into the electromagnetic imaging-based localization method. Furthermore, we evaluate the proposed GA-based method in terms of the simulation time and the location estimation accuracy compared to the conventional methods. In addition, we show that the proposed GA-based method can perform more accurately than the other conventional methods, and also, much less computational complexity of the proposed method can be accomplished than a greedy algorithm-based method.

The growth of the size of the routing tables limits the scalability of the conventional IP routing. As scalable routing schemes for large-scale networks are highly demanded, this paper proposes and evaluates an efficient geometric routing scheme and related low-cost node design applicable to large-scale networks. The approach guarantees that greedy forwarding on derived coordinates will result in successful packet delivery to every destination in the network by relying on coordinates deduced from a spanning tree of the network. The efficiency of the proposed scheme is measured in terms of routing quality (stretch) and size of the coordinates. The cost of the proposed router is quantified in terms of area complexity of the hardware design and all the evaluations involve comparison with a state-of-the-art approach with virtual coordinates in the hyperbolic plane. Extensive simulations assess the proposal in large topologies consisting of up to 100K nodes. Experiments show that the scheme has stretch properties comparable to geometric routing in the hyperbolic plane, while enabling a more efficient hardware design, and scaling considerably better in terms of storage requirements for coordinate representation. These attractive properties make the scheme promising for routing in large networks.

In this study, we propose a simple, yet general and powerful framework of integrating multiple global and local features by Product Sparse Coding (PSC) for image retrieval. In our framework, multiple global and local features are extracted from images and then are transformed to Trimmed-Root (TR)-features. After that, the features are encoded into compact codes by PSC. Finally, a two-stage ranking strategy is proposed for indexing in retrieval. We make three major contributions in this study. First, we propose TR representation of multiple image features and show that the TR representation offers better performance than the original features. Second, the integrated features by PSC is very compact and effective with lower complexity than by the standard sparse coding. Finally, the two-stage ranking strategy can balance the efficiency and memory usage in storage. Experiments demonstrate that our compact image representation is superior to the state-of-the-art alternatives for large-scale image retrieval.

Low pin-count testing is an effective method to reduce test cost. Based on this method multi-site testing, i.e., where multiple devices are tested concurrently, can be supported under the limitation on the number of channels provided by ATE. In this work we propose a scalable test module (called STM) design that can support multi-site testing more efficiently when compared with previous work. In the previous work, the total number of devices that can be tested concurrently is usually fixed when the design for testability hardware is designed. For our STM, each STM can deal with a number of circuits to be tested at the same time. Moreover, STM is scalable, i.e., multiple STMs can work collaboratively while the ATE bandwidth still remains the same to further increase the degree of test parallelism. Our STM will be integrated with ATE and serve as an interface between ATE and circuits under test (CUT). Only four pins are required by STM to communicate with ATE, and IEEE 1149.1 Std. ports are employed to transfer test data to/from CUTs. STM has been verified via silicon proof, which contains only about 2,768 logic gates. Experiments results for a number of ISCAS and IWLS'05 benchmark circuits also demonstrate that by making good use of the scalable feature of STM, test efficiency can be enhanced significantly.

Out-of-order superscalar processors rename register numbers to remove false dependencies between instructions. A renaming logic for register renaming is a high-cost module in a superscalar processor, and it consumes considerable energy. A renamed trace cache (RTC) was proposed for reducing the energy consumption of a renaming logic. An RTC caches and reuses renamed operands, and thus, register renaming can be omitted on RTC hits. However, conventional RTCs suffer from several performance, energy consumption, and hardware overhead problems. We propose a semi-global renamed trace cache (SGRTC) that caches only renamed operands that are short distance from producers outside traces, and solves the problems of conventional RTCs. Evaluation results show that SGRTC achieves 64% lower energy consumption for renaming with a 0.2% performance overhead as compared to a conventional processor.

The the depth-of-field limitation of our eyes causes out-of-focus blur in the retinal images. The blur dynamically changes whenever we change our gaze and accordingly the scene point we are looking at changes its depth. This paper proposes an image display that reproduces retinal out-of-focus blur by using a stereoscopic display and eye trackers. Its purpose is to provide the viewer with more realistic visual experiences than conventional (stereoscopic) displays. Unlike previous similar systems that track only one of the viewer's eyes to estimate the gaze depth, the proposed system tracks both eyes individually using two eye trackers and estimates the gaze depth from the convergence angle calculated by triangulation. This provides several advantages over existing schemes, such as being able to deal with scenes having multiple depths. We describe detailed implementations of the proposed system and show the results of an experiment conducted to examine its effectiveness. In the experiment, creating a scene having two depths using two LCD displays together with a half mirror, we examined how difficult it is for viewers to distinguish between the real scene and its virtual reproduction created by the proposed display system. The results of the experiment show the effectiveness of the proposed approach.

In this paper we propose an adaptive bitrate (ABR) algorithm that selects the video rates by observing and controlling the playback buffer. In a Hypertext Transfer Protocol (HTTP) adaptive streaming session, buffer dynamics largely depend on the chunk sizes. First, we present the algorithm that selects the next video rates based on the current buffer level, while considering the upcoming chunk sizes. We aim to exploit the variation of chunk sizes of a variable bitrate (VBR) encoded video to optimize the tradeoff between the video rate and buffer underflow events while keeping a low frequency of video rate changes. To evaluate the performance of the proposed algorithm, we consider three scenarios: (i) the video flow does not compete with any cross traffic, (ii) the video flow shares the bottleneck link with competing TCP traffic, and (iii) two HTTP clients share the bottleneck. We show that the proposed algorithm selects a high playback video rate and avoids unnecessary rebuffering while keeping a low frequency of video rate changes. Furthermore, we show that the proposed algorithm changes the video quality gradually to guarantee the user's viewing experience.

We developed an electrically driven near-infrared broadband light source based on self-assembled InAs quantum dots (QDs). By combining emissions from four InAs QD ensembles with controlled emission center wavelengths, electro-luminescence (EL) with a Gaussian-like spectral shape and approximately 85-nm bandwidth was obtained. The peak wavelength of the EL was blue-shifted from approximately 1230 to 1200 nm with increased injection current density (J). This was due to the state-filling effect: sequential filling of the discrete QD electron/hole states by supplied carriers from lower (ground state; GS) to higher (excited state; ES) energy states. The EL intensities of the ES and GS emissions exhibited different J dependence, also because of the state-filling effect. The point-spread function (PSF) deduced from the Fourier-transformed EL spectrum exhibited a peak without apparent side lobes. The half width at half maximum of the PSF was 6.5 µm, which corresponds to the estimated axial resolution of the optical coherence tomography (OCT) image obtained with this light source. These results demonstrate the effectiveness of the QD-based device for realizing noise-reduced high-resolution OCT.

Noise and area consumption has been a trade-off in circuit design. Especially for switched-capacitor filters (SCF), kT/C noise gives a limitation to the minimum value of unit capacitance. In case of SCFs with a large capacitance spread, this limitation will result in a large area consumption due to large capacitors. This paper introduces a technique to reduce capacitance spread using charge scaling. It will be shown that this technique can reduce total capacitance of SCFs without deteriorating their noise performances. A design method to reduce the output noise of SC low-pass filters (LPF) based on the combination of cut-set scaling, charge scaling and adaptive configuration is proposed. The proposed technique can reduce the output noise voltage by 30% for small input signals.

We numerically demonstrated the improvement of single-electron (SE) digital logic gates by utilizing SE input discretizers (IDs). The parameters of the IDs were adjusted to achieve SE tunneling at the threshold voltage designed for switching. An SE four-junction inverter (FJI) with an ID (ID-FJI) had steep switching characteristics between the high and low output voltage levels. The limiting temperature and the critical parameter margins were evaluated. An SE NAND gate with IDs also achieved abrupt switching characteristics between output logic levels.

Dynamic instruction window resizing (DIWR) is a scheme that effectively exploits both memory-level parallelism and instruction-level parallelism by configuring the instruction window size appropriately for exploiting each parallelism. Although a previous study has shown that the DIWR processor achieves a significant speedup, power consumption has not been explored. The power consumption is increased in DIWR because the instruction window resources are enlarged in memory-intensive phases. If the power consumption exceeds the power budget determined by certain requirements, the DIWR processor must save power and thus, the performance previously presented cannot be achieved. In this paper, we explore to what extent the DIWR processor can achieve improved performance for a given power budget, assuming that dynamic voltage and frequency scaling (DVFS) is introduced as a power saving technique. Evaluation results using the SPEC2006 benchmark programs show that the DIWR processor, even with a constrained power budget, achieves a speedup over the conventional processor over a wide range of given power budgets. At the most important power budget point, i.e., when the power a conventional processor consumes without any power constraint is supplied, DIWR achieves a 16% speedup.

Nowadays, the batteryless sensor system is widely used for Internet of things (IoT) system. Especially, batteryless backscatter system has a great significance in that it permits us to communicate without power supply devices. However, conventional backscatter system requires high power reader and this can be a problem with the communication efficiency. Therefore, this letter proposes a new transmission scheme on the batteryless backscatter system in order to solve this problem. In the proposed scheme, the mobile devices which embed Wi-Fi chipset are used as a reader. The tag obtains Internet connectivity from the reader. Since the tag can not decode the general Wi-Fi packet, new algorithm of the scheme uses a specially designed packet. In this letter, the designing method for the decodable packet is proposed. Moreover, the scheme implements beamforming to improve the reliability. By concentrating the power to the designated direction, the robust communication can be achieved. The simulation results show that the proposed scheme offers reliable Internet connectivity without extra battery.

To overcome the privacy limitations of conventional PKI (Public Key Infrastructure) systems, combinatorial certificate schemes assign each certificate to multiple users so that users can perform anonymous authentication. From a certificate pool of N certificates, each user is given n certificates. If a misbehaving user revokes a certificate, all the other users who share the revoked certificate will also not be able to use it. When an honest user shares a certificate with a misbehaving user and the certificate is revoked by the misbehaving user, the certificate of the honest user is said to be covered. To date, only the analysis for the worst scenario has been conducted; the probability that all n certificates of an honest user are covered when m misbehaving users revoke their certificates is known. The subject of this article is the following question: how many certificates (among n certificates) of an honest user are covered on average when m misbehaving users revoke their certificates? We present the first average-case analysis of the cover probability in combinatorial certificate schemes.

In previous papers by the authors, a new scheme for diagnosis of stochastic discrete event systems, called sequence profiling (SP), is proposed. From given event logs, N-gram models that approximate the behavior of the target system are extracted. N-gram models are used for discovering discrepancy between observed event logs and the behavior of the system in the normal situation. However, when the target system is a distributed system consisting of several subsystems, event sequences from subsystems may be interleaved, and SP cannot separate the faulty event sequence from the interleaved sequence. In this paper, we introduce wildcard characters into event patterns. This contributes to removing the effect by subsystems which may not be related to faults.

High structural perfection, wafer uniformity, and reproducibility are key parameters for high-volume, low cost manufacture of resonant tunnelling diode (RTD) terahertz (THz) devices. Low-cost, rapid, and non-destructive techniques are required for the development of such devices. In this paper, we report photoluminescence (PL) spectroscopy as a non-destructive characterisation technique for high current densityInGaAs/AlAs/InP RTD structures grown by metal-organic vapour phase epitaxy (MOVPE) for THz applications. By using a PL line scanning technique across the edge of the sample, we identify characteristic luminescence from the quantum well (QW) and the undoped/n+ InGaAs layers. By using the Moss-Burstein effect, we are able to measure the free-electron concentration of the emitter/collector and contact layers in the RTD structure. Whilst the n+ InGaAs luminescence provides information on the doping concentration, information on the alloy composition and compositional variation is extracted from the InGaAs buffer layer. The QW luminescence provides information on the average well width and provides a monitor of the structural perfection with regard to interface and alloy disorder.