In this paper, we propose periodic and aperiodic security limits for compromising emanations in the VHF and UHF bands. First, we perform the electromagnetic emanation security (EMSEC)-channel measurements in the 200-1000MHz frequency bands. Second, we analyse the pathloss characteristics of the indoor EMSEC-channel based on these measurements. Through this EMSEC-channel analysis, we affirm that the total radio attenuation, which is one of the key parameters for determining the security limits for compromising emanations, follows the Rician distribution. With these results, we propose that periodic and aperiodic emission security limits can be classified into two levels depending on the total radio attenuation and the extent of required confidentiality. The proposed security limits are compared with other security limits and existing civil and military EMC standards.

This paper presents an efficient implementation of OFDM inner receiver on a programmable multi-core processor platform with CMMB as an application. The platform consists of an array of programmable SIMD processors interconnected in a 2-D mesh network, which can provide high performance and is quite suitable for wireless communication applications. Implemented on one cluster with 8 cores, the receiver includes symbol timing, carrier frequency offset and sampling frequency offset synchronization, channel estimation and equalization. Multiple optimization techniques are explored to improve system throughput such as: task-level parallelism on many cores, data-level parallelism on SIMD cores, minimization of memory access and route-length-minimization task mapping techniques. Besides, efficient memory strategy and specific instructions for complex computation increase the performance. The simulation results show that the inner receiver could achieve a throughput of up to 120 Mbps when operating at 750 MHz.

The hierarchical multi-function matrix operation (MFMO) circuit modules are designed using coordinate rotations digital computer (CORDIC) algorithm for realizing the intensive computation of matrix operations. The paper emphasizes that the designed hierarchical MFMO circuit modules can be used to develop a power-efficient software-defined radio (SDR) digital beamformer (DBF). The formulas of the processing time for the scalable MFMO circuit modules implemented in field programmable gate array (FPGA) are derived to allocate the proper logic resources for the hardware reconfiguration. The hierarchical MFMO circuit modules are scalable to the changing number of array branches employed for the SDR DBF to achieve the purpose of power saving. The efficient reuse of the common MFMO circuit modules in the SDR DBF can also lead to energy reduction. Finally, the power dissipation and reconfiguration function in the different modes of the SDR DBF are observed from the experiment results.

In the arsenal of resources for improving computer memory system performance, predictors have gained an increasing role in the past few years. They enable hiding the latencies when accessing cache or main memory. In our previous work we proposed a DDR SDRAM controller with predictors that not only close the opened DRAM row but also predict the next row to be opened. In this paper we explore the possibilities of trying the same techniques on the latest type of DRAM memory, DDR3 SDRAM, with further improvements of the predictors.

We present an attractive approach for OFDM transmission using an adaptive pre-FFT equalizer, which can select ICI reduction mode according to channel condition, and a degenerated-inverse-matrix-based channel estimator (DIME), which uses a cyclic sinc-function matrix uniquely determined by transmitted subcarriers. In addition to simulation results, the proposed system with an adaptive pre-FFT equalizer and DIME has been laboratory tested by using a software defined radio (SDR)-based test bed. The simulation and experimental results demonstrated that the system at a rate of more than 100 Mbps can provide a bit error rate of less than 10-3 for a fast multi-path fading channel that has a moving velocity of more than 200 km/h with a delay spread of 1.9 µs (a maximum delay path of 7.3 µs) in the 5-GHz band.

This paper proposes an enhanced method for estimating the a priori Signal-to-Disturbance Ratio (SDR) to be employed in the Acoustic Echo and Noise Suppression (AENS) system for full-duplex hands-free communications. The proposed a priori SDR estimation technique is modified based upon the Two-Step Noise Reduction (TSNR) algorithm to suppress the background noise while preserving speech spectral components. In addition, a practical approach to determine accurately the Echo Spectrum Variance (ESV) is presented based upon the linear relationship assumption between the power spectrum of far-end speech and acoustic echo signals. The ESV estimation technique is then employed to alleviate the acoustic echo problem. The performance of the AENS system that employs these two proposed estimation techniques is evaluated through the Echo Attenuation (EA), Noise Attenuation (NA), and two speech distortion measures. Simulation results based upon real speech signals guarantee that our improved AENS system is able to mitigate efficiently the problem of acoustic echo and background noise, while preserving the speech quality and speech intelligibility.

In this paper, we have shown a major element occupying the large portion of software communications architecture (SCA)-based software defined radio (SDR) handheld embedded system and an important feature for implementing a high speed broadband radio to an SCA waveform through a couple of experiments. First, this paper identifies the main items possessing the large portion of SCA-based SDR handheld embedded system by the experiment on the target platform which is similar to a commercial mobile handheld system. Both the world interoperabillity for microwave access (WiMAX) and high speed downlink packet access (HSDPA) waveform software packages are used as an SCA waveform application. This paper also presents the results of the relative binary size distribution of SCA software resources for looking for the major elements making an SCA-based SDR handheld embedded system heavier. As a result, when focusing on the relative weight portion of SCA core framework (CF), the SCA CF takes 16% up and others have 84% out of the whole binary size distribution of SCA software resources. The results of the experiment give us notice that the weight portion of SCA CF is minor and compatible with the overall software binary size needs of an SCA-based SDR handheld embedded system, on the other hand, the practical problem on the lightweight is in a common object request broker architecture (CORBA) and extensible markup language (XML) parser resources. Second, this paper describes an important feature for implementing a high speed broadband radio to an SCA waveform and presents the performance evaluation results of the SCA port communication on both power PC (PPC) 405 and x86 processor platforms. The PPC 405 platform, which is similar to a commercial mobile handset, takes the value of average round trip time (RTT) with a maximum of thirty six millisecond. The x86 platform, however, which is analogous to a server platform, maintains stable micro-second resolution. From our experiments, we observe that rapid SCA port communication, sufficiently less than the frame length of high-speed broadband radios, should be provided for serving those radio services in a commercial handheld system based on the SCA.

In this letter, we propose a cache organization that substantially reduces the memory bandwidth of motion compensation (MC) in the H.264/AVC decoders. To reduce duplicated memory accesses to P and B pictures, we employ a four-way set-associative cache in which its index bits are composed of horizontal and vertical address bits of the frame buffer and each line stores an 8 2 pixel data in the reference frames. Moreover, we alleviate the data fragmentation problem by selecting its line size that equals the minimum access size of the DDR SDRAM. The bandwidth of the optimized cache averaged over five QCIF IBBP image sequences requires only 129% of the essential bandwidth of an H.264/AVC MC.

In this paper, a new fractional sample rate conversion (SRC) scheme based on a direct insertion/cancellation scheme is proposed. This scheme is suitable for signals that are sampled at a high sample rate and converted to a lower sample rate. The direct insertion/cancellation scheme may achieve low-complexity and lower power consumption as compared to the other SRC techniques. However, the direct insertion/cancellation technique suffers from large aliasing and distortion. The aliasing from an adjacent channel interferes the desired signal and degrades the performance. Therefore, a modified direct insertion/cancellation scheme is proposed in order to realize high performance resampling.

It is well known that there is relationship between electromagnetic emanation and processing information in IT devices such as personal computers and smart cards. By analyzing such electromagnetic emanation, eavesdropper will be able to get some information, so it becomes a real threat of information security. In this paper, we show how to estimate amount of information that is leaked as electromagnetic emanation. We assume the space between the IT device and the receiver is a communication channel, and we define the amount of information leakage via electromagnetic emanations by its channel capacity. By some experimental results of Tempest, we show example estimations of amount of information leakage. Using the value of channel capacity, we can calculate the amount of information per pixel in the reconstructed image. And we evaluate the effectiveness of Tempest fonts generated by Gaussian method and its threshold of security.

This letter evaluates a transmitter architecture using harmonic images in D/A conversion for generating RF signals. In generating harmonic images, the problems such as intermodulation distortion of DAC were investigated. We developed an evaluation system with two bandpass filter and a buffer amplifier. It was experimentally found that the RF signal up to around 400 MHz can be generated by a commonly used 14-bit DAC at the sampling rates of around 40 MHz with EVM less than 6.6%. This letter also presents a more feasible transmitter example having an IF stage with harmonic image extraction scheme and a typical RF upconversion stage.

FPGA-based hardware emulators are often used for the verification of LSI functions. They generally have dedicated external memories, such as SDRAMs, to compensate for the lack of memory capacity in FPGAs. In such a case, access between the FPGAs and the dedicated external memory may represent a major bottleneck with respect to emulation speed since the dedicated external memory may have to emulate a large number of memory blocks. In this paper, we propose three methods, "Dynamic Clock Control (DCC)," "Memory Mapping Optimization (MMO)," and "Efficient Access Scheduling (EAS)," to avoid this bottleneck. DCC controls an emulation clock dynamically in accord with the number of memory accesses within one emulation clock cycle. EAS optimizes the ordering of memory access to the dedicated external memory, and MMO optimizes the arrangement of the dedicated external memory addresses to which respective memories will be emulated. With them, emulation speed can be made 29.0 times faster, as evaluated in actual LSI emulations.

It has been shown that the output information produced by the soft output Viterbi algorithm (SOVA) is too optimistic. To compensate for this, the output information should be normalized. This letter proposes a simple normalization technique that extends the existing sign difference ratio (SDR) criterion. The new normalization technique counts the sign differences between the a-priori information and the extrinsic information, and then adaptively determines the corresponding normalization factor for each data block. Simulations comparing the new technique with other well-known normalization techniques show that the proposed normalization technique can achieve about 0.2 dB coding gain improvement on average while reducing up to about 1/2 iteration for decoding.

A multiple-input multiple-output software defined radio (MIMO-SDR) platform was developed for implementation of MIMO transmission and propagation measurement systems. This platform consists of multiple functional boards for baseband (BB) digital signal processing and frequency conversion of 5 GHz-band radio frequency (RF) signals. The BB boards have capability of arbitrary system implementation by rewriting software on reconfigurable devices such as field programmable gate arrays (FPGAs) and digital signal processors (DSPs). The MIMO-SDR platform employs hybrid implementation architecture by taking advantages of FPGA, DSP, and CPU, where functional blocks with the needs for real-time processing are implemented on the FPGAs/DSPs, and other blocks are processed off-line on the CPU. In order to realize the hybrid implementation, driver software was developed as an application program interface (API) of the MIMO-SDR platform. In this paper, hardware architecture of the developed MIMO-SDR platform and its software implementation architecture are explained. As an application example, implementation of a real-time MIMO channel measurement system and initial measurement results are presented.

A coplanar type lumped-element 6-pole microwave Chebyshev bandpass filter (BPF) of center frequency (f0) 2.0 GHz and fractional bandwidth (FBW) 1.0 % was designed. For the design method, theory of direct coupled resonator filters using K-inverters was employed. Coplanar type lumped-element BPFs are composed of a meander-line L and interdigital C elements. The frequency response was simulated and analyzed using an electromagnetic field simulator (Sonnet-EM). Further, the changes in f0 and FBW of the BPF were also realized by the mechanical tuning method.

This letter describes an efficient architecture for a Software Defined Radio (SDR) Wideband Code Division Multiple Access (WCDMA) receiver using for high performance wireless communication systems. The architecture is composed of a Radio Frequency (RF) front-end, an Analog-to-Digital Converter (ADC), and a Quadrature Amplitude Modulation (QAM) demodulator. A coherent demodulator, with a complete digital synchronization scheme, achieves the bit-error rate (BER) of 10-6 with the implementation loss of 0.5 dB for a raw Quadrature Phase Shift King (QPSK) signal.

The objectives of the End-to-End Reconfigurability (E2R) research project are to bring the full benefits of the valuable diversity within the radio eco-space, composed of a wide range of systems (such as cellular, wireless local area and broadcast), and to devise, develop and trial architectural design of reconfigurable devices and supporting system functions to offer an expanded set of operational choices to the different actors of the value chain in the context of heterogeneous mobile radio systems. The E2R project will help operators to better exploit their investments on infrastructures and terminals and ensure that the infrastructure will be flexible and reconfigurable to accommodate evolving standards, applications and the end-user needs. E2R is seen by many actors of the wireless industry as a core technology to enable the full potential of beyond 3G systems. It has the potential to revolutionize wireless just as the PC revolutionized computing. This paper presents the E2R research project, its architectural framework and approach, the main fields of investigations across the different technical workpackages in 2005, as well as the E2R Phase 2 project proposal ambitions (2006-2007).

Recently, a number of techniques have been introduced to exploit multiuser diversity of a wireless multiple-input multiple-output (MIMO) broadcast channel (BC) that consists of a base station with t transmit antennas and K users with multiple antennas. However, prior works have ignored the rate overhead associated with feedback of MIMO BC channel state information at transmitter (CSIT), which is roughly K times larger than single-user MIMO CSIT (i.e., it is O(tr) where r = rk and rk is the number of antennas at the kth user). Considering the amount of feedback signaling, quantization is a necessity for effective feedback transmission as a form of partial CSIT. In this paper, we propose the greedy multi-channel selection diversity (greedy MCSD) scheme based on block MMSE QR decomposition with dirty paper coding (block MMSE-DP), where partial CSIT is almost sufficient. The sum-rate performance of our novel scheme approaches extremely close to the sum capacity of MIMO BC as the number of users increases, whereas the feedback overhead is reduced by a factor of 2t3/L(t2-t), in which L is the number of active channel vectors. Simulation results validate the expectation from the analysis. In addition, the proposed scheme is shown to be appropriate for reconfigurable implementation.

A very long instruction word (VLIW) digital signal processor (DSP), called ODiN, which could execute six instructions in a single cycle simultaneously, is designed and fabricated using 0.25 µm 1-ploy 5-metal standard cell static CMOS process. The ODiN core delivers maximum 600 MIPS with 100 MHz system clock. In order to achieve high performance operation, the designed core includes compact register files, orthogonal instruction set, single cycle operations for most instructions, and parallel processing based on software scheduling. In addition, a Viterbi decoder processor and a FFT processor that are embedded make it possible to implement software defined radio (SDR) applications efficiently.

A CMOS DFE (decision feedback equalization) receiver with a clock-data skew compensation was implemented for the SSTL (stub-series terminated logic) SDRAM interface. The receiver consists of a 2 way interleaving DFE input buffer for ISI reduction and a X2 over-sampling phase detector for finding the optimum sampling clock position. The measurement results at 1.2 Gbps operation showed the increase of voltage margin by about 20% and the decrease of time jitter in the recovered sampling clock by about 40% by equalization in an SSTL channel with 2 pF 4 stub load. Active chip area and power consumption are 3001000 µm2 and 142 mW, respectively, with a 2.5 V, 0.25 µm CMOS process.