In this letter we proposed the linear combination of two ISI-free pulses with different decay rates in order to obtain a new Nyquist pulse. The proposed pulse contains a new design parameter β, giving an additional degree of freedom to minimize the bit error probability performance in the presence of symbol-timing errors, for a given roll-off factor α. Several practical tools are implemented for evaluating the performance of the proposed filter. The novel pulse is evaluated in terms of the bit error probability performance in the presence of symbol-timing errors. Eye diagrams are presented to visually assess the vulnerability of the transmission system to ISI, and the maximum distortion is estimated as a quantitative measure of performance.

To obtain an ultra-short high-intensity pulse source, we investigated the amplification characteristics of two types of pulses (dissipative soliton and stretched pulses) produced by our Yb-doped fiber laser oscillator. Our results show that the dissipative soliton pulse can be amplified with less deterioration than the stretched pulse.

The design and measured results of a 120 GHz/140 GHz dual-channel OOK (ON-OFF Keying) receiver are presented in this paper. Because a signal with very wide frequency width is difficult to process in a single-channel receiver, a dual-channel configuration with channel selection is adopted in the proposed receiver. The proposed receiver is fabricated using 65 nm CMOS technology. The measured data rate of 3.0 and 3.6 Gbps, minimum sensitivity of -25.6 and -27.1 dBm, communication distance of 0.30 and 0.38 m are achieved in the 120- and 140-GHz receiver, respectively. The correct channel selection is achieved in the 120-GHz receiver. These results indicate the possibility of the CMOS multiband receiver operating at over 100 GHz for low-power high-speed proximity wireless communication systems.

In our privious paper, we proposed an algorithm that determines delay times of a timed Petri net from the structural information of a signaling pathway, but Petri net structures containing cycles and inhibitory arcs were not considered. This paper provides conditions for cycle-contained Petri nets to have reasonable delay times. Furthermore, handling of inhibitory arcs are discussed in terms of the reaction rate of inhibitory interaction in signaling pathway, especially the conversion process of Petri net with inhibitory arc to the one without inhibitory arc is given.

With appropriate geometry configurations, bistatic Synthetic Aperture Radar (SAR) can break through the limitations of monostatic SAR for forward-looking imaging. Thanks to such a capability, bistatic forward-looking SAR (BFSAR) has extensive potential applications. This paper develops a frequency-domain imaging algorithm for translational invariant BFSAR. The algorithm uses the method of Lengendre polynomials expansion to compute the two dimensional point target reference spectrum, and this spectrum is used to perform the range cell migration correction (RCMC), secondary range compression and azimuth compression. In particular, the Doppler-centroid and bistatic-range dependent interpolation for residual RCMC is presented in detail. In addition, a method that combines the ambiguity and resolution theories to determine the forward-looking imaging swath is also presented in this paper.

We report a 40-Gb/s and highly accurate intensity limiter with a single Erbium-Doped Fiber Amplifier (EDFA) for low-power-consumption driving intensity limiting. The intensity limiter based on self-phase modulation with an appropriate pre-chirping procedure makes it possible, which provides a highly accurate limiting of less than 0.01 dB. We fed 40-Gb/s signals with 2.69 dB intensity fluctuation and 4.7 dB improvement on the receiver sensitivity was obtained for a bit error rate of 10-9 by using a numerical simulation.

Automatic vessel tortuosity measures are crucial for many applications related to retinal diseases such as those due to retinopathy of prematurity (ROP), hypertension, stroke, diabetes and cardiovascular diseases. An automatic evaluation and quantification of retinal vascular tortuosity would help in the early detection of such retinopathies and other systemic diseases. In this paper, we propose a novel tortuosity index based on principal component analysis. The index is compared with three existant indices using simulated curves and real retinal images to demonstrate that it is a valid indicator of tortuosity. The proposed index satisfies all the tortuosity properties such as invariance to translation, rotation and scaling and also the modulation properties. It is capable of differentiating the tortuosity of structures that visually appear to be different in tortuosity and shapes. The proposed index can automatically classify the image as tortuous or non tortuous. For an optimal set of training parameters, the prediction accuracy is as high as 82.94% and 86.6% on 45 retinal images at segment level and image level, respectively. The test results are verified against the judgement of two expert Ophthalmologists. The proposed index is marked by its inherent simplicity and computational attractiveness, and produces the expected estimate, irrespective of the segmentation approach. Examples and experimental results demonstrate the fitness and effectiveness of the proposed technique for both simulated curves and retinal images.

Experiments usually aim to study how changes in various factors affect the response variable of interest. Since the response model used most often at present in experimental design is expressed through the effect of each factor, it is straightforward to ascertain how each factor affects the response variable. However, since the response model contains redundant parameters, in the analysis of variance we must calculate the degrees of freedom defined by the number of independent parameters. In this letter, we propose the idea of calculating the degrees of freedom over the model based on an orthonormal system for the first time. In this way, we can easily obtain the number of independent parameters associated with any component, which reduces the risk of mistakes in the calculation of the number of independent parameters and facilitates the implementation of estimation procedures.

Numerous examples in image processing have demonstrated that human visual perception can be exploited to improve processing performance. This paper presents another showcase in which some visual information is employed to guide adaptive block-wise compressive sensing (ABCS) for image data, i.e., a varying CS-sampling rate is applied on different blocks according to the visual contents in each block. To this end, we propose a visual analysis based on the discrete cosine transform (DCT) coefficients of each block reconstructed at the decoder side. The analysis result is sent back to the CS encoder, stage-by-stage via a feedback channel, so that we can decide which blocks should be further CS-sampled and what is the extra sampling rate. In this way, we can perform multiple passes of reconstruction to improve the quality progressively. Simulation results show that our scheme leads to a significant improvement over the existing ones with a fixed sampling rate.

In this paper, we propose a high-speed full-duplex optical wireless communication system using a single channel imaging receiver for personal area network applications. This receiver is composed of an imaging lens, a small sensitive-area photodiode, and a 2-aixs actuator and it can reject most of the background light. Compared with the previously proposed system with single wide field-of-view (FOV) non-imaging receiver, the coverage area at 12.5 Gb/s is extended by > 20%. Furthermore, since the rough location information of the user is available in our proposed system, instead of searching for the focused light spot over a large area on the focal plane of the lens, only a small possible area needs to be scanned. In addition, by pre-setting a proper comparison threshold when searching for the focused light spot, the time needed for searching can be further reduced. Proof-of-concept experiments have been carried out and the results show that with this partial searching algorithm and pre-set threshold, better performance is achieved.

A timed Petri net, an extended model of an ordinary Petri net with introduction of discrete time delay in firing activity, is practically useful in performance evaluation of real-time systems and so on. Unfortunately though, it is often too difficult to solve (efficiently) even most basic problems in timed Petri net theory. This motivates us to do research on analyzing complexity of Petri net problems and on designing efficient and/or heuristic algorithms. The minimum initial marking problem of timed Petri nets (TPMIM) is defined as follows: “Given a timed Petri net, a firing count vector X and a nonnegative integer π, find a minimum initial marking (an initial marking with the minimum total token number) among those initial ones M each of which satisfies that there is a firing scheduling which is legal on M with respect to X and whose completion time is no more than π, and, if any, find such a firing scheduling.” In a production system like factory automation, economical distribution of initial resources, from which a schedule of job-processings is executable, can be formulated as TPMIM. The subject of the paper is to propose two pseudo-polynomial time algorithms TPM and TMDLO for TPMIM, and to evaluate them by means of computer experiment. Each of the two algorithms finds an initial marking and a firing sequence by means of algorithms for MIM (the initial marking problem for non-timed Petri nets), and then converts it to a firing scheduling of a given timed Petri net. It is shown through our computer experiments that TPM has highest capability among our implemented algorithms including TPM and TMDLO.

We propose a novel technique for the estimation of device-parameters suitable for postfabrication performance compensation and adaptive delay testing, which are effective means to improve the yield and reliability of LSIs. The proposed technique is based on Bayes' theorem, in which the device-parameters of a chip, such as the threshold voltage of transistors, are estimated by current signatures obtained in a regular IDDQ testing framework. Neither additional circuit implementation nor additional measurement is required for the purpose of parameter estimation. Numerical experiments demonstrate that the proposed technique can achieve 10-mV accuracy in threshold voltage estimations.

This paper presents an efficient approach for logarithmic and anti-logarithmic converters which can be used in the arithmetic unit of hybrid number system processors and logarithm/exponent function generators in DSP applications. By employing the novel quasi-symmetrical difference method with only the simple shift-add logic and the look-up table, the proposed approach can reduce the hardware area and improve the conversion speed significantly while achieve similar accuracy compared with the previous methods. The implementation results in both FPGA and 0.18-µm CMOS technology are also presented and discussed.

This paper presents a power analysis that applies to elliptic curves over generalized Mersenne prime field Fp. This prime field enables efficient modular reductions which influence the computational performance of an elliptic curve cryptosystem. The general modular reductions stochastically calculate extra operations. Some studies showed the possibility of power analysis attacks to scalar multiplication with a unified code by using the statistical information of extra operations. In this paper, we present the statistical experiment and possibility of attacks, and propose the more sensitive attack and the countermeasure without performance impact.

Reversible data hiding has been a hot research topic since both the host media and hidden data can be recovered without distortion. In the past several years, more and more attention has been paid to reversible data hiding schemes for images in compressed formats such as JPEG, JPEG2000, Vector Quantization (VQ) and Block Truncation Coding (BTC). Traditional data hiding schemes in the BTC domain modify the BTC encoding stage or BTC-compressed data according to the secret bits, and they have no ability to reduce the bit rate but may reduce the image quality. This paper presents a novel reversible data hiding scheme for BTC-compressed images by further losslessly encoding the BTC-compressed data according to the secret bits. First, the original BTC technique is performed on the original image to obtain the BTC-compressed data which can be represented by a high mean table, a low mean table and a bitplane sequence. Then, the proposed reversible data hiding scheme is performed on both the high mean table and low mean table. Our hiding scheme is a lossless joint hiding and compression method based on 22 blocks in mean tables, thus it can not only hide data in mean tables but also reduce the bit rate. Experiments show that our scheme outperforms three existing BTC-based data hiding works, in terms of the bit rate, capacity and efficiency.

Sequence diagrams are often used in the modular design of softwares. In this paper, we propose a method to verify correctness of sequence diagrams. With this method, using the process algebra CSP, concurrent systems can be synthesized from a number of sequence diagrams. We define new CSP operators for the synthesis of sequence diagrams. We also report on a tool implementing our synthesis method and demonstrate how the tool analyzes sequence diagrams.

In our previous study, we proposed the waveform interpolation (WI) approach to model the excitation signals for hidden Markov model (HMM)-based speech synthesis. This letter presents several techniques to improve excitation modeling within the WI framework. We propose both the time domain and frequency domain zero padding techniques to reduce the spectral distortion inherent in the synthesized excitation signal. Furthermore, we apply non-negative matrix factorization (NMF) to obtain a low-dimensional representation of the excitation signals. From a number of experiments, including a subjective listening test, the proposed method has been found to enhance the performance of the conventional excitation modeling techniques.

This paper presents a wide range in supply voltage, resolution, and sampling rate asynchronous successive approximation register (SAR) analog-to-digital converter (ADC). The proposed differential flip-flop in SAR logic and high efficiency wide range delay element extend the flexibility of speed and resolution tradeoff. The ADC fabricated in 40 nm CMOS process covers 4–10 bit resolution and 0.4–1 V power supply range. The ADC achieved 49.8 dB SNDR and the peak FoM of 3.4 fJ/conv. with 160 kS/sec at 0.4 V single power supply voltage. At 10 bit mode and 1 V operation, up to 10 MS/s, the FoM is below 10 fJ/conv. while keeping ENOB of 8.7 bit.

Chip Multiprocessors (CMPs) allow different applications to share LLC (Last Level Cache). Since each application has different cache capacity demand, LLC capacity should be partitioned in accordance with the demands. Existing partitioning algorithms estimate the capacity demand of each core by stack processing considering the LRU (Least Recently Used) replacement policy only. However, anti-thrashing replacement algorithms like BIP (Binary Insertion Policy) and BIP-Bypass emerged to overcome the thrashing problem of LRU replacement policy in a working set greater than the available cache size. Since existing stack processing cannot estimate the capacity demand with anti-thrashing replacement policy, partitioning algorithms also cannot partition cache space with anti-thrashing replacement policy. In this letter, we prove that BIP replacement policy is not feasible to stack processing but BIP-bypass is. We modify stack processing to accommodate BIP-Bypass. In addition, we propose the pipelined hardware of modified stack processing. With this hardware, we can get the success function of the various capacities with anti-thrashing replacement policy and assess the cache capacity of shared cache adequate to each core in real time.

A multigate polycrystalline-silicon (poly-Si) thin-film transistor (TFT) is a recently popular topic in the field of Si devices. In this study, self-aligned planar metal double-gate poly-Si TFTs consisting of an embedded bottom metal gate, a top metal gate fabricated by a self-alignment process, and a lateral poly-Si film with a grain size greater than 2 µm were fabricated on a glass substrate at 550. The nominal field-effect mobility of an n-channel TFT is 530 cm2/Vs, and its subthreshold slope is 140 mV/dec. The performance of the proposed TFTs is superior to that of top-gate TFTs fabricated using equivalent processes.