A method of calculating the exact top event probability of a fault tree with dynamic gates and repeated basic events is proposed. The top event probability of such a dynamic fault tree is obtained by converting the tree into an equivalent Markov model. However, the Markov-based method is not realistic for a complex system model because the number of states that should be considered in the Markov analysis increases explosively as the number of basic events in the model increases. To overcome this shortcoming, we propose an alternative method in this paper. It is a hybrid of a Bayesian network (BN) and an algebraic technique. First, modularization is applied to a dynamic fault tree. The detected modules are classified into two types: one satisfies the parental Markov condition and the other does not. The module without the parental Markov condition is replaced with an equivalent single event. The occurrence probability of this event is obtained as the sum of disjoint sequence probabilities. After the contraction of modules without parent Markov condition, the BN algorithm is applied to the dynamic fault tree. The conditional probability tables for dynamic gates are presented. The BN is a standard one and has hierarchical and modular features. Numerical example shows that our method works well for complex systems.

The application of information hiding to image compression is investigated to improve compression efficiency for JPEG color images. In the proposed method, entropy-coded DCT coefficients of chrominance components are embedded into DCT coefficients of the luminance component. To recover an image in the face of the degradation caused by compression and embedding, an image restoration method is also applied. Experiments show that the use of both information hiding and image restoration is most effective to improve compression efficiency.

Automatic modulation classification (AMC) is an important function of radio surveillance systems in order to identify unknown signals. Many previous works on AMC have utilized signal cyclostationarity, particularly spectral correlation density (SCD), but many of them fail to address several implementation issues, such as the assumption of perfect knowledge of the symbol rate. In this paper, we discuss several practical issues, e.g. cyclic frequency mismatch, which may affect the SCD, and propose compensation techniques to overcome those issues. We also propose a novel feature extraction technique from the SCD, which utilizes the SCD of not only the original received signal, but also the squared received signal. A symbol rate estimation technique which complements the feature extraction is also proposed. Finally, the classification performance of the system is evaluated through Monte Carlo simulations using a wide variety of modulated signals, and simulation results show that the proposed technique can estimate the symbol rate and classify modulation with a probability of above 0.9 down to SNRs of 5 dB.

The trench-gate type high-voltage (HV) MOSFET is one of the variants of HV-MOSFET, typically with its utility segments lying on a larger power consumption domain, compared to planar HV-MOSFETs. In this work, the HiSIM_HV compact model, originally intended for planar LDMOSFETs, was adequately extended to accommodate trench-gate type HV-MOSFETs. The model formulation focuses on a closed-form description of the current path in the highly resistive drift region, specific to the trench-gate HV-MOSFETs. It is verified that the developed compact expression can capture the conductivity in the drift region, which varies with voltage bias and device technology such as trench width. The notable enhancement of current drivability can be accounted for by the electrostatic control exerted by the trench gate within the framework of this model.

We propose a novel threshold-free salient object detection approach which integrates both saliency density and edge response. The salient object with a well-defined boundary can be automatically detected by our approach. Saliency density and edge response maximization is used as the quality function to direct the salient object discovery. The global optimal window containing a salient object is efficiently located through the proposed saliency density and edge response based branch-and-bound search. To extract the salient object with a well-defined boundary, the GrabCut method is applied, initialized by the located window. Experimental results show that our approach outperforms the methods only using saliency or edge response and achieves a comparable performance with the best state-of-the-art method, while being without any threshold or multiple iterations of GrabCut.

First, this paper derives the prefix sum-of-products expression (PreSOP) and the number of products in a PreSOP for an interval function. Second, it derives Ψ(n,τp), the number of n-variable interval functions that can be represented with τp products. Finally, it shows that more than 99.9% of the n-variable interval functions can be represented with ⌈ n - 1 ⌉ products, when n is sufficiently large. These results are useful for a fast PreSOP generator and for estimating the size of ternary content addressable memories (TCAMs) for packet classification.

An SiO2/Si-cap/Si0.55Ge0.45 heterostructure was fabricated on p-type Si(100) and strained silicon on insulator (SOI) substrates by low pressure chemical vapor deposition (LPCVD) and subsequent thermal oxidation in an O2 + H2 gas mixture. Chemical bonding features and valence band offsets in the heterostructures were evaluated by using high-resolution x-ray photoelectron spectroscopy (XPS) measurements and thinning the stack layers with a wet chemical solution.

With the rapid expansion of vector data model application to digital content such as drawings and digital maps, the security and retrieval for vector data models have become an issue. In this paper, we present a vector data-hashing algorithm for the authentication, copy protection, and indexing of vector data models that are composed of a number of layers in CAD family formats. The proposed hashing algorithm groups polylines in a vector data model and generates group coefficients by the curvatures of the first and second type of polylines. Subsequently, we calculate the feature coefficients by projecting the group coefficients onto a random pattern, and finally generate the binary hash from binarization of the feature coefficients. Based on experimental results using a number of drawings and digital maps, we verified the robustness of the proposed hashing algorithm against various attacks and the uniqueness and security of the random key.

This paper presents link analysis based on rhetorical relations with the aim of performing extractive summarization for multiple documents. We first extracted sentences with salient terms from individual document using statistical model. We then ranked the extracted sentences by measuring their relative importance according to their connectivity among the sentences in the document set using PageRank based on the rhetorical relations. The rhetorical relations were examined beforehand to determine which relations are crucial to this task, and the relations among sentences from documents were automatically identified by SVMs. We used the relations to emphasize important sentences during sentence ranking by PageRank and eliminate redundancy from the summary candidates. Our framework omits fully annotated sentences by humans and the evaluation results show that the combination of PageRank along with rhetorical relations does help to improve the quality of extractive summarization.

A variety of ubiquitous computing devices, such as radio frequency identification (RFID) and wireless sensor network (WSN), are generating huge and significant events that should be rapidly processed for business excellence. In this paper, we describe how complex event processing (CEP) technology can be applied to ubiquitous process management based on context-awareness. To address the issue, we propose a method for context-aware event processing using event processing language (EPL) statement. Specifically, the semantics of a situation drive the transformation of EPL statement templates into executable EPL statements. The proposed method is implemented in the domain of ubiquitous cold chain logistics management. With the proposed method, context-aware event processing can be realized to enhance business performance and excellence in ubiquitous computing environments.

We investigated solid-phase growth reactions for the fabrication of β-FeSi2 films from Fe and FeSi sources by reflection high-energy electron diffraction (RHEED). To enhance the interdiffusion of Fe and Si for the growth of β-FeSi2, the use of FeSi instead of pure Fe as the source for the initial deposition was examined. The RHEED observation during the solid phase reaction indicated that the growth temperature was markedly decreased to 390 K using the FeSi source. We discuss the reaction mechanism of the solid phase growth of β-FeSi2 from Fe and FeSi sources in this paper.

In this paper, negative bias temperature instability (NBTI) reliability of pFETs is analyzed under the post-fabrication SRAM self-improvement scheme that we have developed recently, where cell stability is self-improved by simply applying high stress voltage to supply voltage terminal (VDD) of SRAM cells. It is newly found that there is no significant difference in both threshold voltage and drain current degradation by NBTI stress between fresh PFETs and PFETs after self-improvement scheme application, indicating that the self-improvement scheme has no critical reliability problem.

In this paper, a high performance current latch sense amplifier (CLSA) with vertical MOSFET is proposed, and its performances are investigated. The proposed CLSA with the vertical MOSFET realizes a 11% faster sensing time with about 3% smaller current consumption relative to the conventional CLSA with the planar MOSFET. Moreover, the proposed CLSA with the vertical MOSFET achieves an 1.11 dB increased voltage gain G(f) relative to the conventional CLSA with the planar MOSFET. Furthermore, the proposed CLSA realizes up to about 1.7% larger yield than the conventional CLSA, and its circuit area is 42% smaller than the conventional CLSA.

High-resolution time of arrival (TOA) estimation techniques have great promise for the high range resolution required in recently developed radar systems. A widely known super-resolution TOA estimation algorithm for such applications, the multiple-signal classification (MUSIC) in the frequency domain, has been proposed, which exploits an orthogonal relationship between signal and noise eigenvectors obtained by the correlation matrix of the observed transfer function. However, this method suffers severely from a degraded resolution when a number of highly correlated interference signals are mixed in the same range gate. As a solution for this problem, this paper proposes a novel TOA estimation algorithm by introducing a maximum likelihood independent component analysis (MLICA) approach, in which multiple complex sinusoidal signals are efficiently separated by the likelihood criteria determined by the probability density function (PDF) of a complex sinusoid. This MLICA schemes can decompose highly correlated interference signals, and the proposed method then incorporates the MLICA into the MUSIC method, to enhance the range resolution in richly interfered situations. The results from numerical simulations and experimental investigation demonstrate that our proposed pre-processing method can enhance TOA estimation resolution compared with that obtained by the original MUSIC, particularly for lower signal-to-noise ratios.

A use of ultra wideband (UWB) technology within spacecrafts has been proposed with a view to partially replacing wired interface buses with wireless connections. Adoption of wireless technologies within the spacecrafts could contribute to reduction in cable weight (and launching cost as a result), reduction in the cost of manufacture, more flexibility in layout of spacecraft subsystems, and reliable connections at rotary, moving, and sliding joints. However, multipath propagation in semi-closed conductive enclosures, such as spacecrafts, restricts the link performance. In this paper, UWB and narrowband propagation were measured in a UWB frequency band (from 3.1 to 10.6 GHz, the full-band UWB approved in the United States) within a small spacecrafts and a shield box of the same size. While narrowband propagation resulted in considerable spatial variations in propagation gain due to interferences caused by multipath environments, UWB yielded none. This implies that the UWB systems have an advantage over narrowband from a viewpoint of reducing fading margins. Throughputs exceeding 80 Mb/s were obtained by means of commercially-available UWB devices in the spacecraft. Path gains and throughputs were also measured for various antenna settings and polarizations. Polarization configurations were found to produce almost no effect on average power delay profiles and substantially small effects on the throughputs. Significantly long delay spreads and thus limited link performance are caused by a conductive enclosure (the shield box) without apertures on the surfaces. Even in such an environment, it was found that delay spreads can be suppressed by partially paneling a radio absorber on the inner surfaces. More than 96 Mb/s throughputs were attained when the absorber panel covered typically 4% of the total inner surface area.

A method for the specification of weighting functions for a spaceborne/airborne interferometric synthetic aperture radar (SAR) sensor for Earth observation and environment monitoring is introduced. This method is based on designing an optimum mismatched filter which minimizes the total power in sidelobes located out of a specified range region around the peak value point of the system point-target response, i.e. impulse response function under the constraint imposed on the peak value. It is shown that this method allows achieving appreciable improvement in accuracy performance without degradation in the range resolution.

This paper presents a method of designing transmission line couplers (TLCs) and a mixer-based receiver for dicode partial response communications. The channel design method results in the optimum TLC design. The receiver with mixers and DC balancing circuits reduces the threshold control circuits and digital circuits to decode dicode partial response signals. Our techniques enable low inter-symbol interference (ISI) dicode partial response communications without three level decision circuits and complex threshold control circuits. The techniques were evaluated in a simulation with an EM solver and a transistor level simulation. The circuit was designed in the 90-nm CMOS process. The simulation results show 12-Gb/s operation and 52mW power consumption at 1.2V.

Distribution of current onset voltage (COV) as well as threshold voltage (VTH) and drain induced barrier lowering (DIBL) in MOSFETs fabricated by 65 nm technology is statistically analyzed. Although VTH distribution follows the normal distribution, COV and DIBL deviate from the normal distribution. It is newly found that COV follows the Gumbel distribution, which is known as one of the extreme value distributions. This result of statistical COV analysis supports our model that COV is mainly determined by the deepest potential valley between source and drain.

A novel tunneling field-effect transistor (TFET) featuring the sigma-shape embedded SiGe sources and recessed channel is proposed. The gate facing the source effectively focuses the E-field at the tip of the source and eliminates the gradual turn-on issue of planar TFETs. The fabrication scheme modified from the state-of-the-art 45 nm/32 nm CMOS technology flows provides a unique benefit in the co-integrability and the control of ID-VGS characteristics. The feasibility is verified with TCAD process simulation of the device with 14 nm of the gate dimension. The device simulation shows 5-order change in the drain current with a gate bias change less than 300 mV.

Due to the increasing need for low-power circuits in mobile applications, numerous leakage and performance optimization techniques are being used in modern ICs. In the present paper, we propose a novel transistor-level technique to reduce leakage current while maintaining drive current. By slightly increasing the channel length at the edge of a device that exploits the edge effect, a leakage-optimized transistor can be produced. By using TCAD simulations, we analyze edge-length-biased transistors and then propose the optimal transistor shape for minimizing Ioff with the same or higher Ion current. Results show that by replacing all standard cells with their leakage-optimized counterparts, we can save up to 17% of the leakage in average for a set of benchmark circuits.