The self-improvement of static random access memory (SRAM) cell stability by post-fabrication high-voltage stress is experimentally demonstrated and its mechanism is analyzed using 4k device-matrix-array (DMA) SRAM test element group (TEG). It is shown that the stability of unbalance cells is automatically improved by merely applying stress voltage to the VDD terminal of SRAM. It is newly found that | VTH| of the OFF-state pFETs in the SRAM cell is selectively lowered which improves the cell stability and contributes to the self-improvement.

This paper deals with delay faults on clock lines assuming the launch-on-capture test. In this realistic fault model, the amount of delay at the FF driven by the faulty clock line is such that the scan shift operation can perform correctly even in the presence of a fault, but during the system clock operation, capturing functional value(s) at faulty FF(s), i.e. FF(s) driven by the clock with delay, is delayed and correct value(s) may not be captured. We developed a fault simulator that can handle such faults and using this simulator we investigate the relation between the duration of the delay and the difficulty of detecting clock delay faults in the launch-on-capture test. Next, we propose test generation methods for detecting clock delay faults that affect a single or two FFs. Experimental results for benchmark circuits are given in order to establish the effectiveness of the proposed methods.

The string analysis is a static analysis of dynamically generated strings in a target program, which is applied to check well-formed string construction in web applications. The string analysis constructs a finite state automaton that approximates a set of possible strings generated for a particular string variable at a program location at runtime. A drawback in the string analysis is imprecision in the analysis result, leading to false positives in the well-formedness checkers. To address the imprecision, this paper proposes an improvement technique of the string analysis to make it perform more precise analysis with respect to input validation in web applications. This paper presents the improvement by annotations representing screening of a set of possible strings, and empirical evaluation with experiments of the improved analyzer on real-world web applications.

This paper proposes a simple decentralized cell association method for heterogeneous networks, where low transmission-power pico or femto base stations (BSs) overlay onto a high transmission-power macro BS. The focus of this investigation is on the downlink and the purpose of cell association is to achieve better user fairness, in other words, to increase the minimum average user throughput (worst user throughput). In the proposed method, an appropriate cell association for all users within a cell is achieved in an iterative manner based on the feedback information of each individual user assisted by a small amount of broadcast information from the respective BSs. The proposed method does not require cooperation between BSs. Furthermore, the proposed method is applicable to cases of inter-cell interference coordination (ICIC) between macro and pico/femto BSs through the use of protected radio resources exclusively used by the pico/femto BSs. Based on numerical results, we show that the proposed method adaptively achieves better cell association for all users according to the user location distributions compared to the conventional cell range expansion (CRE) method. The advantage of the proposed method over CRE is further enhanced in an ICIC scenario.

Dynamic spectrum leasing (DSL) is regarded as a promising dynamic spectrum sharing (DSS) scheme both to improve the spectrum revenue of primary users (PUs) and to guarantee the QoS of secondary users (SUs). A pricing-based DSL termed PBDSL is formulated as a Stackelberg DSL game model, where PUs as players entering the interacting game with multiple SUs. The strategic design contains both optimal spectrum pricing schemes (including unit spectrum/interference price and interference sensitivity distributed adjustments) of PUs for the specific shared/leased spectrum and optimal transmission strategies (e.g., transmit power and bandwidth) of SUs. To capture two types of competition relationships among multiple SUs and between SUs and PUs, we investigate two intra-game models of multiple PUs and SUs, respectively, which interact with each other to constitute the final Stackelberg DSL game. The existence and uniqueness of Stackelberg equilibrium solution (SES) are analyzed and proved for presented games, based on which a joint multi-stage PBDSL algorithm is presented to approximate the optimal equilibrium strategies. Numerical results demonstrate the convergence property of the interactive decision-making process, and verify the effectiveness of the proposed algorithm, in a comparison with the Nash equilibrium solution (NES)-based approach.

Corpus-based concatenative speech synthesis has been widely investigated and deployed in recent years since it provides a highly natural synthesized speech quality. The amount of computation required in the run time, however, can often be quite large. In this paper, we propose early stopping schemes for Viterbi beam search in the unit selection, with which we can stop early in the local Viterbi minimization for each unit as well as in the exploration of candidate units for a given target. It takes advantage of the fact that the space of the acoustic parameters of the database units is fixed and certain lower bounds of the concatenation costs can be precomputed. The proposed method for early stopping is admissible in that it does not change the result of the Viterbi beam search. Experiments using probability-based concatenation costs as well as distance-based costs show that the proposed methods of admissible stopping effectively reduce the amount of computation required in the Viterbi beam search while keeping its result unchanged. Furthermore, the reduction effect of computation turned out to be much larger if the available lower bound for concatenation costs is tighter.

Nonvolatile flip-flop enables leakage power reduction in logic circuits and quick return from standby mode. However, it has limited write endurance, and its power consumption for writing is larger than that of conventional D flip-flop (DFF). For this reason, it is important to reduce the number of write operations. The write operations can be reduced by stopping the clock signal to synchronous flip-flops because write operations are executed only when the clock is applied to the flip-flops. In such clock gating, a method using Exclusive OR (XOR) of the current value and the new value as the control signal is well known. The XOR based method is effective, but there are several cases where the write operations can be reduced even if the current value and the new value are different. The paper proposes a method to detect such unnecessary write operations based on state transition analysis, and proposes a write control method to save power consumption of nonvolatile flip-flops. In the method, redundant bits are detected to reduce the number of write operations. If the next state and the outputs do not depend on some current bit, the bit is redundant and not necessary to write. The method is based on Binary Decision Diagram (BDD) calculation. We construct write control circuits to stop the clock signal by converting BDDs representing a set of states where write operations are unnecessary. Proposed method can be combined with the XOR based method and reduce the total write operations. We apply combined method to some benchmark circuits and estimate the power consumption with Synopsys NanoSim. On average, 15.0% power consumption can be reduced compared with only the XOR based method.

As the number of cores and the working sets of parallel workloads increase, shared L2 caches exhibit fewer misses than private L2 caches by making a better use of the total available cache capacity, but they induce higher overall L1 miss latencies because of the longer average distance between the requestor and the home node, and the potential congestions at certain nodes. We observed that there is a high probability that the target data of an L1 miss resides in the L1 cache of a neighbor node. In such cases, these long-distance accesses to the home nodes can be potentially avoided. In order to leverage the aforementioned property, we propose Bayesian Theory based Adaptive Proximity Data Accessing (APDA). In our proposal, we organize the multi-core into clusters of 2x2 nodes, and introduce the Proximity Data Prober (PDP) to detect whether an L1 miss can be served by one of the cluster L1 caches. Furthermore, we devise the Bayesian Decision Classifier (BDC) to adaptively select the remote L2 cache or the neighboring L1 node as the server according to the minimum miss cost. We evaluate this approach on a 64-node multi-core using SPLASH-2 and PARSEC benchmarks, and we find that the APDA can reduce the execution time by 20% and reduce the energy by 14% compared to a standard multi-core with a shared L2. The experimental results demonstrate that our proposal outperforms the up-to-date mechanisms, such as ASR, DCC and RNUCA.

In this paper, we present a novel class of long quasi-cyclic low-density parity-check (QC-LDPC) codes. Each of the codes in this class has a structure formed by concatenating single-parity-check codes and QC-LDPC codes of shorter lengths, which allows for efficient, high throughput encoder/decoder implementations. Using a code in this class, we design a forward error correction (FEC) scheme for optical transmission systems and present its high throughput encoder/decoder architecture. In order to demonstrate its feasibility, we implement the architecture on a field programmable gate array (FPGA) platform. We show by both FPGA-based simulations and measurements of an optical transmission system that the FEC scheme can achieve excellent error performance and that there is no significant performance degradation due to the constraint on its structure while getting an efficient, high throughput implementation is feasible.

This paper analyzes the conventional unequal erasure protection (UXP) scheme for scalable video transmission, and proposes a dynamic hybrid UXP/ARQ transmission framework to improve the performance of the conventional UXP method for bandwidth-constrained scalable video transmission. This framework applies automatic retransmission request (ARQ) to the conventional UXP scheme for scalable video transmission, and dynamically adjusts the transmission time budget of each group of picture (GOP) according to the feedback about the transmission results of the current and previous GOPs from the receiver. Moreover, the parameter of target video quality is introduced and optimized to adapt to the channel condition in pursuit of more efficient dynamic time allocation. In addition, considering the play-out deadline constraint, the time schedule for the proposed scalable video transmission system is presented. Simulation results show that compared with the conventional UXP scheme and its enhanced method, the average peak signal to noise ratio (PSNR) of the reconstructed video can be improved significantly over a wide range of packet loss rates. Besides, the visual quality fluctuation among the GOPs can be reduced for the video which has much movement change.

Due to the growing popularity of High Dynamic Range (HDR) images and HDR displays, a large amount of existing Low Dynamic Range (LDR) images are required to be converted to HDR format to benefit HDR advantages, which give rise to some LDR to HDR algorithms. Most of these algorithms especially tackle overexposed areas during expanding, which is the potential to make the image quality worse than that before processing and introduces artifacts. To dispel these problems, we present a new LDR to HDR approach, unlike the existing techniques, it focuses on avoiding sophisticated treatment to overexposed areas in dynamic range expansion step. Based on a separating principle, firstly, according to the familiar types of overexposure, the overexposed areas are classified into two categories which are removed and corrected respectively by two kinds of techniques. Secondly, for maintaining color consistency, color recovery is carried out to the preprocessed images. Finally, the LDR image is expanded to HDR. Experiments show that the proposed approach performs well and produced images become more favorable and suitable for applications. The image quality metric also illustrates that we can reveal more details without causing artifacts introduced by other algorithms.

Diffusion-weighted (DW)-functional magnetic resonance imaging (fMRI) is a recently reported technique for measuring neural activities by using diffusion-weighted imaging (DWI). DW-fMRI is based on the property that cortical cells swell when the brain is activated. This approach can be used to observe changes in water diffusion around cortical cells. The spatial and temporal resolutions of DW-fMRI are superior to those of blood-oxygenation-level-dependent (BOLD)-fMRI. To investigate how the DWI signal intensities change in DW-fMRI measurement, we carried out Monte Carlo simulations to evaluate the intensities before and after cell swelling. In the simulations, we modeled cortical cells as two compartments by considering differences between the intracellular and the extracellular regions. Simulation results suggested that DWI signal intensities increase after cell swelling because of an increase in the intracellular volume ratio. The simulation model with two compartments, which respectively represent the intracellular and the extracellular regions, shows that the differences in the DWI signal intensities depend on the ratio of the intracellular and the extracellular volumes. We also investigated the MPG parameters, b-value, and separation time dependences on the percent signal changes in DW-fMRI and obtained useful results for DW-fMRI measurements.

Application-Specific Network-on-Chips (ASNoCs) have been proposed as a more promising solution than regular NoCs to the global communication challenges for particular applications in nanoscale System-on-Chip (SoC) designs. In ASNoC Design, one of the key challenges is to generate the most suitable and power efficient NoC topology under the constraints of the application specification. In this work, we present a two-step floorplanning (TSF) algorithm, integrating topology synthesis into floorplanning phase, to automate the synthesis of such ASNoC topologies. At the first-step floorplanning, during the simulated annealing, we explore the optimal positions and clustering of cores and implement an incremental path allocation algorithm to predictively evaluate the power consumption of the generated NoC topology. At the second-step floorplanning, we explore the optimal positions of switches and network interfaces on the floorplan. A power and timing aware path allocation algorithm is also integrated into this step to determine the connectivity across different switches. Experimental results on a variety of benchmarks show that our algorithm can produce greatly improved solutions over the latest works.

This paper presents a digitally error-corrected pipeline analog-to-digital converter (ADC) using linearization of incomplete settling errors. A pre-charging technique is used for residue amplifiers in order to reduce the incomplete settling error itself and linearize the input signal dependency of the incomplete settling error. A technique with charge redistribution of divided capacitors is proposed for pre-charging capacitors without any additional reference sources. This linearized settling error is corrected by a first-order error approximation in digital domain with feasible complexity and cost. Simulation results show that the ADC achieves SNDR of 70 dB, SFDR of 79 dB at nyquist input frequency in a 65 nm CMOS process under 1.2 V power supply voltage for 1.2 Vp-p input signal swing. The estimated power consumption of the 12b 200 MS/s pipeline ADC using the proposed digital error correction of incomplete settling errors is 7.6 mW with a small FOM of 22 fJ/conv-step.

Recently, multi-core processors are used in embedded systems very often. Since application programs is much limited running on embedded systems, there must exists an optimal cache memory configuration in terms of power and area. Simulating application programs on various cache configurations is one of the best options to determine the optimal one. Multi-core cache configuration simulation, however, is much more complicated and takes much more time than single-core cache configuration simulation. In this paper, we propose a very fast dual-core L1 cache configuration simulation algorithm. We first propose a new data structure where just a single data structure represents two or more multi-core cache configurations with different cache associativities. After that, we propose a new multi-core cache configuration simulation algorithm using our new data structure associated with new theorems. Experimental results demonstrate that our algorithm obtains exact simulation results but runs 20 times faster than a conventional approach.

This paper presents a bistatic remote sensing system to efficiently estimate the characteristics of sea swell near a harbor by receiving and processing global navigation satellite system signals transmitted in line-of-sight channels and fading multipath channels. The new system is designed to measure and monitor sea swell to improve the safety of mooring and navigation services in or around harbors, and long-term measurement also will provide valuable hydrologic data for harbor construction or reconstruction. The system uses two sets of antennas. One is a conventional antenna to receive line-of-sight signal and mitigate the disturbances from multiple propagation paths, and the other is a left hand circular polarization arrayed antenna to receive reflected signals from sea-surface. In particular, a wide bandwidth RF/IF front-end is designed to process reflected signals with high sampling frequency. A software receiver is developed to provide information from satellites and line-of-sight signals, and a wave characteristic estimator is also developed to process reflected signals. More specifically, correlators and Teager-Kaiser energy operator are combined to detect and depict reflected signals. Wave propagation of sea swell can be accurately mapped using intensity and relative time delays of reflected signals. The operational performance of the remote sensing system was also evaluated by numerical simulations. The results confirm that wavelength and wave period can be measured precisely by the proposed bistatic ocean wave remote sensing system.

Periodic-finite-type shifts (PFT's) are sofic shifts which forbid the appearance of finitely many pre-specified words in a periodic manner. The class of PFT's strictly includes the class of shifts of finite type (SFT's). The zeta function of a PFT is a generating function for the number of periodic sequences in the shift. For a general sofic shift, there exists a formula, attributed to Manning and Bowen, which computes the zeta function of the shift from certain auxiliary graphs constructed from a presentation of the shift. In this paper, we derive an interesting alternative formula computable from certain “word-based graphs” constructed from the periodically-forbidden word description of the PFT. The advantages of our formula over the Manning-Bowen formula are discussed.

In this paper we propose a method to use features of an individual object to locate and recognize this object concurrently in a static image with Multi-feature fusion based on multiple objects sample library. This method is proposed based on the observation that lots of previous works focuses on category recognition and takes advantage of common characters of special category to detect the existence of it. However, these algorithms cease to be effective if we search existence of individual objects instead of categories in complex background. To solve this problem, we abandon the concept of category and propose an effective way to use directly features of an individual object as clues to detection and recognition. In our system, we import multi-feature fusion method based on colour histogram and prominent SIFT (p-SIFT) feature to improve detection and recognition accuracy rate. p-SIFT feature is an improved SIFT feature acquired by further feature extraction of correlation information based on Feature Matrix aiming at low computation complexity with good matching rate that is proposed by ourselves. In process of detecting object, we abandon conventional methods and instead take full use of multi-feature to start with a simple but effective way-using colour feature to reduce amounts of patches of interest (POI). Our method is evaluated on several publicly available datasets including Pascal VOC 2005 dataset, Objects101 and datasets provided by Achanta et al.

In this paper, we describe a new method to deal with analog signal in time domain. The method converts voltage signal to time-interleaved phase modulation signal of clock edge. After being amplified by a new time amplifier (TA), phases of the signal are converted to digital codes by successive approximation time-to-digital converter (SA-TDC). The test chip includes 8 interleaved 4 bit SA-TDCs with short latency. The chip operates up to 4.4 GHz. The measured ENOB is 3.51 bit and FOM is 0.49 pJ/conv.

Cell Range Expansion (CRE) is a promising technique for the enhancement of traffic offload to pico cells. CRE is realized by adjusting the trigger timing of handover (HO) toward/from pico cells. However, inappropriate setting of trigger timing results in HO failures or Ping-Pong HOs. Both the HO failures and the Ping-Pong HOs degrade the continuity of user data services. Therefore, when CRE is applied, both the HO failures and the Ping-Pong HOs should be kept suppressed in order to guarantee the continuity of services for users. However, in the conventional studies, the application of CRE is discussed without consideration of HO performance. This paper clarifies the application range of CRE from the perspective of HO performance by taking the HO failure rates and the Ping-Pong HO rates as HO performance measures. As an example, we reveal that there is an appropriate CRE bias values which keep both the HO failure rate and Ping-Pong HO rate less than 1%. Such an appropriate CRE bias value range is smaller than the one without consideration of HO performance, which is reported in the conventional studies. The authors also observed that Ping-Pong HO occurs due to the short staying time of users at pico cells in high velocity environment. The rate of such Ping-Pong HOs becomes more than about 1% when the user velocity is more than 60 km/h. Therefore, it is more difficult in high velocity environment than that in low velocity environment to find appropriate CRE bias values.