Electromagnetic emissions leak confidential data of cryptographic devices. Electromagnetic Analysis (EMA) exploits such emission for cryptanalysis. The performance of EMA dramatically decreases when correlated noise, which is caused by the interference of clock network and exhibits strong correlation with encryption signal, is present in the acquired EM signal. In this paper, three techniques are proposed to reduce the correlated noise. Based on the observation that the clock signal has a high variance at the signal edges, the first technique: single-sample Singular Value Decomposition (SVD), extracts the clock signal with only one EM sample. The second technique: multi-sample SVD is capable of suppressing the clock signal with short sampling length. The third one: averaged subtraction is suitable for estimation of correlated noise when background samplings are included. Experiments on the EM signal during AES encryption on the FPGA and ASIC implementation demonstrate that the proposed techniques increase SNR as much as 22.94 dB, and the success rates of EMA show that the data-independent information is retained and the performance of EMA is improved.

A leakage-aware Coordinated Scheduling/Coordinated Beamforming (CS/CB) scheme for heterogeneous networks with layered limited feedback is proposed. In particular, all pico cells cooperatively select an optimal beamforming vector for the macro cell within a CoMP cluster so as to minimizing leakage power from the macro cell. Simulations show that the proposed scheme outperforms the conventional non-CoMP scheme with perfect channel state information at teansmitter (CSIT). Furthermore, the feedback amount and scheduler complexity is decreased greatly.

This paper proposes a novel method for object tracking by combining local feature and global template-based methods. The proposed algorithm consists of two stages from coarse to fine. The first stage applies on-line classifiers to match the corresponding keypoints between the input frame and the reference frame. Thus a rough motion parameter can be estimated using RANSAC. The second stage employs kernel-based global representation in successive frames to refine the motion parameter. In addition, we use the kernel weight obtained during the second stage to guide the on-line learning process of the keypoints' description. Experimental results demonstrate the effectiveness of the proposed technique.

Recently, some cryptographic primitives have been described that are based on the supposed hardness of finding an isogeny between two supersingular elliptic curves. As a part of such a primitive, Charles et al. proposed an algorithm for computing sequences of 2-isogenies. However, their method involves several redundant computations. We construct simple algorithms without such redundancy, based on very compact descriptions of the 2-isogenies. For that, we use some observations on 2-torsion points.

This article presents a differential fault analysis (DFA) technique using round addition for a generalized Feistel network (GFN) including CLEFIA and RC6. Here the term “round addition” means that the round operation executes twice using the same round key. The proposed DFA needs bypassing of an operation to count the number of rounds such as increment or decrement. To verify the feasibility of our proposal, we implement several operations, including increment and decrement, on a microcontroller and experimentally confirm the operation bypassing. The proposed round addition technique works effectively for the generalized Feistel network with a partial whitening operation after the last round. In the case of a 128-bit CLEFIA, we show a procedure to reconstruct the round keys or a secret key using one correct ciphertext and two faulty ciphertexts. Our DFA also works for DES and RC6.

In this letter, we point out that key substitution attacks should be taken into account for multisignature schemes, which implies that the existing security notions for multisignature schemes are not sufficient. As an example, we show that the multisignature scheme proposed by Boldyreva at PKC'03 is susceptible to key substitution attacks.

Existing salient object detection methods either simply use a threshold to detect desired salient objects from saliency map or search the most promising rectangular window covering salient objects on the saliency map. There are two problems in the existing methods: 1) The performance of threshold-dependent methods depends on a threshold selection and it is difficult to select an appropriate threshold value. 2) The rectangular window not only covers the salient object but also contains background pixels, which leads to imprecise salient object detection. For solving these problems, a novel saliency threshold-free method for detecting the salient object with a well-defined boundary is proposed in this paper. We propose a novel window search algorithm to locate a rectangular window on our saliency map, which contains as many as possible pixels belonging the salient object and as few as possible background pixels. Once the window is determined, GrabCut is applied to extract salient object with a well-defined boundary. Compared with existing methods, our approach doesn't need any threshold to binarize the saliency map and additional operations. Experimental results show that our approach outperforms 4 state-of-the-art salient object detection methods, yielding higher precision and better F-Measure.

We propose the asynchronous receiver-initiated MAC protocol with the stair-like sleep mode; each node reduces its own sleep time by the sleep-change-rate depending on the number of hops from the source to the sink in wireless sensor networks (WSNs). Using the stair-like sleep approach, our protocol achieves high delivery ratio, low packet delay, and high energy efficiency due to the reduction in idle listening time. Our protocol can formulate the upper bound of the idle listening time because of the feature that the sleep time decreases in a geometric progression, and the reduction of the idle listening time is obtained by using the stair-like sleep approach. In our proposed scheme, the sink calculates the sleep change rate based on the number of hops from the source to the sink. By using the control packets which have the role of the acknowledgment (ACK), our proposed protocol can achieve the stair-like sleep with no additional control packets. In addition, even in the network condition that multi-targets are detected, and the number of hops to the sink are changed frequently, our proposed protocol can change the sleep change rate adaptively because the sink can always obtain the number of hops from the source to the sink. Simulation results show that the proposed protocol can improve the performance in terms of the packet delivery ratio, the packet delay, and the energy efficiency compared to the conventional receiver-initiated MAC (RI-MAC) protocol.

Fault-based attacks are very powerful to recover the secret key for cryptographic implementations. In this work, we consider the faulty output value under a certain fault injection intensity as a new type of leakage called faulty behavior. We examine the data-dependency of the faulty behavior and propose a related side-channel attack called fault behavior analysis (FBA). To verify the validity of the proposed attack, we first show that our attack can work effectively on AES-COMP of SASEBO-R. Then we show how to apply the similar attack on two AES implementations with masking countermeasures, i.e., AES-MAO and AES-TI. Finally we compare the proposed FBA attack with the DFA attack and the FSA attack, trying to complete the research map for the fault-based attack based on setup-time violations.

Accurate modeling of sea clutter and detection of low observable targets within sea clutter are the major goals of radar signal processing applications. Recently, fractal geometry has been applied to the analysis of high range resolution radar sea clutters. The box-counting method is widely used to estimate fractal dimension but it has some drawbacks. We explain the drawbacks and propose a new fractal dimension based detector to increase detection performance in comparison with traditional detectors. Both statistically generated and real data samples are used to compare detector performance.

This paper proposes applying intra-subframe frequency hopping (FH) to closed-loop (CL) type transmit diversity using codebook based precoding for a shared channel carrying user traffic data in discrete Fourier transform (DFT)-precoded Orthogonal Frequency Division Multiple Access (OFDMA). In the paper, we present two types of precoding schemes associated with intra-subframe FH: individual precoding vector selection between 2 slots where a 1-ms subframe comprises 2 slots among the reduced precoding codebooks, and common precoding vector selection between 2 slots. We investigate the effect of intra-subframe FH on the codebook based transmit diversity in terms of the average block error rate (BLER) performance while maintaining the same number of feedback bits required for notification of the selected precoding vector as that for the conventional CL transmit diversity without FH. Computer simulation results show that the codebook based transmit diversity with intra-subframe FH is very effective in decreasing the required average received signal-to-noise power ratio (SNR) when the fading maximum Doppler frequency, fD, is higher than approximately 50 Hz both for 2- and 4-antenna transmission in the DFT-precoded OFDMA.

Wireless capsule endoscopy (WCE) is now one of most important applications in implant body area networks (BANs). WCE requires high throughput performance due to its real-time data transmission, whereas the communication performance depends much on the transmit power, which is strictly regulated in order to satisfy a safety guideline in terms of specific absorption rate (SAR). Spatial diversity reception is well known to improve the wireless performance without any temporal and spectral resource expansion. Additionally, applying spatial diversity reception to WCE systems can be expected to not only improve the wireless communication performance but also to reduce SAR. Therefore, this paper investigates the impact of spatial diversity reception on SAR levels for the 400 MHz medical implant communication service (MICS) band. To begin with, based on finite-difference time-domain (FDTD) simulations for implant BAN propagation with a numerical human body model, we first calculate the BER performance and derive the required transmit power to secure a permissible BER. Then, this paper calculates the local peak SAR under the required transmit power when the implant transmitter moves through the digestive organs. Finally, our simulation results demonstrate that applying spatial diversity reception can significantly reduce SAR in implant BANs.

Based on a proposed frame structure with an unequal sensing slot duration for each channel, and two sensing scenarios (with or without cooperation), a joint channel and sensing time assignment is suggested to maximize the uplink throughput of the centralized multi-band cognitive radio network with the consideration of the mutual interference among the secondary users (SUs). Firstly, the channel assignment is performed by using the proposed Delta Non-square Hungarian (DNH), which is a modified iterative Hungarian algorithm distinguished by throughput increment maximization and non-square weight matrix. Simulation results illustrate that DNH has significant advantages in enhancing the throughput and reducing the computational complexity. Moreover, a hybrid channel assignment, also performed by DNH, is improved based on the two sensing scenarios to maximize the throughput while efficiently limiting the interference power to primary users. Secondly, the convexity of the throughput functions within the range of sensing time is proved under the proposed frame structure, and then the maximum throughput is achieved through the steepest descent method-based sensing time assignment. Both of these results are corroborated by simulations.

In this letter, a novel ultra-wideband circular quasi-fractal monopole antenna with a six-petaled lotus pattern is presented. The CPW-fed technique and quasi-fractal concept are used to achieve ultra-wideband characteristics. The size of the proposed antenna is 4250 mm2 with a lotus diameter of 19.8 mm. The proposed antenna exhibits ultra-wideband characteristics from 2.65 to 12.72 GHz, which corresponds to a fractional bandwidth of 131%. The measured radiation pattern of the proposed antenna is nearly omnidirectional.

This paper proposes a spectrum-overlapped resource management (SORM) technique where each user equipment (UE) can ideally obtain the frequency selection diversity gain under multi-user environments. In the SORM technique for cellular systems, under assumption of adopting a soft canceller with minimum mean square error (SC/MMSE) turbo equalizer, an evolved node B (eNB) accepts overlapped frequency resource allocation. As a result, each UE can use the frequency bins having the highest channel gain. However, the SORM becomes non-orthogonal access when the frequency bins having high channel gain for UEs are partially identical. In this case, the inter-user interference (IUI) caused by overlapping spectra among UEs is eventually canceled out by using the SC/MMSE turbo equalizer. Therefore, SORM can achieve better performance than orthogonal access e.g. FDMA when the IUI is completely canceled. This paper demonstrates that SORM has the potential to improve transmission performance, by extrinsic information transfer (EXIT) analysis. Moreover, this paper evaluates the block error rate (BLER) performance of the SORM and the FDMA. Consequently, this paper shows that the SORM outperforms the FDMA.

We propose optical path routing and frequency slot assignment algorithms that can make the best use of elastic optical paths and the capabilities of distance adaptive modulation. Due to the computational difficulty of the assignment problem, we develop algorithms for 1+1 dedicated/1:1 shared protected ring networks and unprotected mesh networks to that fully utilize the characteristics of the topologies. Numerical experiments elucidate that the introduction of path elasticity and distance adaptive modulation significantly reduce the occupied bandwidth.

A low-cost and low-power via-programmable structured ASIC architecture named “VPEX3” and a VPEX3-specific CAD system are developed. In the VPEX3 architecture, which is an improved version of the old VPEX and VPEX2 architectures, an arbitrary logic function including sequential logic can be programmed by three via layers. The logic elements (LEs) of VPEX3 are 60% smaller than those of the previous VPEX2, which can be programmed by two via layers. In this paper, we describe a global architecture named Logic Array Block (LAB) composed of LE matrices. The clock lines are buffered in the buffering region on the left and right sides of LAB. Next, a VPEX3-specific CAD system utilizing an academic placement tool named “CAPO” and the “FGR” global router is developed. Since these tools are originally designed for ASICs, we developed CAD tools for supporting a structured ASIC architecture. In particular, we developed a detailed router that assigns via positions on the via-programmable routing fabric. Our CAD system successfully converts the HDL design to GDS-II data format including via-1, 2, 3 layouts, and the successful verification of LVS and DRC on GDSII is achieved. The performance of the VPEX3 architecture and the CAD system is evaluated using ISCAS benchmark circuits. The developed CAD system is used to successfully design a test chip composed of 130110 LEs.

Capacitor charging modeling efficiently and accurately represents power consumption current of CMOS digital circuits and actualizes co-simulation of AC power noise including the interaction with on-chip and on-board integrated power delivery network (PDN). It is clearly demonstrated that the AC power noise is dominantly characterized by the frequency-dependent impedance of PDN and also by the operating frequency of circuits as well. A 65 nm CMOS chip exhibits the AC power noise components in substantial relation with the parallel resonance of the PDN seen from on-chip digital circuits. An on-chip noise monitor measures in-circuit power supply voltage, while a near-field magnetic probing derives on-board power supply current. The proposed co-simulation well matches the power noise measurements. The proposed AC noise co-simulation will be essentially applicable in the design of PDNs toward on-chip power supply integrity (PSI) and off-chip electromagnetic compatibility (EMC).

L-band SiGe HBT frequency-tunable differential amplifiers with dual-bandpass or dual-bandstop responses have been developed for the next generation adaptive and/or reconfigurable wireless radios. Varactor-loaded dual-band resonators comprised of series and parallel LC circuits are employed in the output circuit of differential amplifiers for realizing dual-bandpass responses as well as the series feedback circuit for dual-bandstop responses. The varactor-loaded series and parallel LC resonator can provide a wider frequency separation between dual-band frequencies than the stacked LC resonator. With the use of the varactor-loaded dual-band resonator in the design of the low-noise SiGe HBT differential amplifier with dual-bandpass responses, the lower-band frequency can be varied from 0.58 to 0.77 GHz with a fixed upper-band frequency of 1.54 GHz. Meanwhile, the upper-band frequency can be varied from 1.1 to 1.5 GHz for a fixed lower-band frequency of 0.57 GHz. The dual-band gain was 6.4 to 13.3 dB over the whole frequency band. In addition, with the use of the varactor-loaded dual-band resonator in the design of the low-noise differential amplifier with dual-bandstop responses, the lower bandstop frequency can be varied from 0.38 to 0.68 GHz with an upper bandstop frequency from 1.05 to 1.12 GHz. Meanwhile, the upper bandstop frequency can be varied from 0.69 to 1.02 GHz for a lower bandstop frequency of 0.38 GHz. The maximal dual-band rejection of gain was 14.4 dB. The varactor-loaded dual-band resonator presented in this paper is expected to greatly contribute to realizing the next generation adaptive and/or reconfigurable wireless transceivers.

A fractional-N phase-locked loop (PLL) is designed for the DigRF interface. The digital part of the PLL mainly consists of a dual-mode phase frequency detector (PFD), a digital counter, and a digital delta-sigma modulator (DSM). The PFD can operate on either 52 MHz or 26 MHz reference frequencies, depending on its use of only the rising edge or both the rising and the falling edges of the reference clock. The interface between the counter and the DSM is designed to give enough timing margin in terms of the signal round-trip delay. The circuitry is implemented using a 90-nm CMOS process technology with a 1.2-V supply, draining 1 mA.