The Transduction Method is a powerful way to design logic circuits, utilizing already existing circuits. A set of permissible functions (SPF) plays an essential role in such circuit transformation/reduction, and is computed at each point (connection or gate output). Currently, two types of SPFs have been used: the maximum SPFs (MSPFs) and compatible SPFs (CSPFs). At each point, the MSPF is literally the set of all PF's, and CSPF is a subset of the MSPF. When CSPFs are calculated, priorities are first assigned to all gates in the circuit. Based on the priorities, it is decided which subset is to be selected as the CSPF. The quality of the results depends on the priorities. In this paper, the concept of super-sets of permissible functions (SSPFs) is introduced to reduce the effect of the priorities that CSPFs depend on. In order to loosen the dependency, each SSPF is computed to contain CSPFs which are candidates to be selected. The experimental results show that the SSPF-based Transduction Method has intermediate reduction capability and takes an intermediate computation time between the MSPF-based and CSPF-based ones. The capability and the time are considered as an acceptably good trade-off. In addition, without any transformations, since SSPFs are the maximum super-set, SSPFs are applicable for analyzing the maximum performance of the CSPF-based transformation, for comparison with the MSPF-based one. Theoretically, the number of connectable gate pairs detected by the MSPFs is 100%. According to the experimental results obtained using SSPFs, on average, 99% are detectable by SSPFs and 1% are detectable only by using the MSPFs. The results show that by using CSPFs, 72% of connectable gate pairs are detectable with any priority assignment and 99% (SSPFs capability) are detectable on average even when the best priorities are assigned. According to the experimental results of CSPF calculation with five priorities, 82% to 93% are practically detectable on average. This is the first quantitative analysis realized by SSPFs which compares the CSPF-based and MSPF-based Transduction Methods with respect to the coverage of PF's.

We have demonstrated radio-over-fiber transmission of wireless signals at millimeter-wave bands. The system incorporated 25 km of an optical intermediate frequency feeder and 60 GHz OFDM signal transmission at 155 Mbps with a BER of less than 10-6 was achieved within the system cell of a radius of 2.6 m under the channel condition of Line-of-Sight.

This paper proposes a new simulation algorithm for analyzing large power distribution networks, modeled as linear RLC circuits, based on a novel partial random walk concept. The random walk simulation method has been shown to be an efficient way to solve for voltages of small number of nodes in a large power distribution network, but the algorithm becomes expensive to solve for voltages of nodes that are more than a few with high accuracy. In this paper, we combine direct methods like LU factorization with the random walk concept to solve power distribution networks when voltage waveforms from a large number of nodes are required. We extend the random walk algorithm to deal with general RLC networks and show that Norton companion models for capacitors and self-inductors are more amenable for transient analysis by using random walks than Thevenin companion models. We also show that by nodal analysis (NA) formulation for all the voltage sources, LU-based direct simulations of subcircuits can be speeded up. Experimental results demonstrate that the resulting algorithm, called partial random walk (PRW), has significant advantages over the existing random walk method especially when the VDD/GND nodes are sparse and accuracy requirement is high.

In recent years the size of transformer in a DC-DC converter becomes smaller and thinner for power module type application. It results in the increase of the leakage inductances because the number of turns of the secondary winding becomes smaller. This paper presents the analysis of static and dynamic characteristics of the novel flyback converter proposed before, and clarifies that the transformer's leakage inductances deteriorate the static load regulation, but improve the dynamic stability by increasing the dumping factor.

This study proposes an edge-based single-resolution compression scheme for triangular mesh connectivity. The proposed method improves upon EdgeBreaker. Nearly all of these algorithms are either multiple traversals or operate in reverse order. Operating in reverse order should work only off-line in the EdgeBreaker decompression process. Many restrictions on applications will be caused by these factors. To overcome these restrictions, the algorithm developed here can both encode and decode 3D models in a straightforward manner by single traversal in sequential order. Most algorithms require complicated operations when the triangular mesh is split. This study investigates spatial locality to minimize costs in split operations. Meanwhile, some simplification rules are proposed by considering geometric characteristics which ignore the last triangle when a split occurs. The proposed method improves not only the compression ratio but also the execution time.

In recent years, interruption of services large-scale business sites and Root Name Servers caused by Denial-of-Service (DoS) attacks or Distributed DoS (DDoS) attacks has become an issue. Techniques for specifying attackers are, thus important. On the other hand, since information on attackers' source IP addresses are generally spoofed, tracing techniques are required for DoS attacks. In this paper, we predict network traffic volume at observation points on the network, and detect DoS attacks by carefully examining the difference between predicted traffic volume and actual traffic volume. Moreover, we assume that the duration time of an attack is the same at every observation point the attack traffic passes, and propose a tracing method that uses attack duration time as a parameter. We show that our proposed method is effective in tracing DDoS attacks.

In multicarrier code division multiple access (MC-CDMA) systems, the orthogonality among the spreading codes is destroyed because the channels exhibit frequency-selective fading and the despreading stage performs gain control; that is, inter-code interference (ICI) can significantly degrade system performance. This paper proposes an optimum spreading code assignment method that reflects our analysis of ICI for up and downlink MC-CDMA cellular systems over correlated frequency-selective Rayleigh fading channels. At first, we derive theoretical expressions for the desired-to-undesired signal power ratio (DUR) as a quantitative representation of ICI; computer simulation results demonstrate the validity of the analytical results. Next, based on the ICI imbalance among code pairs, we assign specific spreading codes to users to minimize ICI (in short, to maximize the multiplexing performance); our proposed method considers the quality of service (QoS) policy of users or operators. We show that the proposed method yields better performance, in terms of DUR, than the conventional methods. The proposed method can maximize the multiplexing performance of a MC-CDMA cellular system once the channel model, spreading sequence, and combining strategy have been set. Three combining strategies are examined at the despreading stage for the uplink, equal gain combining (EGC), orthogonality restoring combining (ORC), and maximum ratio combining (MRC), while two are considered for the downlink, EGC and MRC.

This paper proposes a cell layout synthesis method via Boolean Satisfiability (SAT). Cell layout synthesis problems are first transformed into SAT problems by our formulations. Our method realizes a high-speed layout synthesis for CMOS logic cells and guarantees to generate the minimum-width cells with routability under our layout styles. It considers complementary P-/N-MOSFETs individually during transistor placement, and can generate smaller width layout compared with pairing the complementary P-/N-MOSFETs case. To demonstrate the effectiveness of our SAT-based cell synthesis, we present experimental results which compare it with the 0-1 ILP-based transistor placement method and a commercial cell generation tool. The experimental results show that our SAT-based method can generate minimum-width placements in much shorter run time than the 0-1 ILP-based transistor placement method, and can generate the cell layouts of 32 static dual CMOS logic circuits in 54% run time compared with the commercial tool. Area increase of our method without compaction is only 3% compared with the commercial tool with compaction.

There is an emerging requirement for real-time flow-based traffic monitoring, which is vital to detecting and/or tracing DoS attacks as well as troubleshooting and traffic engineering in the ISP networks. We propose the architecture for a scalable real-time flow measurement tool in order to allow operators to flexibly define "the targeted flows" on-demand, to obtain various statistics on those flows, and to visualize them in a real-time manner. A traffic distribution device and multiple traffic capture devices processing packets in parallel are included in the architecture, in which the former device copies traffic and distributes it to the latter devices. We evaluate the performance of a proto-type implementation on PC-UNIX in testbed experiments to demonstrate the scalability of our architecture. The evaluation shows that the performance increases in proportion to the number of the capture devices and the maximum performance reaches 80 K pps with six capture devices. Finally we also show applications of our tool, which indicate the advantage of flexible fine-grained flow measurements.

Thin film of polyurethane having metal complex was prepared by vapor deposition polymerization of bis (5,8-dihydroxyquinoline) zinc (ZnHq2) and 4, 4'-diphenylmethane diisocyanate monomers. The film was applied for the electron-transporting emissive layer of the organic light emitting diode. The deposition-polymerized film was found to give higher quantum efficiency of luminescence than the ZnHq2 monomer film.

This paper presents a non-scan design scheme to enhance delay fault testability of controllers. In this scheme, we utilize a given state transition graph (STG) to test delay faults in its synthesized controller. The original behavior of the STG is used during test application. For faults that cannot be detected by using the original behavior, we design an extra logic, called an invalid test state and transition generator, to make those faults detectable. Our scheme allows achieving short test application time and at-speed testing. We show the effectiveness of our method by experiments.

In this paper, a test architecture optimization for system-on-a-chip under floorplanning constraints is proposed. The models of previous test architecture optimizations were too ideal to be applied to industrial SOCs. To make matters worse, they couldn't treat topological locality of cores, that is, floorplanning constraints. The optimization proposed in this paper can avoid long wires for TAMs in consideration of floorplanning constraints and finish optimizing test architectures within reasonable computation time.

Ultrafast all-optical switching was experimentally demonstrated using four-wave mixing in an SOA. Two pump pulses with different wavelengths and timings were used for 12 switching. The cross-correlation measurements of FWM signals using a short reference pulse show the high-speed switching capability for wavelength routing in OTDM networks.

Availability of network access "anytime and anywhere" will impose new requirements to presence services - server load sharing and privacy protection. In such cases, presence services would have to deal with sensor device information with maximum consideration of user's privacy. In this paper, we propose FieldCast: peer-to-peer system architecture for presence information exchange in ubiquitous computing environment. According to our proposal, presence information is exchanged directly among user's own computing resources. We illustrate our result of evaluation that proves the feasibility of our proposal.

Performance measurements are indispensable for managing the Internet. Among the performance measurement techniques known, passive measurement is attractive because of its accuracy; user traffic is observed without inserting additional test traffic. However, the technique is handicapped by its large storage and bandwidth costs. This paper proposes a passive packet loss measurement technique that effectively avoids the difficulty of the conventional passive measurement approaches. Its key advance is utilizing the packet feature computed by a hash function. Since the feature can identify a packet with a short length of data, it becomes possible to greatly decrease the storage and bandwidth costs of passive measurements. The paper details the measurement procedure and assesses the design parameters used in the method. In addition, the validity of the proposed method is confirmed through experiments. The experiments also show the advantage of the method over the conventional active measurement.

The partial projection filter gives optimal signal restoration in the presence of both the signal space and the observation space noises. In this paper, the filter has been characterized from the point of view of its signal restoration and noise suppression capabilities. The filter is shown to suppress the noise component in the restored signal while retaining the signal component, thus maximizing the signal-to-noise ratio. Further, a digital implementation of the filter is presented in matrix form in contrast to its original operator based derivation, for practical applications.

Replication to mask the effects of failures is a basic technique for improving reliability of a file system. Consistency control protocols are implemented to ensure the consistency among these replicas. The native token-based mechanism which merely sequences the distributed requests suffered from the poor system utilization due to the lack of dependence checking between writes and management of out-of-ordered requests. Hence, in this paper, by utilizing the idempotent property of NFS and executing ahead most of independent WRITE requests, the new consistency control scheme is proposed to improve the performance of operations and failure recovery. Finally, a numeric case shows the efficiency of the new scheme.

In this paper, usage of undefined states on a State Transition Graph (STG) is addressed to obtain high fault coverage, in the area of Synthesis For Testability (SFT) of synchronous sequential circuits. Basically, a given STG could be modified by adding undefined states and distinguishable transitions so that each state might be included in one strongly-connected component as much as possible. Such modification decreases the number of redundant faults caused by the existence of unreachable states on an STG. For the modification, we propose two algorithms for both incompletely-specified STGs and completely-specified STGs, respectively. In case of incompletely-specified STGs, undefined states are added using unspecified transitions of defined states. In case of completely-specified STGs, undefined states are added by changing transitions specified on an STG while preserving state equivalence. Experimental results with MCNC benchmarks show that the number of redundant faults of gate-level circuits synthesized by our modified STGs are reduced, resulting in high fault coverage as well as short test generation time

A large memory is typically designed with multiple identical memory blocks for reducing delay and power. The circuit verification of individual memory blocks can be effectively handled by the Symbolic Trajectory Evaluation (STE) approach. However, if multiple memory blocks are integrated into a single system, the STE approach cannot verify it economically. This paper introduces algorithms for verifying block-level connectivity of memories. The verification time of a large memory can be reduced drastically by using bottom-up verification scheme. That is, a memory block is first verified thoroughly, and then only the interconnection between memory blocks of the large memory needs to be verified. The proposed verification algorithms require (3n+2(log2n+1)+3log2m) Read/Write operations for a 2nm-bit memory, where n and m are the address width and data width, respectively. Also, the algorithms can verify 100% of the inter-port and intra-port signal misplaced faults of the address, data input, and data output ports.

In this paper, we present a test data compression technique to reduce test data volume for multiscan-based designs. In our method the internal scan chains are divided into equal sized groups and two dictionaries were build to encode either an entire slice or a subset of the slice. Depending on the codeword, the decompressor may load all scan chains or may load only a group of the scan chains, which can enhance the effectiveness of dictionary-based compression. In contrast to previous dictionary coding techniques, even for the CUT with a large number of scan chains, the proposed approach can achieve satisfied reduction in test data volume with a reasonable smaller dictionary. Experimental results showed the proposed test scheme works particularly well for the large ISCAS'89 benchmarks.