In this paper two algorithms for the synthesis and minimization of a CA (cellular array architecture) are proposed. Starting from a completely specified single-output switching function, our methods produce rectangularly shaped arrays of cells, interconnected in chains, with an effort to minimize the number of the produced chains (cascades). This kind of cellular topology is known throughout the bibliography as Maitra cellular arrays. The significance of those algorithms is underlined by the fact that this particular type of cellular architecture can be mapped to reversible circuits and gates (generalized Toffoli gates), which are the type of logic used in quantum circuits. The proposed methodologies include use of ETDDs (EXOR ternary decision diagrams), and switching function decompositions (including new types of boolean expansions).

This paper discusses performance limitation of on-chip interconnects. On-chip global interconnects are considered to be a bottleneck of high-performance LSIs. To overcome this issue, high-speed signaling and large throughput interconnection using electrical wires have been studied. However the limitation of on-chip interconnects has not been examined sufficiently. This paper reveals the maximum performance of on-chip global interconnects based on derived analytic expressions and detailed circuit simulation. We derive trade-off curves among bit rate, interconnect length, and eye opening both for single-end and for differential signaling. The results show that differential signaling improves signaling performance several times compared with conventional single-end signaling, and demonstrate that 80 Gbps differential signaling on 10 mm interconnects is promising.

A novel CMOS LC oscillator architecture combining an LC tuned oscillator and a ring structure is presented as a new design topology to deliver improved phase noise for multiphase applications. The relative enhancement in the phase noise is estimated using a linear noise modeling approach. A three-stage LC-ring oscillator fabricated in a 0.6 mm CMOS technology achieves measured phase noise of -132 dBc/Hz at 600 kHz offset from a 900 MHz carrier and dissipates 20 mW with a 2.5 V power supply.

We propose a novel approach for designing a low power datapath in wireless communication systems. Especially, we focus on the digital FIR filter. Our proposed approach can reduce the power consumption and the circuit area of the digital FIR filter by optimizing the bitwidth of the each filter coefficient with keeping the filter calculation accuracy. At first, we formulate the constraints about keeping accuracy of the filter calculations. We define the problem to find the optimized bitwidth of each filter coefficient. Our defined problem can be solved by using the commercial optimization tool. We evaluate the effects of consuming power reduction by comparing the digital FIR filters designed in the same bitwidth of all coefficients. We confirm that our approach is effective for a low power digital FIR filter.

A novel bias circuit providing a stable quiescent current for temperature and supply voltage variations is proposed and implemented to a W-CDMA MMIC power amplifier. The power amplifier with the proposed bias circuit has the quiescent current variation of only 6% for the -30 to 90 temperature change, and 8.5% for the 2.9 V to 3.1 V supply voltage change, and the variation of the power gain at the 28 dBm output power is less than 0.8 (0.05) dB for the 0.1 V of supply voltage (60 of temperature) variation.

The development of information/communication technology has made it possible to access substantial amounts of data and retrieve information. However, it is often difficult to locate the desired information, and it becomes necessary to spend considerable time determining how to access specific available data. This paper describes a method to quantitatively evaluate the usability of large-scale information-oriented websites and the effects of improvements made to the site design. This is achieved by utilizing the Cognitive Walkthrough for the Web and website modeling using Markov chains. We further demonstrate that we can greatly improve usability through simple modification of the link structure by applying our approach to an actual informational database website with over 40,000 records.

Active Queue Management (AQM) can maintain smaller queuing delay and higher throughput by purposefully dropping packets at the intermediate nodes. Most of the existing AQM schemes follow the probability dropping mechanism originated from Random Early Detection (RED). In this paper, we develop a novel packet dropping mechanism for AQM through designing a two-category classifier based on the Fisher Linear Discriminate approach. The simulation results show that the new scheme outperforms other well-known AQM schemes, such as RED, AdaptiveRED, AVQ, PI, REM etc., in the integrated performance. Additionally, our mechanism is simple since it requires few CPU cycles, which makes it suitable for the high-speed routers.

A b-bit SIMD functional unit has n k-bit sub-functional units in itself, where b = k n. It can execute n-parallel k-bit operations. However, all the b-bit functional units in a processor core do not necessarily execute n-parallel operations. Depending on an application program, some of them just execute n/2-parallel operations or even n/4-parallel operations. This means that we can modify a b-bit SIMD functional unit so that it has n/2 k-bit sub-functional units or n/4 k-bit sub-functional units. The number of k-bit sub-functional units in a SIMD functional unit is called sub-operation parallelism. We incorporate a sub-operation parallelism optimization algorithm into SIMD functional unit optimization. Our proposed algorithm gradually reduces sub-operation parallelism of a SIMD functional unit while the timing constraint of execution time satisfied. Thereby, we can finally find a processor core with small area under the given timing constraint. We expect that we can obtain processor core configurations of smaller area in the same timing constraint rather than a conventional system. The promising experimental results are also shown.

Several IP cells are available in the market to implement 8051-compliant microcontroller in embedded systems. Yet they frequently lack features that have become a key point in such systems, like power optimization. This paper aims at lowering the power consumption of an 8051 IP core while keeping unaltered performances, through Register Transfer Level techniques such as clustered clock gating, operand isolation and state encoding. This approach preserves the IP high-reusability and technology independence, as it only consists of modifications to the source VHDL code. A total power reduction of about 40% is achieved, with limited area overhead.

A new Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) scheme is proposed to suppress leakage current by two orders of magnitude in the SRAM's for sub-70 nm process technology with sub-1-V VDD. This two-order leakage reduction is caused from the cooperation of reverse body-to-source biasing and Drain Induced Barrier Lowering (DIBL) effects. In addition, metal shields are proposed to be inserted between the cell nodes and the bit lines not to allow the cell nodes to be flipped by the external bit-line coupling noise in this paper. A test chip has been fabricated to verify the effectiveness of the RRDSV scheme with the metal shields by using 0.18-µm CMOS process. The retention voltages of SRAM's with the metal shields are measured to be improved by as much as 40-60 mV without losing the stored data compared to the SRAM's without the shields.

A packet diversity scheme is introduced to increase uplink channel efficiency in a wireless network where forward error correction is used. The packet diversity allows neighbor base stations to receive uplink packets from a mobile terminal in order to increase the efficiency of the uplink channel. By allowing multiple base stations to receive the same packets, we can improve the error correction capability in an uplink channel. By incorporating the packet diversity we can reduce the parity overhead of each packet for a given tolerable loss probability, which improves the link efficiency.

This paper presents a novel approach to improving the IDDQ-based diagnosability of a CMOS circuit by dividing the circuit into independent partitions and using a separate power supply for each partition. This technique makes it possible to implement multiple IDDQ measurement points, resulting in improved IDDQ-based diagnosability. The paper formalizes the problem of partitioning a circuit for this purpose and proposes optimal and heuristic based solutions. The effectiveness of the proposed approach is demonstrated through experimental results.

This paper presents a wavelength lock system using a Z-cut quartz etalon supported at the middle point. The Z-cut quartz etalon possesses the cavity length modulation and the low temperature coefficient. We propose a Z-cut quartz etalon supported at the middle point in order to improve the modulation index and response time. The mechanism of the center supported Z-cut quartz etalon is described. We also show that the etalon possesses a high modulation index, a high Q factor, and a rapid response time in experimental results. A self-tuning dither oscillator realized by using quartz etalon is also described.

This paper proposes a Voice Activity Detection (VAD) algorithm using Radial Basis Function (RBF) network. The k-means clustering and Least Mean Square (LMS) algorithm are used to update the RBF network to the underlying speech condition. The inputs for RBF are the three parameters a Code Excited Linear Prediction (CELP) coder, which works stably under various background noise levels. Adaptive hangover threshold applies in RBF-VAD for reducing error, because threshold value has trade off effect in VAD decision. The experimental results show that the proposed VAD algorithm achieves better performance than G.729 Annex B at any noise level.

This paper presents an analytical model for the electromagnetic radiation in multi-microstrip lines covering the frequency range from 30 MHz to 1 GHz. The radiated emissions of multi-microstrip structure can be divided into the summation of radiated emissions of multi-individual microstrip structures. It is done by modelling the imperfect ground effect of the PCBs. Here we present a circuit model based on traditional transmission lines (TMLs) model. For more accurate analysis of the imperfect ground effect in multi-microstrip lines, we will divide the equivalent circuit model into N sections, based on transverse electromagnetic (TEM) assumption, to estimate the electromagnetic interference (EMI) of multi-microstrip lines. The quantitative value of induced current distribution along the ground return path depends on the physical size, geometry and length of ground trace. Measured data are presented to confirm the results of numerical analysis and the computer simulations with a software package based on the Finite Element Method. A knowledge of EMI source mechanism and their relationship to layout geometries is necessary to determine the essential features that must be modelled to estimate emissions in PCBs design.

A diagnosis technique is presented to locate at least one fault in a scan chain with multiple timing faults. This diagnosis technique applies Single Excitation (SE) patterns of which only one bit can be flipped even in the presence of multiple faults. By applying the SE patterns, the problem of simulations with unknown values is eliminated. The diagnosis result is therefore deterministic, not probabilistic. Experiments on the ISCAS benchmark circuits show that the average diagnosis resolution is less than ten scan cells.

In this paper, we present a model for evaluating the effectiveness of (2, 1, m) convolutional-code-based packet-level FEC, under the condition of a limited buffer size in which the number of available packets is restricted for recovery. We analytically derive the post-reconstruction receiving rate, i.e., the probability that a lost packet is received or recovered before the buffer limit is reached. We show numerical examples of the analytical results and demonstrate that the buffer size at the same level as m gives sufficient recovery performance.

Most of the proposed self-similar traffic models are asymptotic in nature. Hence, they are less effective in queueing-based performance evaluation when the buffer sizes are small. In this paper, we propose a short range dependent (SRD) process modelling by a generalized variance-based Markovian fitting to provide effective queueing-based performance measures when buffer sizes are small. The proposed method is to match the variance of the exact second-order self-similar processes. The fitting procedure determines the related parameters in an exact and straightforward way. The resultant traffic model essentially consists of a superposition of several two-state Markov-modulated Poisson processes (MMPPs) with distinct modulating parameters. We present how well the resultant MMPP could emulate the variance of original self-similar traffic in the range of the specified time scale, and could provide more accurate bounds for the queueing-based performance measures, namely tail probability, mean waiting time and loss probability. Numerical results show that both the second-order statistics and queueing-based performance measures when buffer capacity is small are more accurate than that of the variance-based fitting where the modulating parameters of each superposed two-state MMPP are equal. We then investigate the relationship between time scale and the number of superposed two-state MMPPs. We found that when the performance measures pertaining to larger time scales are not better than that of smaller ones, we need to increase the number of superposed two-state MMPPs to maintain the accurate and reliable queueing-based performance measures. We then conclude from the extensive numerical examples that an exact second-order self-similar traffic can be well represented by the proposed model.

In this paper, a dual level access scheme is proposed to provide two levels of access to the broadcast data; one to video signals protected for authorized users, another to extra information e.g. advertisements provided for the remaining users in the network. In the scheme, video signals in MPEG format are considered. The video contents are protected from unauthorized viewing by encrypting the DC coefficients of the luminance component in I-frames, which are extracted from the MPEG bit-stream. An improved direct sequence spread spectrum technique is used to add extra information to non-zero AC coefficients, extracted from the same MPEG bit-stream. The resultant MPEG bit-stream still occupies the same existing bandwidth allocated for a broadcast channel. At the receiver, the extra information is recovered and subtracted from the altered AC coefficients. The result is then combined with the decrypted DC coefficients to restore the original MPEG bit-stream. The experimental results show that less than 2.9% of the size of MPEG bit-stream was required to be encrypted in order to efficiently reduce its commercial value. Also, on average, with a 1.125 Mbps MPEG bit-stream, an amount of extra information up to 1.4 kbps could be successfully transmitted, while the video quality (PSNR) was unnoticeably degraded by 2.81 dB.

This paper proposes a decentralized and asynchronous replica control method based on a fair assignment of the variation in numerical data that has weak consistency for loosely coupled database systems managed or used by different organizations of human activity. Our method eliminates the asynchronous abort of already committed transactions even if replicas in all network partitions continue to process transactions when network partitioning occurs. A decentralized and asynchronous approach is needed because it is difficult to keep a number of loosely coupled systems in working order, and replica operations performed in a centralized and synchronous way can degrade the performance of transaction processing. We eliminate the transaction abort by fairly distributing the variation in numerical data to replicas according to their demands and updating the distributed variation using only asynchronously propagated update transactions without calculating the precise global state among reachable replicas. In addition, fairly assigning the variation of data to replicas equalizes the disadvantages of processing update transactions among replicas. Fairness control for assigning the data variation is performed by averaging the variation requested by the replicas. A simulation showed that our system can achieve extremely high performance for processing update transactions and fairness among replicas.