This manuscript proposes an FPGA by embedding a multidimensional switch topology onto a two-dimensional chip. We show, using Rent's Rule, that this procedure reduces the number of switches. Then we propose the actual procedure and demonstrate that this does not increase metal wire density critically.

A new Successive-Approximation ADC (Analog-to-Digital Converter) was designed which not only consumes little power, but also requires a small chip area. To achieve those goals, both comparator and internal DAC (Digital-to-Analog Converter) have been improved. The ADC was designed in a 1.2 µm CMOS double-poly double-metal n-well process. It performs 10-bit conversion with 67 dB SFDR. Power consumption and die area are 0.6 mW and 0.95 mm2, respectively. ADC was extensively simulated using Hspice to verify the desired performance.

In this paper, a dual level access scheme is proposed to provide two levels of access to the broadcast data; one to video signals protected for authorized users, another to extra information e.g. advertisements provided for the remaining users in the network. In the scheme, video signals in MPEG format are considered. The video contents are protected from unauthorized viewing by encrypting the DC coefficients of the luminance component in I-frames, which are extracted from the MPEG bit-stream. An improved direct sequence spread spectrum technique is used to add extra information to non-zero AC coefficients, extracted from the same MPEG bit-stream. The resultant MPEG bit-stream still occupies the same existing bandwidth allocated for a broadcast channel. At the receiver, the extra information is recovered and subtracted from the altered AC coefficients. The result is then combined with the decrypted DC coefficients to restore the original MPEG bit-stream. The experimental results show that less than 2.9% of the size of MPEG bit-stream was required to be encrypted in order to efficiently reduce its commercial value. Also, on average, with a 1.125 Mbps MPEG bit-stream, an amount of extra information up to 1.4 kbps could be successfully transmitted, while the video quality (PSNR) was unnoticeably degraded by 2.81 dB.

We propose a low-power resource-shared VLIW processor (RSVP) for future leaky nanometer process technologies. It consists of several single-way independent processor units (IPUs) that share parallel processor resources. Each IPU works as a variable-way VLIW processor sharing the parallel resources according to priorities of given tasks. RSVP allocates shared parallel resources to the IPUs cycle by cycle. It can minimize the number of NOPs that is wasting power. The performance per power (P3) of a 4-parallel 4-way RSVP that corresponds to four 4way VLIWs is 3.7% better than a conventional 4-parallel 4-way VLIW multiprocessor in the current 90 nm process. We estimate that the RSVP achieves 36% less leakage power and 28% better P3 in the future 25 nm process. We have fabricated an RSVP test chip that contains two IPU and a shared resource equivalent to two 2way VLIWs in a 180 nm process. It is functional at 100 MHz clock speed and its power is 130 mW.

The role of electric field in metal-induced lateral crystallization (MILC) of amorphous Si (a-Si) under limited Ni-supply condition has been investigated. The nominal lateral-growth rate was increased from 3.6 µm/h (no-electric field) to 23 µm/h at the positive electrode side and reduced to 2.8 µm/h at the negative electrode side in presence of the electric field of 20 V/cm. However, spontaneously nucleated needle-like Si crystals were observed in the enhanced positive electrode side, which have been found to be independent of the MILC. Further investigation under the condition where Ni in the supply region was removed on the way of crystallization revealed that the electric field enhanced crystallization greatly reduced. These results indicate that the electric field does not enhance the MILC growth but enhances the diffusion of Ni in a-Si which takes place prior to the MILC growth.

A novel cache-based packet-processing-engine (PPE) architecture that achieves low-power consumption and high packet-processing throughput by exploiting the nature of network traffic is proposed. This architecture consists of a processing-unit array and a bit-stream manipulation path called a burst stream path (BSP) that has a special cache mechanism called a process-learning cache (PLC). Network packets, which have the same information in their header, appear repeatedly over a short time. By exploiting that nature, the PLC memorizes the packet-processing method with all results (i. e. , table lookups), and applies it to other packets. The PLC enables most packets to skip the execution at the processing-unit array, which consumes high power. As a practical implementation of the cache-based PPE architecture, P-Gear was designed. In particular, P-Gear was compared with a conventional PPE in terms of silicon die size and power consumption. According to this comparison, in the case of current 0.13-µm CMOS process technology, P-Gear can achieve 100-Gbps (gigabit per second) packet-processing throughput with only 36.5% of the die size and 32.8% of the power consumption required by the conventional PPE. Configurations of both architectures for the 1- to 100-Gbps throughput range were also analyzed. In the throughput range of 10-Gbps or more, P-Gear can achieve the target throughput in a smaller die size than the conventional PPE. And for the whole throughput range, P-Gear can achieve a target throughput at lower power than the conventional PPE.

A new hybrid method for characterizing the irregular power/ground plane pair is developed in this paper by combining the conventional eigen-mode expansion method with the new-presented inverted composition method and a simple model order reduction. By the approach, the eigen-mode expansion method can be extended to the characteristics research of the power/ground plane pair with holes. In this gridless method, ports and decoupling capacitors can be arbitrarily placed on the plane pair. The numerical example demonstrates its good validity.

We have developed separation by bonding Si islands (SBSI) process for advanced CMOS LSI applications. In this process, the Si islands that become the SOI regions are formed by selective etching of the SiGe layer in the Si/SiGe stacked layers, and those are bonded to the Si substrate with the thermal oxide layers by furnace annealing. The etching selectivity for SiGe/Si and surface roughness after the SiGe etching were found to be improved by decreasing the HNO3 concentration in the etching solution. The thicknesses of the fabricated Si island and the buried oxide layer also became uniform by decreasing the HNO3 concentration. In addition, it was found that the space formed by SiGe etching in the Si/SiGe stacked layers was able to be filled with the thermal oxide layer without furnace annealing.

This paper deals with a TE plane wave reflection and transmission from a one-dimensional random slab by means of the stochastic functional approach. The relative permittivity of the random slab is written by a Gaussian random field in the vertical direction with finite thickness, and is uniform in the horizontal direction with infinite extent. An explicit form of the random wavefield is obtained in terms of a Wiener-Hermite expansion with approximate expansion coefficients (Wiener kernels) under a small fluctuation case. By using the first three terms of the random wavefield representation, the optical theorem is illustrated in figures for several physical parameters. It is then found that the optical theorem holds with good accuracy.

In this paper, an adaptive microphone array system with a two-stage adaptation mode controller (AMC) is proposed for high-quality speech acquisition in real environments. The proposed system includes an adaptive array algorithm, a time-delay estimator and a newly proposed AMC. To ensure proper adaptation of the adaptive array algorithm, the proposed AMC uses not only temporal information, but also spatial information. The proposed AMC is constructed with two processing stages: an initialization stage and a running stage. In the initialization stage, a sound source localization technique is adopted, and a signal correlation characteristic is used in the running stage. For the adaptive array algorithm, a generalized sidelobe canceller with an adaptive blocking matrix is used. The proposed algorithm is implemented as a real-time man-machine interface module of a home-agent robot. Simulation results show 13 dB SINR improvement with the speaker sitting 2 m distance from the home-agent robot. The speech recognition rate is also enhanced by 32% when compared to the single channel acquisition system.

Packet classification is important in fulfilling the requirements of differentiated services in next generation networks. One of interesting hardware solutions proposed to solve the packet classification problem is bit vector algorithm. Different from other hardware solutions such as ternary CAM, it efficiently utilizes the memories to achieve an excellent performance in medium size policy database; however, it exhibits poor worst-case performance with a potentially large number of policies. In this paper, we proposed an improved bit-vector algorithm named Condensate Bit Vector which can be adapted to large policy databases in the backbone network. Experiments showed that our proposed algorithm drastically improves in the storage requirements and search speed as compared to the original algorithm.

In this paper, we present a model for evaluating the effectiveness of (2, 1, m) convolutional-code-based packet-level FEC, under the condition of a limited buffer size in which the number of available packets is restricted for recovery. We analytically derive the post-reconstruction receiving rate, i.e., the probability that a lost packet is received or recovered before the buffer limit is reached. We show numerical examples of the analytical results and demonstrate that the buffer size at the same level as m gives sufficient recovery performance.

Poly-Si TFT (Thin Film transistor) fabricated below 170 using excimer laser crystallization of sputtered Si films was characterized. In particular, a gate insulator with a breakdown field exceeding 8 MV/cm was deposited by using ICP (Inductively Coupled Plasma) CVD (Chemical Vapor Deposition). A buffer layer possessing high thermal conductivity was inserted between the active channel and the plastic substrate, in order to protect the plastic substrate from the thermal energy of the laser and to increase adhesion of Si film on plastic. Using this method, we successfully fabricate TFT with a stable electron field-effect mobility value greater than 14.7 cm2/Vsec.

This paper proposes a decentralized and asynchronous replica control method based on a fair assignment of the variation in numerical data that has weak consistency for loosely coupled database systems managed or used by different organizations of human activity. Our method eliminates the asynchronous abort of already committed transactions even if replicas in all network partitions continue to process transactions when network partitioning occurs. A decentralized and asynchronous approach is needed because it is difficult to keep a number of loosely coupled systems in working order, and replica operations performed in a centralized and synchronous way can degrade the performance of transaction processing. We eliminate the transaction abort by fairly distributing the variation in numerical data to replicas according to their demands and updating the distributed variation using only asynchronously propagated update transactions without calculating the precise global state among reachable replicas. In addition, fairly assigning the variation of data to replicas equalizes the disadvantages of processing update transactions among replicas. Fairness control for assigning the data variation is performed by averaging the variation requested by the replicas. A simulation showed that our system can achieve extremely high performance for processing update transactions and fairness among replicas.

Spring-mass systems are widely used in computer animation to model soft objects. Although the systems can be numerically solved either by explicit methods or implicit methods, it has been difficult to obtain stable results from explicit methods. This paper describes detailed discussion on stabilizing explicit methods in spring-mass simulation. The simulation procedures are modeled as a linear digital system, and system stability is mathematically defined. This allows us to develop theories of simulation stability. The application of these theories to explicit methods allows them to become as stable as implicit methods. Furthermore, a faster explicit method is proposed. Experiments confirm the theories and demonstrate the efficiency of the proposed methods.

We propose a novel approach for designing a low power datapath in wireless communication systems. Especially, we focus on the digital FIR filter. Our proposed approach can reduce the power consumption and the circuit area of the digital FIR filter by optimizing the bitwidth of the each filter coefficient with keeping the filter calculation accuracy. At first, we formulate the constraints about keeping accuracy of the filter calculations. We define the problem to find the optimized bitwidth of each filter coefficient. Our defined problem can be solved by using the commercial optimization tool. We evaluate the effects of consuming power reduction by comparing the digital FIR filters designed in the same bitwidth of all coefficients. We confirm that our approach is effective for a low power digital FIR filter.

This paper presents an approach of logic mapping into LUT-Array-Based PLD where Boolean functions in the form of the sum of generalized complex terms (SGCTs) can be mapped directly. While previous mapping approach requires predetermined variable ordering, our approach performs mapping and variable reordering simultaneously. For the purpose, we propose a directed acyclic graph based on the multiple-valued decision diagram (MDD) and an algorithm to construct the graph. Our algorithm generates candidates of SGCT expressions for each node in a bottom-up manner and selects the variables in the current level by evaluating the sizes of SGCT expressions directly. Experimental results show that our approach reduces the number of terms maximum to 71 percent for the MCNC benchmark circuits.

A novel CMOS LC oscillator architecture combining an LC tuned oscillator and a ring structure is presented as a new design topology to deliver improved phase noise for multiphase applications. The relative enhancement in the phase noise is estimated using a linear noise modeling approach. A three-stage LC-ring oscillator fabricated in a 0.6 mm CMOS technology achieves measured phase noise of -132 dBc/Hz at 600 kHz offset from a 900 MHz carrier and dissipates 20 mW with a 2.5 V power supply.

In this paper, rail-to-rail OTA utilizing linear V-I conversion circuit whose input stage is composed of single channel MOSFETs, is proposed. The proposed conversion circuit is realized with two circuit blocks. One of them consists of a single MOSFET operating in plural regions and the other a pair of MOSFETs in saturation region and cut-off region. Combination of the circuit blocks achieves a linear voltage-current conversion for a rail-to-rail input signal. Rail-to-rail OTA is proposed using the proposed conversion circuit. HSPICE simulations are performed to verify the validity of the proposed V-I converter and rail-to-rail OTA. Simulation results indicate good performances. As an application example, 2nd-order LPF is realized using the proposed OTAs.

The linear operation of a HBT with a GaAs/InGaP composite collector structure is demonstrated. The composite collector structure allows for a thin collector design that is suitable for the linear operation of a HBT without critical degradation of the breakdown voltage. The load pull measurements under a 1.95 GHz WCDMA signal have shown that a composite-collector HBT with a 400-nm thick collector layer operates with power-added-efficiency (PAE) as high as 53% at VCE = 3.5 V as a result of improved distortion characteristics. Despite the thin collector design, collector-emitter breakdown voltage of 11 V was achieved even at current density of 10 kA/cm2. The composite-collector HBT has even greater advantage for future low voltage (< 3 V) applications where maintaining PAE and linearity becomes one of the critical issues.