In this paper, low-power design techniques of high-speed A/D converters are reviewed and discussed. Pipeline and parallel-pipeline architectures are treated as these are dominant architectures when required high sampling rate and high resolution with reasonable power dissipation. A systematic approach to the power optimization of pipeline and parallel pipeline ADC's is introduced based on models of noise analysis and response time of a building block in the multiple-stage pipeline ADC. Finally, the theoretical minimum of required power as functions of the sampling rate, resolution and SNR is discussed. The analysis shows that, with the developments of new circuits and systems to approach to the minimum, the power can be further reduced by a factor of more than 1/10 without changing the basic architectures.

Poly-Si TFT (Thin Film transistor) fabricated below 170 using excimer laser crystallization of sputtered Si films was characterized. In particular, a gate insulator with a breakdown field exceeding 8 MV/cm was deposited by using ICP (Inductively Coupled Plasma) CVD (Chemical Vapor Deposition). A buffer layer possessing high thermal conductivity was inserted between the active channel and the plastic substrate, in order to protect the plastic substrate from the thermal energy of the laser and to increase adhesion of Si film on plastic. Using this method, we successfully fabricate TFT with a stable electron field-effect mobility value greater than 14.7 cm2/Vsec.

We have fabricated Al-gate MOS capacitors with a Si quantum-dots (Si-QDs) floating gate, the number of dots was changed in the range of 1.6-4.81011 cm-2 in areal density with repeating the formation of Si dots and their surface oxidation a couple of times. The capacitance-voltage (C-V) characteristics of Si-QDs floating gate MOS capacitors on p-Si(100) confirm that, with increasing number of dots density, the flat-band voltage shift due to electron charging in Si-QDs is increased and the accumulation capacitance is decreased. Also, in the negative bias region beyond the flat-band condition, the voltage shift in the C-V curves due to the emission of valence electrons from intrinsic Si-QDs was observed with no hysterisis presumably because holes generated in Si-QDs can smoothly recombine with electrons tunneling through the 2.8 nm-thick bottom SiO2. In addition, we have demonstrated the charge retention characteristic improves in the Si-QDs stacked structure.

A new Successive-Approximation ADC (Analog-to-Digital Converter) was designed which not only consumes little power, but also requires a small chip area. To achieve those goals, both comparator and internal DAC (Digital-to-Analog Converter) have been improved. The ADC was designed in a 1.2 µm CMOS double-poly double-metal n-well process. It performs 10-bit conversion with 67 dB SFDR. Power consumption and die area are 0.6 mW and 0.95 mm2, respectively. ADC was extensively simulated using Hspice to verify the desired performance.

Path following circuits (PFC's) are circuits for solving nonlinear problems on the circuit simulator SPICE. In the method of PFC's, formulas of numerical methods are described by circuits, which are solved by SPICE. Using PFC's, numerical analysis without programming is possible, and various techniques implemented in SPICE will make the numerical analysis very efficient. In this paper, we apply the PFC's of the homotopy method to various nonlinear problems (excluding circuit analysis) where the homotopy method is proven to be globally convergent; namely, we apply the method to fixed-point problems, linear programming problems, and nonlinear programming problems. This approach may give a new possibility to the fields of applied mathematics and operations research. Moreover, this approach makes SPICE applicable to a broader class of scientific problems.

We propose a heuristic session allocation algorithm for switch with multiple output links, named SCDF (Shortest Class Delay First) algorithm. The proposed SCDF algorithm allocates a new session to an output link with the smallest estimated average packet delay among those of sessions that belong to the same class. The empirical study proves that SCDF shows the best performance comparing those of other competitive algorithms, in terms of balancing packet delay difference and maximizing throughput.

This paper presents an analytical model for the electromagnetic radiation in multi-microstrip lines covering the frequency range from 30 MHz to 1 GHz. The radiated emissions of multi-microstrip structure can be divided into the summation of radiated emissions of multi-individual microstrip structures. It is done by modelling the imperfect ground effect of the PCBs. Here we present a circuit model based on traditional transmission lines (TMLs) model. For more accurate analysis of the imperfect ground effect in multi-microstrip lines, we will divide the equivalent circuit model into N sections, based on transverse electromagnetic (TEM) assumption, to estimate the electromagnetic interference (EMI) of multi-microstrip lines. The quantitative value of induced current distribution along the ground return path depends on the physical size, geometry and length of ground trace. Measured data are presented to confirm the results of numerical analysis and the computer simulations with a software package based on the Finite Element Method. A knowledge of EMI source mechanism and their relationship to layout geometries is necessary to determine the essential features that must be modelled to estimate emissions in PCBs design.

A noise reduction technique that uses the linear prediction to remove noise components in speech signals has been proposed previously. The noise reduction works well for additive white noise signals, because the coefficients of the linear predictor converge such that the prediction error becomes white. In this method, the linear predictor is updated by a gradient-based algorithm with a fixed step-size. However, the optimal value of the step-size changes with the values of the prediction coefficients. In this paper, we propose a noise reduction system using the linear predictor with a variable step-size. The optimal value of the step-size depends also on the variance of the white noise, however the variance is unknown. We therefore introduce a speech/non-speech detector, and estimate the variance in non-speech segments where the observed signal includes only noise components. The simulation results show that the noise reduction capability of the proposed system is better than that of the conventional one with a fixed step-size.

A diagnosis technique is presented to locate at least one fault in a scan chain with multiple timing faults. This diagnosis technique applies Single Excitation (SE) patterns of which only one bit can be flipped even in the presence of multiple faults. By applying the SE patterns, the problem of simulations with unknown values is eliminated. The diagnosis result is therefore deterministic, not probabilistic. Experiments on the ISCAS benchmark circuits show that the average diagnosis resolution is less than ten scan cells.

This paper provides algorithms in order to solve an interval implicit function of the Poincare map generated by a continuous piece-wise linear (CPWL) vector field, with the use of interval arithmetic. The algorithms are implemented with the use of MATLAB and INTLAB. We present an application to verification of canards in two-dimensional CPWL vector field appearing in nonlinear piecewise linear circuits frequently, and confirm that the algorithms are effective.

The linear operation of a HBT with a GaAs/InGaP composite collector structure is demonstrated. The composite collector structure allows for a thin collector design that is suitable for the linear operation of a HBT without critical degradation of the breakdown voltage. The load pull measurements under a 1.95 GHz WCDMA signal have shown that a composite-collector HBT with a 400-nm thick collector layer operates with power-added-efficiency (PAE) as high as 53% at VCE = 3.5 V as a result of improved distortion characteristics. Despite the thin collector design, collector-emitter breakdown voltage of 11 V was achieved even at current density of 10 kA/cm2. The composite-collector HBT has even greater advantage for future low voltage (< 3 V) applications where maintaining PAE and linearity becomes one of the critical issues.

In this paper, rail-to-rail OTA utilizing linear V-I conversion circuit whose input stage is composed of single channel MOSFETs, is proposed. The proposed conversion circuit is realized with two circuit blocks. One of them consists of a single MOSFET operating in plural regions and the other a pair of MOSFETs in saturation region and cut-off region. Combination of the circuit blocks achieves a linear voltage-current conversion for a rail-to-rail input signal. Rail-to-rail OTA is proposed using the proposed conversion circuit. HSPICE simulations are performed to verify the validity of the proposed V-I converter and rail-to-rail OTA. Simulation results indicate good performances. As an application example, 2nd-order LPF is realized using the proposed OTAs.

A memory address allocation method for digital signal processors of indirect addressing with indexed auto-modification is proposed. At first, address auto-modification amounts for a given program are analyzed. And then, address allocation of program variables are moved and shifted so that both indexed and simple auto-modifications are effectively exploited. For further reduction in overhead codes, a memory address allocation method coupled with computational reordering is proposed. The proposed methods are applied to the existing compiler, and generated codes prove their effectiveness.

We have fabricated poly-Si/Si0.7Ge0.3/Si stacked gate on 4 nm-thick SiO2/Si(100), and examined the diffusion of Ge and impurities as a function of annealing temperature in the range of 800-1000 by energy dispersive X-ray spectroscopy (EDX) and secondary ion mass spectrometry (SIMS). It is reviealed that germanium atoms diffuse into 100 nm-thick silicon cap layer uniformly after 1000 annealing for 30 min and the crystallinity of As+ doped poly-SiGe is better than that of doped poly-SiGe. Also, in comparison with poly-Si gate MOS capacitors, we have confirmed that MOS capcitors with p+ and n+ SiGe gates show a 0.2 V reduction in the flat-band voltage for p+ gate and no change for n+ gate, with no increase in gate leakage current with respect to the oxide voltage. This result is attributable to the difference in the energy band structure between Si and Si0.7Ge0.3.

In this paper, we investigate packet loss and system dimensioning of feedback (FB) type wavelength division multiplexing (WDM) optical routers under asynchronous and variable packet length self-similar traffic. We first study the packet loss performance for two different types of WDM optical routers under asynchronous and variable packet length self-similar traffic. Based on simulation results, we demonstrate that a 1616 FB type WDM optical router employing more than 4 re-circulated ports without using void filling (VF) algorithm has better performance. We then present the system dimensioning issues of FB type WDM optical routers, by showing the performance of FB type WDM optical routers as a function of the number of re-circulated ports, buffer depth, re-circulation limit, basic delay unit in the fiber delay line optical buffers and traffic characteristics. The sensitivity of the mutual effects of the above parameters on packet loss is investigated in details. Based on our results, we conclude that the FB type WDM optical routers must be dimensioned with the appropriate number of re-circulated ports, re-circulation limits, buffer depth, and optimal basic delay unit in the fiber delay line optical buffers under relevant traffic characteristics to achieve high switching performance.

This paper presents the analysis of the stopping maneuver of the human driver by using a new three-dimensional driving simulator that uses CAVE, which provides stereoscopic immersive vision. First of all, the difference in the driving behavior between 3D and 2D virtual environments is investigated. Secondly, a GMDH is applied to the measured data in order to build a mathematical model of driving behavior. From the obtained model, it is found that the acceleration information has less importance in stopping maneuver under the 2D and 3D environments.

Live streaming media are delay sensitive and have limited allowable delays. Current conventional multicast protocols do not have a loss retransmission mechanism. Even though several reliable multicast protocols with retransmission mechanisms have been proposed, the long delay and high packet loss rate make them inefficient for live streaming. This paper proposes a multicast protocol focusing on the allowable delay called the QoS Multicast for Live Streaming (QMLS) protocol. QMLS routers are placed along the multicast tree to detect and retransmit lost packets. We propose a method that enables data recovery to be done immediately after lost packets are detected by the QMLS router and a method that reduces the unnecessary packets sent to end receivers. This paper discusses the mathematical analysis of the proposed protocol and compares it with other multicast protocols. The results reveal that our protocol is more effective in live streaming. Finally, we do a simulation to evaluate its performance and study the effect of consecutive losses. The simulation reveals that consecutive losses can slightly increase losses with our protocol.

We investigate strategies to improve the utterance verification performance using a 2-class pattern classification approach, including: utilizing N-best candidate scores, modifying segmentation boundaries, applying background and out-of-vocabulary filler models, incorporating contexts, and minimizing verification errors via discriminative training. A connected-digit database recorded in a noisy, moving car with a hands-free microphone mounted on the sun-visor is used to evaluate the verification performance. The equal error rate (EER) of word verification is employed as the sole performance measure. All factors and their effects on the verification performance are presented in detail. The EER is reduced from 29%, using the standard likelihood ratio test, down to 21.4%, when all features are properly integrated.

This paper describes a polarimetric feature extraction method from urban areas using the POLSAR (Polarimetric Synthetic Aperture Radar) data. The scattering characteristic of urban areas is different from that of natural distributed areas. The main point of difference is polarimetric correlation coefficient, because urban areas do not satisfy property of azimuth symmetry, Shh = Shv = 0. The decomposition technique based on azimuth symmetry can not be applied to urban areas. We propose a new model fit suitable for urban areas. The proposed model fit consists of odd-bounce, even-bounce and cross scattering models. These scattering models can represent the polarimetric backscatter from urban areas, and satisfy Shh 0 and Shv 0. In addition, the combination with the proposed model fit and the three component scattering model suited for natural distributed areas is examined. It is possible to apply the combined technique to POLSAR data which includes both urban areas and natural distributed areas. The combined technique is used for feature extraction of actual X-band POLSAR data acquired by Pi-SAR. It is shown that the proposed model fit is useful to extract polarimetric features from urban areas.

Digital signature is by far one of the most important cryptographic techniques used in the e-government and e-commerce applications. It provides authentication of senders or receivers and offers non-repudiation of transmission (senders cannot deny their digital signature in the signed documents and the document cannot be altered in transmission without being detected). This paper presents our implementation results of digital signature algorithms on IC cards by using byte-unit modular arithmetic algorithm method. We evaluated the performance of well-known ESIGN and RSA digital signature algorithms on the dedicated IC card chips and showed that ESIGN is more efficient than RSA.