A band-pass delta-sigma modulator (BPDSM) is a key building block to implement a digital intermediate frequency (IF) receiver in a wireless communication system. This paper proposes a time-interleaved (TI) switched-capacitor (SC) BPDSM architecture that consists of 5-stage TI blocks with recursive loop. The proposed TI BPDSM provides reduction in the clock frequency requirement by a factor of 5 and relaxes the settling time requirement to one-fourth of conventional approach. The test chip was designed and fabricated for a 30-MHz IF system with a 0.35-µm CMOS process. The measured peak SNR for a 200-kHz bandwidth is 63 dB while dissipating 75 mW from a 3.3-V supply and occupying 1.3 mm2.

This paper is focused on the measurement of the complex permittivity of a liquid phantom by the transmission line method using a coaxial line for measuring high-permittivity and high-loss materials. First, the complex permittivity of the liquid phantom material is measured under various physical lengths of the coaxial line for accurate measurement. Secondly, comparison between the measured result and the result obtained by the coaxial probe method is carried out in the frequency range from 0.5 to 3 GHz. Finally, the measurement error included in the complex permittivity is estimated quantitatively. The discussions lead to the conclusion that accurate measurement of the liquid material with high-permittivity and high-loss is possible by the presented method.

The objective of this research is to compare the performance of the Matrix Pencil Method (MPM) and well known root-MUSIC algorithm for high resolution DOA estimation. Performance of each technique in terms of the probability of resolution and SNR in the presence of noise is investigated. Simulation results show that the MPM has a superior resolution to the root-MUSIC algorithm.

We propose a method for reducing the size of a share in visual secret sharing schemes. The proposed method does not cause the leakage and the loss of the original image. The quality of the recovered image is almost same as that of previous schemes.

Quality of Service (QoS) provisioning is a new but challenging research area in the field of Mobile Ad hoc Network (MANET) to support multimedia data communication. However, the existing QoS routing protocols in ad hoc network did not consider a major aspect of wireless environment, i.e., mutual interference. Interference between nodes belonging to two or more routes within the proximity of one another causes Route Coupling. This can be avoided by using zone-disjoint routes. Two routes are said to be zone disjoint if data communication over one path does not interfere with the data communication along the other path. In this paper, we have proposed a scheme for supporting priority-based QoS in MANET by classifying the traffic flows in the network into different priority classes and giving different treatment to the flows belonging to different classes during routing so that the high priority flows will achieve best possible throughput. Our objective is to reduce the effect of coupling between routes used by high and low priority traffic by reserving zone of communication. The part of the network, used for high priority data communication, i.e, high priority zone, will be avoided by low priority data through the selection of a different route that is maximally zone-disjoint with respect to high priority zones and which consequently allows contention-free transmission of high priority traffic. The suggested protocol in our paper selects shortest path for high priority traffic and diverse routes for low priority traffic that will minimally interfere with high priority flows, thus reducing the effect of coupling between high and low priority routes. This adaptive, priority-based routing protocol is implemented on Qualnet Simulator using directional antenna to prove the effectiveness of our proposal. The use of directional antenna in our protocol largely reduces the probability of radio interference between communicating hosts compared to omni-directional antenna and improves the overall utilization of the wireless medium in the context of ad hoc wireless network through Space Division Multiple Access (SDMA).

A VLSI-specific wavelet processing technique has been developed and implemented as a processor in accordance with the JPEG2000 specification. This proposed procedure of discrete wavelet transforms uses an altered calculation equations and makes use of intermediate results through wavelet calculation. The implementation of the proposed procedure is capable of realizing a highly efficient DWT for large size images in spite of using low hardware costs and a small size buffering memory. In order to obtain fast EBCOT processing, three types of parallel processing are introduced in the EBCOT architecture. The processor performs compression of 720480 pixels images with the speed of 30 frames per second (fps) at a required operating frequency as low as 32 MHz or lower. Furthermore, it need not divide an image into tiles so that the problem of deterioration of image quality due to tile division does not occur. A prototype of this processor has been fabricated in a 0.25-µm 5-layer CMOS process. The chip is 10.210.4 mm2 in size and consumes 2.0 W when supplied with 2.5 V and 32 MHz.

This paper formulates functions generating four kinds of binary sequence sets of length 2n with zero correlation zone, which have been discussed for approximately synchronized CDMA systems without co-channel interference nor influence of multipath. They are logic functions of a binary vector of order n, expressed by EXOR and AND operations.

This paper describes the implementation of an optical switch control system for best-effort multi-wavelength path assignment in DWDM networks based on the SLAMNet (Statistical Lambda Multiplexing Network) that provides dynamic path assignment capabilities without signaling between nodes. The platform of the prototype system consists of a hardware and operation system that are commercially available in the market. We developed the control functions of the SLAMNet as application software to run on the platform. The control function monitors the instantaneous bit rate of the traffic in the wavelength paths and autonomously sets up or releases optical channels in an independent and distributed manner. We demonstrate that the prototype system achieves a switching time of less than 28 milliseconds, which can respond to the burst traffic that emerges and disappears within a fraction of a second in backbone networks. This result indicates that the network architecture SLAMNet is applicable for best-effort multi-wavelength path assignment as an overlay network built on a legacy infrastructure that has no signaling capabilities. The design description and detail hardware configuration are presented. The control mechanisms and performance analysis are also included.

A power-aware interconnect circuit design--called µI/O architecture--has been developed to provide low-cost system solutions for System-on-Chip (SoC) and System-in-Package (SiP) technologies. The µI/O architecture provides a common interface throughout the module enabling hierarchical I/O design for SoC and SiP. The hierarchical I/O design allows the driver size to be optimized without increasing design complexity. Moreover, it includes a signal-level converter for integrating wide-voltage-range circuit blocks and a signal wall function for turning off each block independently--without invalid signal transmission--by using an internal power switch.

Recently, Kuwakado and Tanaka proposed a transitive signature scheme for directed trees. In this letter, we show that Kuwakado-Tanaka scheme is insecure against a forgery attack, in which an attacker is able to forge edge signatures by composing edge signatures provided by a signer.

This paper proposes a hardware/software cosynthesis algorithm for processors with heterogeneous registers. Given a CDFG corresponding to an application program and a timing constraint, the algorithm generates a processor configuration minimizing area of the processor and an assembly code on the processor. First, the algorithm configures a datapath which can execute several DFG nodes with data dependency at one cycle. The datapath can execute the application program at the least number of cycles. The branch and bound algorithm is applied and all the number of functional units and memory banks are tried. For an assumed number of functional units and memory banks, an appropriate number of heterogeneous registers and connections to functional units and registers are explored. The experimental results show effectiveness and efficiency of the algorithm.

Software agents are knowledgeable, autonomous, situated and interactive software entities. Agents' interactions are of special importance when a group of agents interact with each other to solve a problem that is beyond the capability and knowledge of each individual. Efficiency, performance and overall quality of the multi-agent applications depend mainly on how the agents interact with each other effectively. In this paper, we suggest an agent model by which we can clearly distinguish different agent's interaction scenarios. The model has five attributes: goal, control, interface, identity and knowledge base. Using the model, we analyze and describe possible scenarios; devise the appropriate reasoning and decision making techniques for each scenario; and build a library of reasoning and decision making modules that can be used readily in the design and implementation of multiagent systems.

This paper presents time slot assignment algorithms applicable to uplink of space division multiple access (SDMA)/time division multiple access (TDMA) systems with adaptive antennas. In the time slot assignment process for a new terminal in a cell, we consider not only the signal quality of the new terminal but also that of active terminals in the same cell. Intra-cell hand over is performed for an active terminal when its signal quality deteriorates. We evaluate the blocking and forced termination probabilities for pure TDMA systems, sectorized systems, and SDMA/TDMA systems in cellular environments by computer simulations. The simulation results show that the SDMA/TDMA systems have much better performance than the pure TDMA and sectorized systems.

In this paper, we design and implement a fast asynchronous embedded CISC microprocessor, A8051, introducing well-tuned pipeline architecture and enhanced control schemes. This work shows an asynchronous design methodology for a CISC type processor, handling the complicated control structure and various instructions. We tuned the proposed architecture to the 5-stage pipeline, reducing the number of idle stages. For the work, we regrouped the instructions based on the number of the machine cycles identified. A8051 has three enhanced control features to improve the system performance: multi-looping control of the pipeline stage, variable length instruction register to get a multiple word instruction in a time, and branch prediction accelerating. The proposed A8051 was synthesized to a gate level design using a 0.35 µm CMOS standard cell library. Simulation results indicate that A8051 provides about 18 times higher speed than the traditional Intel 8051 and about 5 times higher speed than the previously designed asynchronous 8051. In power consumption, core of A8051 shows 15 times higher MIPS/Watt than the synchronous H8051.

A method for estimating the bit-error rate (BER) of turbo codes called the Monte Carlo distance spectrum method is proposed. Testing this method shows that the estimated BER curves closely approximate the results of a Monte Carlo simulation.

A new speaker feature extracted from multi-wavelet decomposition for speaker recognition is described. The multi-wavelet decomposition is a multi-scale representation of the covariance matrix. We have combined wavelet transform and the multi-resolution singular value algorithm to decompose eigenvector for speaker feature extraction not at the square matrix. Our results have shown that this multi-wavelet feature introduced better performance than the cepstrum and Δ-cepstrum with respect to the percentages of recognition.

In low-power embedded processors design, stand-by power constraint is also important with average power and operation frequency. Multi-threshold-voltage cells are used in the design and the ratio of low-Vth cells should be controlled. On the other hand, physical synthesis flow is indispensable to achieve high performance and short design time. This paper proposes a physical synthesis methodology under the restriction of maximum low-Vth cell ratio. The experimental results show that our method can achieve only 4 MHz slower logic within 5% margin of the target low-Vth ratio. We have applied this design flow in an application processor design and the designed processor demonstrates 360 MIPS at 200 MHz only with 80 mW at 1.0 V, namely 4500 MIPS/W and 4.2 mA leakage current without any power-cut mode.

We apply a selective-sets resizable cache and a complete hierarchy SRAM for the high-performance and low-power RISC CPU core. The selective-sets resizable cache can change the cache memory size by varying the number of cache sets. It reduces the leakage current by 23% with slight degradation of the worst case operating speed from 213 MHz to 210 MHz. The complete hierarchy SRAM enables the partial swing operation not only in the bit lines, but also in the global signal lines. It reduces the current consumption of the memory by 4.6%, and attains the high-speed access of 1.4 ns in the typical case.

A multiple channel active noise control (ANC) system with several secondary sources, error sensors, and reference sensors has been used for complicated noise fields. Centralized multiple channel ANC systems have been proposed, however implementation of such systems becomes difficult according to increase of control points. Distributed multiple channel ANC systems which have more than a controller are considered. This paper proposes a new implementation of distributed multiple channel ANC systems based on simultaneous equations methods. In the proposed algorithm, communications between controllers are permitted to distribute the computational burden and to improve the performance of noise reduction. This algorithm shows good performances for noise cancellation and tracking of changes in the error paths.

In this paper, we propose the CMOS implementation of a multiple-valued memory cell using -shaped negative-resistance devices. We first propose the construction of a multiple-stable circuit that consists of -shaped negative-resistance devices from four enhancement-mode MOSFETs without a floating voltage source, and connect this in parallel with a unit circuit. It is shown that the movement of -shaped negative-resistance characteristics in the direction of the voltage axis is due to voltage sources. Furthermore, we propose the construction of a multiple-valued memory cell using a multiple-stable circuit. It is shown that it is possible to write and hold data. If the power supply is switched on, it has a feature which enables operation without any electric charge leakage. It is possible, by connecting -shaped negative-resistance devices in parallel, to easily increase the number of multiple values.