In this paper, the electromagnetic scattering from a cylinder with a computer-generated random rough surface is analyzed by a numerical simulation method. The validity of the proposed numerical method is confirmed by comparing the present numerical results with those calculated by the perturbation method to second order and its Pade approximation. It is shown that the present proposed method can be applied to the case where the surface roughness becomes relatively large.

Multi-cycle paths are paths between registers where 2 or more clock cycles are allowed to propagate signals, and the detection of multi-cycle paths is important in deciding proper clock period, timing verification and logic optimization. This paper presents a satisfiability-based multi-cycle path detection method, where the detection problems are reduced to CNF formulae and the satisfiability is checked using SAT provers. We also show heuristics on conversion from multi-level circuits into CNF formulae. We have applied our method to ISCAS'89 benchmarks and other sample circuits. Experimental results show the remarkable improvements on the size of manipulatable circuits.

The subject of this study is to propose a new structure that can realize simultaneously high breakdown voltage and high packing density for both Nch low side switch and Pch high side switch in 200 V class rating. As the conventional techniques for the electric field relaxation, the structure of field plate, field ring and RESURF are well known, but these techniques are inadequate for the high packing density because they are the techniques in surface region. In order to conquer this subject, it is necessary to relax the electric field in the deep region. The electric field relaxation was investigated by device simulation. In the Nch low side switch the electric field is relaxed by buried oxide film in SOI structure. However, electric field relaxation cannot be realized only by adapting the SOI structure for Pch high side switch. Then we tried to insert an intrinsic layer between P-drift layer and the buried oxide film in order to spread the depletion layer in the deep region. This spread depletion layer by intrinsic layer and the depletion layer by field plate connect vertically, and the dosage of the ion implantation for drift layer can be set to two times higher than the case without intrinsic layer. As the results, it was revealed that the SOI structure with intrinsic layer is effective to achieve this subject. Furthermore, by fabricating both Nch low side switch and Pch high side switch on intrinsic SOI substrate, breakdown voltage more than 250 V were achieved.

An averaged intensity peak profile of light scattered from a random medium depends on a thickness of a sample as well as parameters such as a volume fraction and a size of particles composing the medium. We used this dependence to measure a depth profile varied in the random medium. We demonstrated the possible simultaneous measurement of a transport mean free path and a depth of an aqueous suspension of titanium particles.

This letter proposes a modified synchronous acquisition method using code-orthogonalizing filters (COFs) in an asynchronous direct sequence (DS) / CDMA. Improvements on the average acquisition time for several conditions are shown.

In this paper, we consider the coherent radar detection of rapid fluctuating signals in the Gaussian noise. This problem has been previously solved by employing the GLR technique, but we use the ALR to improve the detection performance. So, after deriving an approximate ALR detector, we compare the new detector with the GLR and Square-law detectors and we show its superiority.

In this paper, we present a low-power and area-efficient design method of embedded high-speed A/D converters for mixed analog-digital system LSI's. As the A/D converter topology, a 1.5 bit/stage interleaved pipeline A/D converter is employed, because the basic topology covers a wide range of specifications on the conversion frequency and the resolution. The design method determines the minimum DC supply current, the minimum device sizes and the minimum number of channels to meet the precision given by the specification. This paper also points out that the interleaved pipeline structure is very effective for low-power design of high-speed A/D converters whose sampling frequency is over 100 MHz.

An 1 V, 50 MHz, 16-bit DSP core was developed using a 0.25-µm Dual Vt library, SRAM, and Mask ROM tailored for 1 V operation. The core speed was 41% enhanced using an alternate MAC and 2-stage execution pipeline. A 1.0 V to 1.5 V voltage up converter with 59% power efficiency and a 450 ps 1 V to 2.5 V level converter were implemented. An new long wire delay estimation method enhanced the synthesis. The measured power consumption at 0.9 V was 8.7 mW, which was 40% less than the power of the normal library's at 1.3 V, when the PSI-CELP CODEC firmware was run at 40 MHz.

Four different types of GaAs HEMT DCFL static delay latches based on NOR gates were developed. Eight different types of low-voltage, low-power, high-speed delay flip-flops (D-FFs) were constructed using two delay latches of different types. These delay latches and D-FFs were designed using 0.25-µm n-AlGaAs/i-InGaAs HEMT technology, and their characteristics were evaluated by SPICE simulation. A positive-edge D-FF, called "1P0P," was fabricated and tested. Its operating clock frequency, power dissipation, power delay product, and phase margin were measured as a function of supply voltage VD. The dissipation was almost proportional to VD for VD up to 1.2 V. The "1P0P" D-FF consumed only 2.03 mW at a clock frequency of 5.17 GHz (i.e., at a data rate of 5.17 Gbps) and a VD of 0.6 V, so the power delay product was 0.196 pJ. For a (29-1) pseudo-random signal, a maximum frequency of 7.15 GHz was obtained at a VD of 1.1 V, with dissipation of 6.02 mW and an error rate of less than 10-9. Clear, wide eye openings were obtained at frequencies up to 7.15 GHz. A sufficiently high phase margin of 180 was obtained with a data rate of 5 Gbps at a VD of 0.6 V.

A novel adaptive algorithm based on pilot channel (PCA) for MMSE multiuser detection in downlink CDMA is proposed in this paper. This algorithm uses the information in pilot channel to compute the desired weight vector directly. Compared with conventional adaptive algorithms and blind algorithms, it does not require training sequences nor channel estimation. Analysis shows that the weight vector obtained by the PCA algorithm converges to the Wiener solution globally and its computational complexity is O(N2). Simulation results show that the PCA algorithm can adapt rapidly to the changing environment. The steady state performance can be enhanced by increasing the transmitted power in pilot channel, but is worse than that of conventional recursive least-square (RLS) algorithm in decision-directed mode. Also, performance of the adaptive MMSE detector is much better than that of conventional RAKE receiver.

In this letter, the constant amplitude transmission for orthogonal multicode systems is discussed. In order to obtain the high power efficiency, we require the high power amplifier which has non-linear characteristic. The nonlinear distortion, however, may occur because of the multicode signals having large amplitude fluctuations. If we can achieve the constant amplitude transmission, the nonlinear distortion can be neglected. In this letter, I investigate the property of the information bit streams that can achieve the constant amplitude transmission and show that the bent sequences can achieve the constant amplitude transmission.

This paper investigates the influence of the number of antennas, the angle difference between the direction of arrival (DOA) of the desired signal and those of interfering signals, and the antenna arrangement on the BER performance of the coherent adaptive antenna array diversity (CAAAD) receiver in the wideband DS-CDMA (W-CDMA) reverse link. Experiments assuming high-rate interfering users were conducted in a radio anechoic room using a three-sectored antenna with a 120-degree beam (maximum number of antennas was six). The experimental results showed that the degree to which the interference was suppressed from high-rate users of the CAAAD receiver was significantly increased by increasing the number of antennas, especially when the number of interfering users was larger than degree of freedom of the CAAAD. It was also verified that although the BER performance of the CAAAD receiver significantly improved compared to a single sectored antenna, the improvement remarkably decreased when the DOA difference between the desired signal and interfering signals was within approximately 10-15 degrees irrespective of the number of antennas. Finally, we show that the BER performance difference between the linear and conformal arrangements was small when using the three-sectored antenna.

A new timing estimation algorithm for asynchronous DS/CDMA multiuser communication system is proposed in this paper. The algorithm is based on the Minimum Variance Distortionless Response (MVDR) beamforming technique that minimizes the beamformer's output power with the constraint that only the signal with exact timing is distortionlessly passed. Exploiting the characteristics that the MVDR beamformer's output power is severely degraded according to erroneous timing estimation, we develop an efficient algorithm to estimate each user's timing by scanning the beamformer's output power variation. Compared to the maximum a posteriori (MAP) or maximum likelihood (ML) based multiuser timing estimator, the complexity is extensively reduced by separating the multi-dimensional optimization problem into several one-dimensional optimization problems. Furthermore, the algorithm is computationally feasible than the subspace-based timing estimator since no eigendecomposition (EVD) is required. Moreover, the proposed algorithm is near-far resistant since the MVDR beamformer is inherently energy independent to the interferers.

A constant amplitude transmission scheme for multicode wideband CDMA systems is proposed. Multicode wideband CDMA systems result in large amplitude fluctuation because the multicode signal is the sum of constituent code channel signals. This large amplitude fluctuation brings out large non-linear distortion and then, if unaccounted, can significantly degrade the bit error rate (BER) performance. Constant amplitude transmission, achieved by using a Walsh code and parity generator, is proposed to combat the large amplitude fluctuation and reduce the peak-to-average power ratio (PAPR). Unlike other constant amplitude transmission scheme, the proposed scheme does not use a redundant code channel. Computer simulation results show that the proposed scheme improves BER performance significantly and that the proposed scheme is extremely effective to the non-linear distortion of high power amplifier (HPA).

A fully balanced (FB) transconductor using two multi-input single-ended (SE) CMOS transconductors is proposed, where the transconductors use MOS transitors operating in a triode region for achieving a wide linear input-range. SE circuits are easier to design than differential circuits and inherently reject common-mode (CM) signals. The multi-input structure is used to make a CM feedback loop and to determine an output CM voltage. A high-output-resistance current mirror is used in converting a differential signal to a single-ended signal in order to achieve a high common-mode rejection ratio (CMRR) and a high output-resistance of the transconductor. The FB transconductor achieves a 2-Vpp linear input range at a 2.5-V power supply and consumes 1.74 mA. The output resistance of the FB transconductor is 2 MΩ. It operates at 2 V with a linear input-range of 1.2 Vpp and at 1.6 V with a linear input-range of 0.9 Vpp. A 2.5-V 2.5-MHz FB Gm-C filter using the FB transconductors achieved a CMRR of 45 dB and a passband IIP3 of 32 dBm.

This paper presents a new design of spread spectrum signals with the minimally sufficient dimension from the view point of frequency diversity. Letting the signature signal duration and the bandwidth be denoted by T and B, respectively, we can nominally represent a signature signal of either Direct Sequence (DS) or MultiCarrier (MC) spread spectrum system as the sum of N=BT sinusoidal signal units with their frequencies separated by 1/T or its multiples. In our design,assuming the maximum expected channel delay spread σd « T as usual, one signature signal viewed in the frequency domain is made up of the minimum number K 2πσdB of sinusoidal signal units which are arranged so as there is placed at least one unit in coherence bandwidth 1/(2πσd) in which the fading channel transfer function has strong correlation. Although the signature signal does not make use of all the units in the given frequency domain as in the ordinary spread spectrum systems, but uses only skipped units, it can be shown that almost the same frequency diversity effect is attained. And it is also shown that the immunity to the external interfering signals is by no means inferior. If every L=N/K T/(2πσd) consecutive sinusoidal signal units are assigned to the K signal units of a signature signal, L different signature signals are simultaneously available mutually orthogonal when the synchronous demodulation is performed in the same T period. We call each of the orthogonal sinusoidal signal sets a Frequency Devision (FD) signal set. Now, CDMA can be independently realized on each of the L FD signal sets provided the operation is synchronous or quasi-synchronous with respect to the symbol demodulation (or signature) period. Partitioning the simultaneous users among the FD sets, it is possible to decrease the number of CDMA users to be processed, retaining the total number of simultaneous users. Owing to this effect, the multiple access performance for the FD/CDMA system is shown to be superior to that of the ordinary DS or MC/CDMA system, assuming matched filter reception based on the complete estimation of the channel characteristics for the both cases. The decrease of the number of CDMA users per FD set makes it practical for the receiver to employ multiple access interference cancellation and even the maximum likelihood detection. Curiously, any FD signal set can be represented in the time domain as L repetition of a sequence with its period equal to K in the number of 1/B duration time chips.

Most distributed systems are based on either the C/S (Client/Server) model or the P-to-P (Peer to Peer) model. In C/S based distributed systems, a client invokes a server and waits for the server reply. Because of this sequential nature, C/S based distributed systems can be implemented by the RPC (Remote Procedure Call) scheme. Most tools for developing distributed objects are based on the RPC scheme. Whereas, in P-to-P based distributed systems, each distributed objects work concurrently, by exchanging asynchronous messages, without waiting for the receiver's action. To implement these P-to-P distributed systems, the RPC scheme is not powerful enough, and the active object model using asynchronous messages is suitable. This paper explains the pure Java library CAPE for developing P-to-P based distributed active object systems.

In this paper, we discuss the access control in multimedia CDMA ALOHA protocol. We introduce a new algorithm for the access control based on Modified Channel Load Sensing Protocol (MCLSP) in an integrated voice and two different classes of data users, high bit rate and low bit rate, exist in a multi-code CDMA Slotted ALOHA system. With our new algorithm, we show that the throughput of high bit rate data users, as well as, the total throughput of the data medium can be optimized and take a maximum value even at high values of offered loads. We also investigate the performance when voice activity detection (VAD) is considered in voice transmission.

Generating state spaces is one of important and general methods in the analysis of Petri nets. There are two reasons why state spaces of Petri nets become so large. One is concurrent occurring of transitions, and the other is periodic occurring of firing sequences. This paper focuses on the second problem, and proposes a new algorithm for exploring state spaces of finite capacity Petri nets with large capacities. In the proposed algorithm, the state space is represented in the form of a tree such that a set of markings generated by periodic occurrences of firing sequences is associated with each node, and it is much smaller than the reachability graph.

We introduce a high-level synthesis framework to automatically synthesize asynchronous circuits, especially speed-independent circuits, from a concurrent programming language called ALPEH. ALPEH is a high-level concurrent algorithmic specification that can model complex concurrent control flows, logical and arithmetic computations, and communications in easy way. This specification language has been developed to be translated into a Petri net. The major contribution of this paper is the generation of globally optimized control circuits during preserving neat formalism in the specification.