The hardware-software codesign of distributed embedded systems is a more challenging task, because each phase of codesign, such as copartitioning, cosynthesis, cosimulation, and coverification must consider the physical restrictions imposed by the distributed characteristics of such systems. Distributed systems often contain several similar parts for which design reuse techniques can be applied. Object-oriented (OO) codesign approach, which allows physical restriction and object design reuse, is adopted in our newly proposed Distributed Embedded System Codesign (DESC) methodology. DESC methodology uses three types of models: Object Modeling Technique (OMT) models for system description and input, Linear Hybrid Automata (LHA) models for internal modeling and verification, and SES/workbench simulation models for performance evaluation. A two-level partitioning algorithm is proposed specifically for distributed systems. Software is synthesized by task scheduling and hardware is synthesized by system-level and object-oriented techniques. Design alternatives for synthesized hardware-software systems are then checked for design feasibility through rapid prototyping using hardware-software emulators. Through a case study on a Vehicle Parking Management System (VPMS), we depict each design phase of the DESC methodology to show benefits of OO codesign and the necessity of a two-level partitioning algorithm.

This paper proposes an efficient reduction method for a substrate network model, which is extracted from layout data, to analize a substrate coupling noise. The proposed method adopts in a reduction operation a hierarchic structure of a substrate RC network model, a computational procedure using matrix elements, and an expression of admittance as polynominal in complex frequency s=jω. These techniques improve computational efficiency and are suitable for an implementation. In the example of a triple well CMOS circuit, a reduced model, from 7500 nodes to 5 nodes, has less than 25% errors up to 1 GHz.

Multilayer feedforward neural network (MFNN) trained by the backpropagation (BP) algorithm is one of the most significant models in artificial neural networks. MFNNs have been used in many areas of signal and image processing due to high applicability. Although they have been implemented as analog, mixed analog-digital and fully digital VLSI circuits, it is still difficult to realize their hardware implementation with the BP learning function efficiently. This paper describes a special BP algorithm for the logic oriented neural network (LOGO-NN) which we have proposed as a sort of MFNN with quantized weights and multilevel threshold neurons. Both weights and neuron outputs are quantized to integer values in LOGO-NNs. Furthermore, the proposed BP algorithm can reduce high precise calculations. Therefore, it is expected that LOGO-NNs with BP learning can be more effectively implemented as digital type circuits than the common MFNNs with the classical BP. Finally, it is shown by simulations that the proposed BP algorithm for LOGO-NNs has good performance in terms of the convergence rate, convergence speed and generalization capability.

This paper presents a method of statistical system optimization. The method uses a constraint generation, which is a design methodology based on a hierarchical top-down design, to give specifications to sub-circuits of the system. The specifications are generated not only to reduce the costs of sub-circuits but also to take adequate margin to achieve enough yield of the system. In order to create an appropriate amount of margin, a term which expresses a statistical figure based on Mahalanobis' distance is added to the constraint generation problem. The method is applied to a PLL, and it is confirmed that the yield of the lock-up time reaches 100% after the optimization.

In this paper, we propose a fine grain Cooled Logic architecture for low-power oriented processors. Cooled Logic detects, in novel hardware method with dual-rail logic, functional blocks to be active, and stops clocks to each of the functional blocks in order to make it inactive at certain periods. To confirm the effectiveness of our approach, we design a 4-bit and a 16-bit event-driven array multipliers, and analyze their power consumption by the HSPICE simulator. As a result, it is shown that Cooled Logic has a tendency to reduce power consumptions in both the functional blocks and the clock drivers of the multipliers.

A new architecture-based Dynamically Programmable Arithmetic Array processor (DPAA) is proposed for general purpose Digital Signal Processing applications. Parallelism and pipelining are achieved by using DPAA, which consists of various basic arithmetic blocks connected through a code-division multiple access bus interface. The proposed architecture poses 100% interconnection flexibility because connections are done virtually through code matching instead of physical wire connections. Compared to conventional multiplexing architectures, the proposed interconnection topology consumes less chip area and thus, more arithmetic blocks can be incorporated. A 16-bit prototype chip incorporating 10 multipliers and 40 other arithmetic blocks had been implemented into a 4.5 mm 4.5 mm chip with 0.6 µm CMOS process. DPAA also features its simple programmability, as numerical formula can be used to configure the processor without programming languages or specialized CAD tools.

In this paper, an architecture of multi-threaded processor for embedded systems is proposed and evaluated comparing with other processors for embedded systems. The experimental results show the trade-off of hardware costs and execution times among processors. Taking proposed multi-threaded processor into account as an embedded processor, design space of embedded systems are enlarged and more suitable architecture can be selected under some design constraints.

This paper proposes a new heuristic algorithm FMDB for the minimum initial marking problem MIM of Petri nets: "Given a Petri net and a firing count vector X, find an initial marking M0, with the minimum total token number, for which there is a sequence δ of transitions such that each transition t appears exactly X(t) times in δ, the first transition is firable on M0 and the rest can be fired one by one subsequently. " Experimental results show that FMDB produces better solutions than any known algorithm.

Optimization procedure on higher order Delta-sigma (ΔΣ) modulator coefficients is proposed. The procedure is based on the higher order ΔΣ modulator stability judgement method. The application specification can be satisfied with the proposed method. The 4th order modulator examples are illustrated. Optimized coefficients and its behavior model simulation results demonstrated that this methodology is suitable for the design of higher order ΔΣ AD converter. The coefficients tolerance up to 2% is allowed for switched-capacitor implementation, with not more than 3.5 dB SNR (Signal to Noise Ratio) degradation. The optimized coefficients improves 2 to 3 bit of the modulator's resolution than the previous proposed algorithm, and remains the stable input limit satisfies the original design requirement.

In this paper, we discuss power spectrum overlapping of wideband/narrowband signals and wideband/wideband signals for increasing transmission efficiency. Here, in order to eliminate cross signal interference among those signals, we propose a generalized zero-forcing type decorrelating detection. Our numerical results show that, with the decorrelating detector, the overlapped wideband/wideband signal transmission can much improve the transmission efficiency. This implies that, for a given frequency bandwidth, in order to increase the information transmission rate, we should employ two different kinds of direct sequence spread spectrum-based signals with each power spectrum appropriately overlapped, not taking a single carrier-based approach nor an orthogonal multi-carrier approach.

First, we show that the necessary and sufficient condition for the existence of a balanced bowtie decomposition of the complete tripartite multi-graph λ Kn1,n2,n3 is (i) n1=n2=n3 0 (mod 6) for λ 1,5 (mod 6), (ii) n1=n2=n3 0 (mod 3) for λ 2,4 (mod 6), (iii) n1=n2=n3 0 (mod 2) for λ 3 (mod 6), and (iv) n1=n2=n3 2 for λ 0 (mod 6). Next, we show that the necessary and sufficient condition for the existence of a balanced trefoil decomposition of the complete tripartite multi-graph λ Kn1,n2,n3 is (i) n1=n2=n3 0 (mod 9) for λ 1,2,4,5,7,8 (mod 9), (ii) n1=n2=n3 0 (mod 3) for λ 3,6 (mod 9), and (iii) n1=n2=n3 3 for λ 0 (mod 9).

In this letter, we present a method to generate sets of sequences suitable for multicode transmission in quasi-synchronous (QS) CDMA systems. We focus on Gold code but extension to orthogonal Gold code is straightforward. We show that by appropriate classification of sequences, it is possible to have sets whose cross correlation is small in QS situations.

In this article, we shall propose an efficient anonymous channel protocol for wireless communications. The most important feature of our proposed protocol has the property of untraceability. In our scheme, the mobile stations (MSs) and the home network (HN) must authenticate each other. Moreover, the HN is untraceable in such a way that supports location anonymity and MSs identity anonymity for MSs roaming, dynamic channel assignment and broadcasting. Compare our protocol with Juang et al.'s protocol, our mobile agent communication cost is 3m which is more efficient than the Juang et al.'s protocol 5m. At the same time, our mobile agent computation cost is 2Th which is also more efficient than the Juang et al.'s protocol 1Tpublic+1Th. We can avoid employing public key cryptography in the anonymous channel ticket authentication phase since to keep the computation cost down.

This paper is concerned with fuzzy modeling in some reduction methods of inference rules with gradient descent. Reduction methods are presented, which have a reduction mechanism of the rule unit that is applicable in three parameters--the central value and the width of the membership function in the antecedent part, and the real number in the consequent part--which constitute the standard fuzzy system. In the present techniques, the necessary number of rules is set beforehand and the rules are sequentially deleted to the prespecified number. These methods indicate that techniques other than the reduction approach introduced previously exist. Experimental results are presented in order to show that the effectiveness differs between the proposed techniques according to the average inference error and the number of learning iterations.

The paper proposes a transmitter diversity scheme with a desired signal selection for the mobile communication systems in which the severe cochannel interference (CCI) is assumed to occur at the base station. The feature of the proposed scheme is that the criterion of the downlink branch selection is based on the desired signal power estimated by the correlation between the received signal and the unique word at the matched filter. Moreover, the unique word length control method according to the instantaneous SIR is applied to the proposed scheme, taking account of the uplink transmission efficiency. Computer simulation results show that the proposed scheme provides the better performance than the conventional transmitter diversity in the severe CCI environments, and that the unique word length control method applied to the proposed scheme decreases the unique word length without the degradation of the transmission quality, comparing with the fixed unique word length method.

In this letter, we introduce new parameters for classifying digitally modulated unknown QAM and PSK signals. Our two parameters for the classification are the variance of magnitude ratios and the mean of mod 2π phase differences. The gain adjustments of amplitudes are not required for the classification. Five different types of QAM constellations and three different types of PSK constellations are tested and the characteristics of our classification parameters are investigated in various SNR environments. Simulation results demonstrate the effectiveness of our proposed technique.

In this paper, a new expression is derived for the bit error rate (BER) performance of Gray-encoded MDPSK for M=2 and 4 in orthogonal frequency division multiplexing (OFDM) systems over time-variant and frequency-selective Rayleigh fading channels. We assume that the guard time is sufficiently larger than the delay spread to solve the intersymbol interference (ISI) problem on the demodulated OFDM signal. In this case, the performance depends on the Doppler spread of fading channel. The closed form expression for the bit error probability of MDPSK/OFDM extended from the result in [5] shows that the BER performance of MDPSK is determined by (N + NG ) fD Ts where N is the number of subchannels, NG the length of the guard interval, fD the maximum Doppler frequency, and Ts the sampling period. The theoretical analysis results are confirmed by computer simulations for DPSK and QDPSK signals.

A merged analog-digital circuit architecture is proposed for implementing intelligence in SoC systems. Pulse modulation signals are introduced for time-domain massively parallel analog signal processing, and also for interfacing analog and digital worlds naturally within the SoC VLSI chip. Principles and applications of pulse-domain linear arithmetic processing are explored, and the results are expanded to the nonlinear signal processing, including an arbitrary chaos generation and continuous-time dynamical systems with nonlinear oscillation. Silicon implementations of the circuits employing the proposed architecture are fully described.

A new adaptive multichannel filtering approach is introduced and analyzed in this paper. The technique is simpler and more appropriate than traditional approaches that have been addressed by means of groupwise vector ordering information. These filters are a two-stage filters based on rational functions (RF) using fuzzy transformations of the Euclidean and angular distances among the different vectors to adapt to local data in the color image. The output is the result of vector rational operation taking into account three fuzzy sub-function outputs. Simulation studies indicate that the filters are computationally attractive and have excellent performance such as edge and details preservation and accurate chromaticity estimation.

This paper proposes a new hybrid active noise control (ANC) system without the estimation of the secondary path filter in advance. The algorithm of the feedforward part of the proposed method is based on the simultaneous equations method and the feedback part employs the filtered-X LMS algorithm. The estimation of the secondary path filter is obtained in the operation of the feedforward part and it is used in the feedback part. When the secondary path changes in the operation of the system, the proposed system can follow to this change. In the simulation example which treats the colored measurement noise, the fine noise reduction performance is obtained.