Browsing is an important function supporting efficient access to relevant information in video archives. In this paper, we present PanoramaExcerpts -- a video browsing interface that shows a catalogue of two types of video icons: panoramic and keyframe icons. A panoramic icon is automatically synthesized from a video segment taken with camera pan or tilt using a camera parameter estimation technique. One keyframe icon is extracted for each shot to supplement the panoramic icons. A panoramic icon represents the entire visible contents of a scene extended with a camera pan or tilt, which is difficult to represent using a single keyframe. A graphical representation, called camera-work trajectory, is also proposed to show the direction and the speed of camera operation. For the automatic generation of PanoramaExcerpts, we propose an approach to integrate the following: (a) a shot-change detection method; (b) a method for locating segments that contain smooth camera operations; (c) a layout method for packing icons in a space-efficient manner. In this paper, we mainly describe (b) and (c) with experimental results.

In Synthetic Aperture Radar Interferometry (InSAR), phase unwrapping holds the key to accurate inversion of digital elevation data. Two new techniques are introduced in this paper that can perform automatic phase unwrapping. The first one is an "optimal" branch-cut algorithm and the second one a hybrid branch-cut/least-square technique, in which pole locations form the weighting basis for the weighted least-square approach. Application of both techniques to ERS-1 data indicates that the height inversion errors are comparable and offer over fifty percent reduction in root mean square (rms) height error compared to the straight least squares method and over thirty-five percent reduction in rms height error compared to the weighted least squares method based on coherence data weighting schemes. The hybrid technique is especially appealing due to its computational efficiency and robustness when compared to traditional branch-cut algorithms.

Precise simulation of non-quasi-static (NQS) characteristics is crucial for the analog application of MOS transistors. This paper presents the small signal admittance model of four-terminal NQS MOS transistors by solving the differential equation derived from the primary principle. The model contains the bulk-charge effect, the mobility reduction, and the velocity saturation. The results are compared with those for the conventional quasi-static model, the BSIM3v3 NQS model, and the 2-D device simulation.

In this paper, a new approach to adaptive direction-of-arrival (DOA) estimation based upon a database retrieval technique is proposed. In this method, angles and signal powers are quantized, and a set of true correlation vectors of the array antenna input vectors for various combinations of the quantized angles and signal powers is stored in a database. The k-d tree is then selected as the data structure to facilitate range searching. Estimated a correlation vector, range searching is performed to retrieve several correlation vectors close to it from the k-d tree. The DOA and the signal power are estimated by taking the weighted average of angles and powers associated with the retrieved correlation vectors. Unlike the other high-resolution methods, this method requires no eigenvalue computation, thus allowing a fast computation. It is shown through simulation results that the processing speed of the proposed method is much faster than that of the root-MUSIC that requires the eigenvalue decomposition.

The subject of this study is to propose a new structure that can realize simultaneously high breakdown voltage and high packing density for both Nch low side switch and Pch high side switch in 200 V class rating. As the conventional techniques for the electric field relaxation, the structure of field plate, field ring and RESURF are well known, but these techniques are inadequate for the high packing density because they are the techniques in surface region. In order to conquer this subject, it is necessary to relax the electric field in the deep region. The electric field relaxation was investigated by device simulation. In the Nch low side switch the electric field is relaxed by buried oxide film in SOI structure. However, electric field relaxation cannot be realized only by adapting the SOI structure for Pch high side switch. Then we tried to insert an intrinsic layer between P-drift layer and the buried oxide film in order to spread the depletion layer in the deep region. This spread depletion layer by intrinsic layer and the depletion layer by field plate connect vertically, and the dosage of the ion implantation for drift layer can be set to two times higher than the case without intrinsic layer. As the results, it was revealed that the SOI structure with intrinsic layer is effective to achieve this subject. Furthermore, by fabricating both Nch low side switch and Pch high side switch on intrinsic SOI substrate, breakdown voltage more than 250 V were achieved.

We analyze a scheme that provides frequency hopping pattern for DS/FH spread spectrum. The proposed scheme, based on the theory of finite projective planes, intends to make the number of transmitting terminals uniform across all channels and distribute the interference to all the participant terminals equally. Thus, when a terminal is in a state of power surge, the probability of having the worst case of interference for terminals sharing the same channel is reduced. In the performance evaluation, we demonstrate that the bit error rate is reduced by an order of magnitude through the use of the proposed hopping pattern for both internal and external interference.

This paper presents a method of thread composition in a hardware compiler Bach. Bach synthesizes RT level circuits from a system description written in Bach-C language, where a system is modeled as communicating processes running in parallel. The system description is decomposed into threads, i.e., strings of sequential processes, by grouping processes which are not executed in parallel. The set of threads are then converted into behavioral VHDL models and passed to a behavioral synthesizer. The proposed method attempts to find a thread configuration that maximize resource sharing among processes in the threads. Experiments on two real designs show that the circuit sizes were reduced by 3.7% and 14.7%. We also show the detailed statistics and analysis of the size of the resulting gate level circuits.

Methods for implementing SS7 functions are proposed for a large-capacity decentralized switching node; they satisfy the condition of hiding distributed configurations from adjacent nodes. First, line accommodation and acquisition methods are clarified for a large-capacity switching node in which multiple modules are used to realize trunk circuits and SS7 signaling links. Two methods are then proposed for allocating SS7 functions within the switching node. One distributes the functions over multiple circuit-switched modules (distributed allocation) while the other centralizes the functions in dedicated signaling modules (centralized allocation). We quantitatively evaluate both methods in terms of node scale versus the number of modules and signaling links required, the inter-module data transfer rate required, and the node traffic handling capacity when a particular module fails. From the evaluation results, we show that the distributed allocation should be employed for small-scale nodes and the centralized allocation for large-scale nodes. We also show the effectiveness of a method for avoiding a characteristic problem that arises when a particular module fails. Finally, we implement an experimental system as an example.

This letter points out some flaws in the previous works on UKS (unknown key-share) attacks. We show that Blake-Wilson and Menezes' revised STS-MAC (Station-to-Station Message Authentication Code) protocol, which was proposed to prevent UKS attack, is still vulnerable to a new UKS attack. Also, Hirose and Yoshida's key agreement protocol presented at PKC'98 is shown to be insecure against public key substitution UKS attacks. Finally, we discuss countermeasures for such UKS attacks.

In this paper we present a case study of a hierarchical statistical analysis. The method which we use here bridges the statistical information between process-level and system-level, and enables us to know the effect of the process variation on the system performance. We use two modeling techniques--intermediate model and response surface model--in order to link the statistical information between adjacent design levels. We show an experiment of the hierarchical statistical analysis applied to a Phase Locked Loop (PLL) circuit, and indicate that the hierarchical statistical analysis is practical with respect to both accuracy and simulation cost. Following three applications are also presented in order to show advantage of this linking method; these are Monte Carlo analysis, worst-case analysis, and sensitive analysis. The results of the Monte Carlo and the worst-case analysis indicate that this method is realistic statistical one. The result of the sensitive analysis enables us to evaluate the effect of process variation at the system level. Also, we can derive constraints on the process variation from a performance requirement.

The classified side-match vector quantizer, CSMVQ, has already been presented for low-bit-rate image encoding. It exploits a block classifier to decide which class the input vector belongs to using the variances of the upper and left codewords. However, this block classifier doesn't take the variance of the current input vector itself into account. This letter presents a new CSMVQ in which a two-level block classifier is used to classify input vectors and two different master codebooks are used for generating the state codebook according to the variance of the input vector. Experimental results prove the effectiveness of the proposed CSMVQ.

A known problem of the four-phase handshaking protocol is that a return-to-zero phase of the signals involved in the handshake is necessary before starting another cycle, in which no useful work is usually done. In this paper we first define an easy-to-write specification style to specify four-phase handshaking asynchronous controllers that can be translated to an STG to obtain a gate-level implementation using existing synthesis methods. Then, we propose an algorithm that takes the specification written using our specification style and finds an optimized timing in which the idle-phase overhead of its gate-level implementation is reduced.

We propose a functional memory for addition (FMA), which is a memory-merged logic LSI. It is a memory as well as a SIMD parallel processor. To minimize the area, a precessing element (PE) consists of several DRAM words and a bit-serial ALU. The ALU has a functionality of addition bit by bit. This paper describes two FMA experimental LSIs. One is for general purpose, and the other is for full search block matching of image compression. We estimate that a 0.18 µm process realizes 57,000 PEs in a 50 mm2 die, achieving 205 GOPS under 1.36 W power.

Timing verification of digital synchronous designs is a complex process that is traditionally carried out deep in the design cycle, at the gate level. A method, embodied in a C++ based design system, is presented that allows modeling and verification of clock regions at a higher level. By combining event-driven, clock-cycle true and behavioral simulation, we are able to perform static and dynamic timing analysis of the clock regions.

This study presents two new bit-parallel cellular multipliers based on an irreducible all one polynomial (AOP) over the finite field GF(2m). Using the property of the AOP, this work also presents an efficient algorithm of inner-product multiplication for computing AB2 multiplications is proposed, with a structure that can simplify the time and space complexity for hardware implementations. The first structure employs the new inner-product multiplication algorithm to construct the bit-parallel cellular architecture. The designed multiplier only requires the computational delays of (m+1)(TAND+TXOR). The second proposed structure is a modification of the first structure, and it requires (m+2) TXOR delays. Moreover, the proposed multipliers can perform A2iB2j computations by shuffling the coefficients to make i and j integers. For the computing multiplication in GF(2m), the novel multipliers turn out to be efficient as they simplify architecture and accelerate computation. The two novel architectures are highly regular, simpler, and have shorter computation delays than the conventional cellular multipliers.

In this letter we propose a filter for extracting a quasi-periodic signal from a noisy observation using wavelets. It is assumed that the instantaneous frequency of the signal is known. A particularly difficult task when the frequency and amplitude of the desired signal are varying with time is shown. The proposed algorithm is compared with three other methods.

We investigated the dependence of the desired echo return loss on frequency for various hands-free telecommunication conditions by subjective assessment. The desired echo return loss as a function of frequency (DERLf) is an important factor in the design and performance evaluation of a subband echo canceller, and it is a measure of what is considered an acceptable echo caused by electrical loss in the transmission line. The DERLf during single-talk was obtained as attenuated band-limited echo levels that subjects did not find objectionable when listening to the near-end speech and its band-limited echo under various hands-free telecommunication conditions. When we investigated the DERLf during double-talk, subjects also heard the speech in the far-end room from a loudspeaker. The echo was limited to a 250-Hz bandwidth assuming the use of a subband echo canceller. The test results showed that: (1) when the transmission delay was short (30 ms), the echo component around 2 to 3 kHz was the most objectionable to listeners; (2) as the transmission delay rose to 300 ms, the echo component around 1 kHz became the most objectionable; (3) when the room reverberation time was relatively long (about 500 ms), the echo component around 1 kHz was the most objectionable, even if the transmission delay was short; and (4) the DERLf during double-talk was about 5 to 10 dB lower than that during single-talk. Use of these DERLf values will enable the design of more efficient subband echo cancellers.

This paper discusses a gate resizing method for performance enhancement based on statistical static timing analysis. The proposed method focuses on timing uncertainties caused by local random fluctuation. Our method aims to remove both over-design and under-design of a circuit, and realize high-performance and high-reliability LSI design. The effectiveness of our method is examined by 6 benchmark circuits. We verify that our method can reduce the delay time further from the circuits optimized for minimizing the delay without the consideration of delay fluctuation.

Aged people who live alone are in particular need of a daily health check, medication, and of warm communication with family and friends. The authors have been developing a life-support computer system with such functions. Among them, a daily health check function with the capability of measuring blood pressure, detecting diseases from coughing, and so on would in particular be very powerful for primary care. As a first step to achieving quick services for a daily health check with a personal computer, utilization of cough information is considered. Features of cough data are analyzed aiming at developing an automatic cough data detection method. This paper proposes a novel method for extracting cough signals from other types of signals. The differential coefficient of a low-pass filtered waveform is first shown to be an effective parameter for discriminating between vowel and cough signals, and the relationship between cut-off frequency and cough detection rate is clarified. This parameter is then applied to cough signals mixed with vowel signals or white noises to evaluate robustness. The evaluation tests show that the cough feature can be perfectly detected for a 20 dB S/N ratio when the cut-off frequency is set to 24 [Hz]. The experimental results suggest that the proposed cough detection method can be a useful tool as a primary care for aged people with a bronchitis like an asthmatic bronchitis and a bronchopneumonia.

This paper presents a system-level bus architecture validation technique and shows its application to a consumer product design. This technique enables the entire system to be validated with bus cycle accuracy using bus architecture level models derived from their corresponding behavioral level models. Experimental results from a digital still camera (DSC) system design show that our approach offers much faster simulation speed than register transfer level (RTL) simulators. Using this fast and accurate validation technique, bus architecture designs, validations and optimizations can be effectively carried out at system-level and total turn around time of system designs can be reduced dramatically.