This paper will describe an overview on several design issues and solutions for the realization of MPEG2 encoder &decoder LSIs. ULSI technology and video-coding specific design have been able to actualize an MPEG2 encoder &decoder LSI with realtime capability, flexibility and cost effectiveness, though MPEG2 processing at MP＠ML (Main Profile and Main Level) requires an enormous computation power of 10-200 GOPS depending on the motion estimation algorithm and a search range. Video coding processors, whose performance has been enhanced at the rate of one order per 3 years, have reached the performance level required to implement MPEG2 encoding using multiple chip configuration. This has been achieved by a hybrid architecture with video-oriented RISC and hardware engine optimized for coding algorithms. Intensive circuit optimization was carried out for transform coding such as DCT and predictive coding with motion estimation. Now cost effective MPEG2 decoders have begun to penetrate the multimedia market. There are two main design issues. One is the architectural and circuit design which minimizes the silicon area and power dissipation. The other is external DRAM control which makes use of DRAM storage and band width efficiently to reduce the system cost. Also future trends in a deep submicron era will be discussed. A single chip MPEG2 MP＠ML encoder is expected to appear in the 0.25 micron era at the latest. An MPEG2 MP＠ML decoder could be compressed to an area of about 25 mm2.

A new method is proposed for realizing a flexible change detection which is free from the limitation that multitemporal images must have the same spectral bands whose center wavelength and bandwidth are identical. As spaceborne multispectral scanners are continuously improved for performance and new scanners do not necessarily have the same spaectral bands for observation, this limitation is a serious obstacle for detecting long term temporal change. The proposed method removes this limitation by using an image normalization technique based on multiple regression analysis. The method is successfully applied to actual remotely sensed multitemporal images.

A motion compensation LSI for realtime MPEG1/H.261 video encoding has been developed. This LSI employs a compact motion estimator that consists of vector search array processors. Furthermore, an efficient motion vector search strategy that enables bidirectioanl searches with a -16.0/+15.5 pels range is adopted to maintain encoded picture quality. The adopted strategy takes two steps. The first step is the full search for 2-pel precision vectors within the range of 16 pels. A 4-to-1 sub-sampling technique with a low pass filter is employed in this step. The second step is the full search for half-pel precision vectors within a 1.0 pels search range centered on the location pointed by the best 2-pel precision vectors. This strategy is compared with the exhaustive-search strategy. It is shown that the number of operations and external memory access cycles are reduced to 1/11 and 1/2, respectively, while differences of the signal to noise ratios obtained by simulation are within 0.2 dB. Those reductions contribute to lowering power dissipation. The array processors calculate the values of distortion. They accumulate the absolute differences between current and reference data with a feedback loop to keep the number of processor elements equal to the number of pels in a row of the current block. Multiple reference data buses and a delay line in the feedback loop have been introduced for efficient calculation. In addition, cascade connection of the array processors is studied to shorten calculation periods. This LSI controls input frames reordering buffers and reference frames buffers. It generates the prediction and the prediction error blocks as well as the motion vectors. AC power of current blocks and the values of distortion are obtained for the bit rate control. This LSI is fabricated using 0.8 µm 2-level metal CMOS technology and dissipates 2.0 W from 5 V supply at 36 MHz.

CAMs (Content Addressable Memories) are functional memories which have functions such as word-parallel equivalence search, bilateral 1-bit data shifting between consecutive words, and word-parallel writing. Since CAMs can be integrated because of their regular structure, massively parallel CAM functions can be executed. Taking advantage of CAMs, Ishiura and Yajima have proposed a parallel fault simulation algorithm using a CAM. This algorithm, however, requires a large amount of CAM storage to simulate large-scale circuits. In this paper, we propose a new massively parallel fault simulation algorithm requiring less CAM storage, and compare it with Ishiura and Yajima's algorithm. Experimental results of the algorithm on CHARGE --the CAM-based hardware engine developed in our laboratory--are also reported.

This paper discusses and evaluates an effect of cell level FEC (Forward Error Correction) capability on error-free (i.e. reliable) IP multicast service over ATM networks. In the error-free IP multicast service, every receiver is delivered IP packet from the sender synchronously. Without applying the FEC policy, the expected IP packet error/loss probability becomes large, when the number of multicast receivers is large. For example, when the cell error/loss probability of each ATM data-link segment is 10-6 and the number of receivers is 103, the IP packet error/loss probability observed at the sender is about 0.5, which means that about 50% of IP packet sent from the sender will be subject to retransmission. One possible solution would be using the intermediate multicast-TCP entities, that terminate TCP protocol, among the sender and the receivers. However, this approach requires the additional entities within the network and can not provide the ordered message delivery for a multipoint-to-multipoint communication. On the contrary, with applying the FEC policy, the expected IP packet error/loss probability is dramatically reduced. Therefore, an error-free IP multicast service can be provided with a simple architecture, even when the number of multicast receiver is large, e.g. 105. For example, when the cell error/loss probability of each ATM data-link segment is 10-6, the packet error/loss probability observed at the sender is less than 10-2 even for 106 receivers. Finally, even when the cell error/loss probability of ATM data-link segment is large, e.g. 10-3, the IP multicast service without the FEC policy can not apply even for 10 receivers. However, the IP multicast with the FEC policy can apply upto few hundred of receivers.

This paper presents Ternary Decision Diagrams which represent sets of products. This paper also presents manipulating methods for sum-of-products forms and ringsum-of-products forms using Ternary Decision Diagrams, and gives comparison results between Ternary Decision Diagrams and Binary Decision Diagrams.

This paper describes a new, low power 16-bit Digital Signal Processor (DSP). The DSP has a double-speed MAC mechanism, an accelerator for Viterbi decoding, and a block floating section which contribute to lower power consumption. The double-speed MAC can perform two multiply and accumulate operations in one instruction cycle. Since MAC operations are so common in digital signal processing, this mechanism can reduce the average clock frequency of the DSP resulting in lower power consumption. The Viterbi accelerator and block floating circuitry also reduce the clock frequency by minimizing the number of required cycles needed to be executed. The DSP was fabricated using a 0.8 µm CMOS 2-aluminum layer process technology to integrate 644 K transistors on a 9.30 mm9.09 mm die. It can realize an 11.2 kbps VSELP speech CODEC while consuming only 70 mW at 3.5 V Vdd.

This work deals with thermal-noise modeling for silicon vertical bipolar junction transistors (BJTs) and relevant integrated circuits (ICs) operating at low currents. The two-junction BJT compact model is consistently derived from the thermal-noise generalization of the Shockley semiconductor equations developed in work which treats thermal noise as the noise associated with carrier velocity fluctuations. This model describes BJT with the Itô non-linear stochastic-differential-equation (SDE) system and is suitable for large-signal large-fluctuation analysis. It is shown that thermal noise in silicon p-n-junction diode contributes to "microplasma" noise. The above model opens way for a consistent-modeling-based design/optimization of bipolar device noise performance with the help of theory of Itô's SDEs.

We propose a distributed operation system platform for optical cable networks. This distributed platform is an extension of the previously proposed platform for a flexible cable network operation. The concept of the unit platform has been proposed for the distributed operation system platform. By using this concept, we discuss the system upgrade including the connection to other operation systems. We use an object-oriented software technology for designing the distributed operation system platform. The prototype system has been constructed using C++ programing language and the evaluated results are shown.

In this paper we study the properties induced by the symmetrical properties of a system of hybridly coupled oscillators of the Rayleigh type on the bifurcations of its equilibria. We first discuss the symmetrical properties of the system. Then we classify the equilibria according to their symmetrical properties. Demonstrating the structural degeneracy of the system, we give the complete stability analysis of the equilibria.

This paper describes an oversampling analog-to-digital converter (ADC) suitable for PCM codes. Non-linear 5-level quantizer is implemented to noise-shaping modulator. This ADC meets the specifications of ITU-T G.712, in spite of using first order delta-sigma modulator, and realizes low power operation. This chip is fabricated in 0.8 µm double-poly and double-metal CMOS process and occupies a chip area of 15 mm2. Maximum power consumption is 12.8 mW with a single +3 V power supply including DAC and TONE generator.

A new low-power and high-speed CMOS interface circuit is proposed in which signals are transmitted by means of impulse voltage. This mode of transmission is called impulse transmission. Although a termination resistor is used for impedance matching, the current through the output transistors and the termination resistor flows only in transient states and no current flows in stable states. The output buffer and the termination resistor dissipate power only in transient states, so their power dissipation is reduced to 30% that of conventional low-voltage-swing CMOS interface circuits at 160 MHz. The circuit was fabricated by 0.5 µm CMOS technology and was evaluated at a supply voltage of 3.3 V. Experimental results confirm low power of 4.8 mW at 160 MHz and high-speed 870 Mb/s error free point-to-point transmission.

In arithmetic units multiplication is a very important operation. It is a common approach to use the modified Booth's algorithm to reduce the number of partial products in a multiplication and speed it up. In this letter we show two circuits that fuse the usually separate functions of generating the partial products and selecting them. The circuits designed in DPL (Double Pass-transistor Logic) are bigger in MOS transistors, but are faster and, function at higher frequencies than a typical CMOS implementation. One of our circuits also has lower power consumption.

This paper describes our newly developed intelligent sensor system which comprises two eyes and four ears on a movable head. It can acquire its dynamical visual and auditory image of its surrouding 3-D environment while showing humanlike behavior naturally and autonomously. The most important feature of the sensor system is in an autonomous and optimum sensory architecture of it. This enables the sensor to achieve 1) repid (5 ms) and accurate (2 deg) auditory localization, 2) rapid (0.5 s/65536 pixel) extraction of visual motion in marginal view, 3) rapid (several TV frames' time) eye movement and binocular fixation to a suddenly appeared object, 3) rapid (0.1 s/4096 pixel) extraction of 3-D object profile and image features, which is activated by its own auditory localization and motion detection. We describe in this paper the several key items for realizing this sensor.

A two-dimensional recording method that achieves double recording density by reducing the track pitch is described. This method uses a flat disk and the data are recorded with circular marks on lattice points. Two-dimensional interference consisting of crosstalk and inter-symbol interference is reduced by two-dimensional equalization. To minimize the two-dimensional interference, the optimum equalization coefficients are calculated dynamically with the reproduced signal of the training marks. Reproduction was simulated and this showed that the signal-to-noise ratio of the processed signal was 24.3 dB under ideal conditions and 19.8 dB under worst-case conditions with the usual magneto-optical media using double recording density. These simulation results were checked by a recording/reproduction experiment. The experimental result for the signal-to-noise ratio of the processed signal was 23.6 dB with an areal density of 2.3 Gbit/in2.

Tremendous progress has been made in magnetic data storage by applying theoretical considerations to technologies accumulated empirically through a great deal of research and development. In Japan, the recording demagnetization phenomenon was eagerly analyzed by many researchers because it was a serious problem in analogue signal recording such as video tape recording using a relatively thick magnetic recording medium. Consequently, perpendicular magnetic recording was proposed as a method for extremely high-bit-density recording. This paper describes the theoretical background which has resulted in the idea of perpendicular magnetic recording. Furthermore, the possibility of magnetic recording is discussed on the basis of the results obtained theoretically by magnetic recording simulators. Magnetic storage has the potential for extremely high-bit-density recording exceeding 1 Tb/cm2. We propose the idea of 'spinic data storage' in which binary digital data could be stored into each ferromagnetic single-domain columnar particle when the perpendicular magnetizing method is used.

The magnetic properties and the structure of electroless-deposited NiFeB films were investigated in comparison with those of electrodeposited NiFe films. The electroless-deposited NiFeB film with 27at% Fe content had the lowest coercivity, H, as low as 0.5 Oe with a saturation magnetic flux density, Bs, of 1.0 T. The saturation magnetostriction, λ, and the uniaxial magnetic anisotropy, Hk, were 5.010-6 and 10 Oe, respectively, which were larger than those of the conventional, electrodeposited permalloy film. The permeability of as-deposited Ni70Fe27B3 film was 1000 at 1 MHz. In order to improve the permeability, the film was heated at 200 in a magnetic field applied in the hard-axis direction to decrease the Hk value, and the permeability became 2000 at 1 MHz. The crystal structure and grain size of NiFeB and NiFe films were investigated by XRD, THEED and TEM. Both films with low Hc had an fcc structure; the grain size of the NiFeB film was smaller than 10 nm, while that of the NiFe film was larger, approximately 20 nm. The results suggested that the electroless-deposited NiFeB film had a larger magnetic anisotropy than the electrodeposited NiFe film. Moreover, the films with Hc less than 10 Oe ded not show clear difference between their TEM bright images and THEED patterns.

This paper deals with the improvement of performance in the transform and subband image coding systems with negatively-correlated input signal. Using a more general source model than the AR(1) model as an input, the coding performance for the transform and subband coding schemes is evaluated in terms of the coding gain over PCM. The source model used here has such resonant band characteristics that its power spectrum has a peak at some frequency between 0 and π/2 for positive autocorrelation and between π/2 and π for negative autocorrelation. It is shown that coding schemes are classified into two classes; one has the pairwise mirror-image property in their filter banks and performs symmetrically regardless of the sign of the autocorrelation, and the other has no that property and performs asymmetrically with inferior performance for negative autocorrelation. Among the well-known transform and subband coding schemes, the DHT and QMF coding systems belong to the former class and the DCT and SSKF coding systems to the latter. In order to remedy the inferior performance, we propose the method in which one modulates the negatively-correlated signal sequences by the alternating sign signal with unity magnitude (-1)n to convert them into positively-correlated sequences. The algorithms are presented for the DCT and SSKF image coding systems with the adaptive signal modulation. In the DCT coding systems, we are particularly concerned with the DCT-based hierarchical progressive coding mode of operation, since the signal modulation works well for that coding mode. The SSKF image coding system has the regular quad-tree structure with three stages. The simulation results for test images show that our method can successfully be applied to the images with a considerable amount of energy in the frequency range higher than π/2 in horizontal or vertical direction, such as fingerprints and textile patterns sampled at a rate close to the Nyquist rate. The paper closes with a brief introduction to the modification of our DCT-based method.

This paper proposes and investigates a tap selectable Viterbi equalizer for mobile radio communications. When the multipath channel is modeled by a tapped delay line only, the taps which may seriously affect the data sequence estimation are selected and used to calculate the trellis metric in the Viterbi algorithm. The proposed equalization algorithm can reduce the number of path metric calculations and the number of path selections in the Viterbi algorithm. Moreover, we propose an extended equalizer which has antenna diversity. This equalizer calculates the path metric using the antenna outputs and results of channel estimators. Computer simulation is used to evaluate the BER performance of the proposed equalizer in a multipath radio channel.

Genetic Algorithm (GA) is the method of approaching optimization problem by modeling and simulating the biological evolution. As the genetic algorithm is rather time consuming, the use of a parallel genetic algorithm can be advantage. This paper describes new methods for fine-grained parallel genetic algorithm using a multiprocessor system FIN. FIN has a VLSI-oriented interconnection network, and is constructed from a viewpoint of fractal geometry so that self-similarity is considered in its configuration. The performance of the proposed methods on the Traveling Salesman Problem (TSP), which is an NP-hard problem in the field of combinatorial optimization, is compared to that of the simple genetic algorithm and the traditional fine-grained parallel genetic algorithm. The results indicate that the proposed methods yield improvement to find better solutions of the TSP.