This paper deals with the problems in testing large mixed-signal ICs. To help generating test patterns of these larger mixed-signal circuits for a functional test, a fast fault simulation algorithm and a fault model voltage stuck-at fault" which the algorithm is based on, are proposed. A voltage stuck-at fault is that a signal line sticks its voltage level at a certain constant. Under an assumption that blocks in a circuit are designed as identically current-independent, i.e. their input impedance can be regarded as infinite and their output impedance as zero, fault simulation can be realized by the event driven method and the concurrent method and can detect voltage stuck-at faults. These methods are essential for digital fault simulation and very effective to high speed simulation, although they were impossible for an analog or mixed-signal circuit by a conventional algorithm. Furthermore, the efficiency of the simulation is improved because I/O relation of blocks is approximated to a stepwise linear function. The above techniques and methods make fault simulation for a mixed-signal circuit possible in practical use. Actually, a fault simulator was implemented, then some test circuits were simulated. The simulator is really faster than conventional simulation based on circuit simulation. Next, fault analysis was applied to several bipolar ICs to verify the validity of the fault model voltage stuck-at faults". Analyses of open and short faults between terminals of transistors and resistors show that this fault model has sufficient coverage (more than 50%) to test mixed-signal circuit.

At the beginning of the 21st century, 1 Gb DRAMs will be in practical use, and sufficient in terms of memory capacity for most memory applications systems. The key technologies for multimedia systems include data compression, communication, storage, and human interfaces. Image data processing, ATM switch, and microprocessor in multimedia applications require the high data transfer rate from several 100 Mbits/s to Tbits/s. Storage systems, on the other hand, require the reduction of the price per bit to less than 10 cents/Mbytes. Application specific design approaches towards a system-on-chip are strongly needed for ULSI memories in the multimedia era.

In the final stages of VLSI testing, improved quality VLSI testing is an important subject for ensuring reliability in the forwarded VLSI market. On the other hand, developments in high integration technology have resulted in an increased number of functional blocks in VLSI devices and an increased number of gates for each terminal. Consequently, it has become more difficult to improve the quality of VLSI tests. We have developed a new test method in addition to conventional testing methods intended for improving the test coverage in VLSI tests. This new test method analyzes the relationship between IDDq (Quiescent Power Supply Current) of DUT and DUT failure by applying the concept of the toggle rate. Accordingly, in this paper we report that the results of IDDq testing confirm a correlation with defect level.

This paper presents techniques used in combinational test generation for multiple stuck-at faults using the parallel vector pair analysis. The techniques accelerate a test generation procedure previously proposed and reduce the number of test vectors generated, while higher fault coverage is derived. The first technique proposed in this paper, which is applied at the first phase of test generation, is rules of ordering vector pairs to be analyzed, to derive high fault coverage without repeating the analysis for the same vector pairs. The second one is to generate new vector pairs for undetected faults, instead of random vector pairs. Both techniques are based on the idea that faults close to primary inputs should be detected earlier than close to primary outputs. The third technique proposed here is how to construct vector pairs from one input vector in order to accelerate test generation especially for circuits with many primary inputs and scan flip-flops. Experimental results for bench-mark circuits show the effectiveness of the techniques.

Transition coverage has been proposed as a measure of two-pattern test capabilities of TPG circuits for use in BIST. This paper investigates experimentally the relationships between transition coverages and actual stuck-open fault coverages in order to reveal what kind of circuits are appropriate for two-pattern testing. Fault simulation was performed using conventional (n-stage) LFSR, 2n-stage LFSR, and one-dimensional cellular automata (CAs) as TPG circuits and such sample circuits as balanced NAND tree and some ISCAS '85 benchmark circuits as CUTs. It was found that CAs which are designed so as to apply exhaustive transitions to any 3-dimensional subspaces can detect high rate of stuck-open faults. Influence of hazards of decreasing the fault coverage is also mentioned.

In the correspondence discrete Wigner higher order spectra (WHOS) of harmonizable random signals are addressed and their relations with polyspectra (HOS) are illustrated. It is shown, that discrete WHOS of a random stationary signal do not reduce to the aliased polyspectra in a similar way as Wigner distribution (WD) reduces to the power spectrum of a random signal. Wigner 2nd-order time-frequency distribution of deterministic signals and the 3rd-order spectrum of stationary signals are presented in their modified forms to be used to estimate time-varying third-order spectrum of discrete nonstationary random harmonizable processes.

We compared--for the same propagation conditions and parameters--the performances of distributed dynamic channel assignment (DDCA) strategies and the performance of fixed channel assignment (FCA). This comparison quantitatively showed the effects of DDCA strategies in increasing spectrum efficiency. It also showed that using DDCA with transmitter power control (TPC) increases the system capacity to 3 4 times what it is with FCA and to 1.4 1.8 times what it is when using DDCA without TPC. We also evaluated the blocking rate and the interference probability for the inside of a cell and found that these are generally much higher close to the cell border than they are near the base station.

The applicability of Dynamic Channel Assignment methods to a Reuse Partitioning system in cellular radio systems is investigated in this paper. The investigations indicate that such a system has a tendency to increase the difference between blocking probability for the partitioning two coverage areas in comparison with the conventional Reuse Partitioning system employing Fixed Channel Assignment method. Two schemes using new Channel Rearrangement algorithms are also proposed in order to alleviate the difference as a disadvantage which gives unequal service to the system. The simulation results show that the proposed schemes are able to reduce the difference significantly while increasing the carried traffic by 10% as compared with the conventional system.

The word error probability of linear block codes is computed for diversity systems with maximal ratio combining in mobile communications with three decoding algorithms: error correction (EC), error/erasure correction (EEC), and maximum likelihood (ML) soft decoding algorithm. Ideal interleaving is assumed. EEC gives 0.1-1.5dB gain over EC. The gain of EEC over EC decreases as the number of diversity channels increases. ML soft gives 1.8-5.5dB gain over EC.

The subject is the horizontal coil's temperature rise in DY for high frequency by being unavoidable for the tendency of more information on display monitor equipments. Writers made the temperature-balance model from a point of view that this temperature rise is coming from the heat rise and the conductivity, and we expressed the temperature rise of DY by using amount of the heat rise and conductivity characteristics of each element. Also, we indicated the method to decide about the selection of the wire size of coils, the section area and deflection sensitivity, with regard to reducing the temperature rise. We confirmed the effect of the temperature rise reduction by about 9 on products, under the condition of 64 kHz horizontal frequency.

There is general trend toward larger chip size and tighter layout due to customer requests of loading more and more functions on single chip. This trend makes yield difficult to be maintained high enough, since larger amount of defects are distributed on such large and tight-ruled chips. To overcome such a situation, RADLYS (RAnDom Logic Yield Simulator) and DD-TEG (Defect Density TEG) have been developed. DD-TEG extracts defect size distribution and its amount automatically, while RADLYS simulates defects on any layout and outputs yield based on the extracted defect size distribution. Critical layout from yield point of view can be found in this procedure. DD-TEG and RADLYS are used as a set of parameter extraction and simulation of the SPICE. In this paper, we introduce these tools and showed two application results. The predicted yield showed a good agreement with the actual yield in the first application (Optical Device A). Critical layout at the Local I/O portion was found in the second application (Random Logic portion of Memory Device B) and the layout was changed based on the RADLYS results.

Retiming is a technique to resynthesize a synchronous sequential circuit by rearranging flip-flops. In view of logic optimization, retiming can potentially derive a circuit which is more simplified and testable because retiming can convert several sequential redundancies into combinational redundancies. Retiming methods proposed before have no guarantee to generate the same output sequences when the circuit start from a specified initial state such as the reset state. If the circuit with a specified initial state must have the same output sequences after retiming, rearrangement of flip-flops should be restricted. This paper presents a retiming method for circuits with a specified initial state so that retimed circuits give the same output sequences of the original circuits for any input sequences. In the proposed method, during the procedure of retiming each flip-flop keeps a value corresponding to the initial state and unification of flip-flops with different value is avoided. Our procedures uses 5-valued logic on gate level implementation to describe and calculate the values of flip-flops. Therefore after optimization using our method, the circuit has completely the same behavior as that of the original. Experimental results for ISCAS'89 benchmark circuits show the method can be used to optimize the circuits as well as a method without considering the initial state. And testability of the retimed circuit is more enhanced than that of the original circuit.

This paper describes a flexible point-to-multipoint access protocol for the fiber-optic passive double star (PDS) system. To provide various types of services, and permit flexibility in changing transport capacity, a time division multiple access (TDMA) scheme for the PDS system is considered. Dynamic time slot multiplexing based on TDMA is proposed to provide required time slots efficiently according to service changes. The effectiveness of dynamic time slot multiplexing is calculated and compared to fixed time slot multiplexing for telephony services. A TCM/TDMA frame structure and an access protocol enabling dynamic time slot multiplexing are proposed. ONU bandwidth is dynamically assigned by using a set of pointers. The ONU access protocol causes no interruption to operating ONUs on the same PDS system during the configuration or reconfiguration of an ONU. The access time is analyzed to estimate the performance of the access protocol. The probability density of access time is calculated for the number of ONUs connected. The calculation results indicate that a PDS system can accommodate up to around 60 ONUs within the maximum access time specified by ITU-T. The experimental results also agree fairly well with the theoretical values.

This paper describes an 8:1 multiplexer and a 1:8 demultiplexer for fiber optic transmission systems. These chips incorporate new architectures having a smaller hardware and enabling the use of a lower supply voltage. The multiplexer and the demultiplexer are fabricated using 0.8 µm silicon-bipolar process with a double polysilicon self-aligned structure. The multiplexer operates at a bit rate of up to 3.0 Gb/s, while the demultiplexer operates at a bit rate of up to 4.1 Gb/s. The multiplexer consumes 272 mW and the demultiplexer consumes 388 mW under the power supplies of VEE=-4.0 V and VTT=-2.0 V. These values are the smallest so far above 2.5 Gb/s which is the standard of the Level-16 of the synchronous transfer mode (STM-16).

A single bridging fault location technique for CMOS combinational circuits is proposed. In this technique, the cause of an error observed at the primary outputs in deduced using a diagnosis table constructed from the circuit under test and the given tests. The size of a diagnosis table is [the number of gates][the number of tests]2 bits, which is much smaller than that of the fault dictionary. The experimental results show that the number of possible bridging faults is reduced to less than 5 in several seconds, when using the tests to detect single stuck-at faults and considering only the bridging faults between physically adjacent nets.

Current testing has been proposed as an alternative technique for testing fully CMOS digital LSIs. Current testing has higher fault coverage than conventional stuck-at fault (SAF) testing and is more economical because it detects a wide range of faults and requires fewer test vectors than does SAF testing. We have proposed a current testing that measures the integral of the power supply current (IDD) during one clock period including the switching current. Since this method cannot be affected by the switching current, it can be used to test an LSI operating at a relatively high clock freuqnecy. This paper presents an improved current testing method for CMOS digital and analog LSIs. The method uses two current values (i.e., an upper limit and a lower limit) and judges the circuit under test to be faulty if the measured IDD is outside these limits. The proposed current testing is evaluated here for some kinds of faults (e.g., the bridging fault and the breaking fault) in digital and mixed-signal LSIs, and its efficiency of the current testing using SPICE3.

In this paper, we evaluate the performance of handoff schemes in microcellular personal communication systems (PCS) which cater to both pedestrian and vehicular users. Various performance parameters, including blocking of new calls,channel utilization, handoff blocking and call termination probabilities for each user type are evaluated. We study different queuing disciplines for handoff calls and their impact on system performance. We also study the tradeoff in handoff blocking and call termination probabilities between user types as the handoff traffic carried by the system from each user type is varied.

This paper studies the problem of reconstructing a planar surface from stereo images of multiple feature points that are known to be coplanar in the scene. We present a direct method by applying maximum likelihood estimation based on a statistical model of image noise. The significant fact about our method is that not only the 3-D position of the surface is reconstructed accurately but its reliability is also computed quantitatively. The effectiveness of our method is demonstrated by doing numerical simulation.

A novel wireless multimedia network employing a time division duplex CDMA/TDMA scheme is proposed. The network connects mobile multimedia terminals to an ATM based LAN through a radio central unit, and provides both uplink and downlink with unbalanced data rates in the same frequency band. The uplink (from a mobile terminal to a radio central unit) employs a CDMA scheme to transmit low speed human interface signals (-2.4kbit/s), and the downlink employs a TDMA scheme to transmit high speed video signals (-24Mbit/s). The data rates of both links are independent from that of the LAN. The uplink also employs a RAKE receiver and a forward error correction (FEC) scheme using a BCH code in order to reduce bit errors caused by multipath fading. To mitigate channel degradation caused by the near-far problem and multipath fading, a transmission power control (TPC) method for both links and a channel equalizer (CEQ) for the downlink are proposed. The control signals for the TPC and the CEQ are estimated from the impulse response of the channel which is extracted as the output of the matched filters in the CDMA receiver. Theoretical analyses are performed to evaluate the bit error rate (BER) characteristics of the proposed network. The BER performance is derived for a general multipath fading condition modeled by the Nakagami-m distribution and a typical delay profile. Numerical calculation using recent propagation measurements shows the bit error rates of both uplink and downlink to be less than 10-6 when both of the TPC and the CEQ are employed if there are some specular components in the received signals. This excellent performance can cut a way to realize a mobile multimedia terminal for customer premises. Furthermore, the configuration of the mobile terminal is quite simple even if the high speed TDMA signals are received over a multipath fading channel.

Currently there is considerable world-wide speculation regarding the introduction of optical fiber cable into access networks, because optical fiber has a big potential for providing attractive multimedia services. Since optical fiber cable can provide a variety of grade of services, high-reliability of cable networks would be required compared with the conventional copper cable networks. To develop multimedia telecommunication networks as an infrastructure, it is urgent to clarify the highly reliable optical fiber cable network architecture. Since cable network architecture deeply depends on regional conditions such as demand, area size, duct layer networks (consisting of ducts, manholes, tunnels, feeder points etc.), it is necessary to develop a cable network designing tool with user-friendly interfaces for efficiently evaluating cable network architectures. This paper firstly proposes the heuristic algorithms enhanced by the disjoint-shortest-path and the depth-first-search methods that would be applicable for real access networks. Secondly, the design method of highly reliable optical fiber cable network based on the heuristic algorithms in terms of network cost and unavailability caused by cable breakdown is proposed. It can design the combination of star- and loop-shaped (where two diversified routes exist between a feeder point and central office) cable network. Furthermore, comparison with the conventional design method which simply applies star- or loop-shaped cable network is done in terms of economy and reliability on real access networks in the Tokyo metropolitan area. It is concluded that the proposed method can reduce the network cost further and realize a short unavailability value compared with the conventional method.