Circuit simulators are used to verify circuit functionality and to obtain detailed timing information before the expensive fabrication process takes place. They have become an essential CAD tool in an era of sub-micron technology. We have developed a new event-driven MOS circuit simulator to replace a direct method circuit simulator. In our simulator, partitioned subcircuits are analyzed by a direct method matrix solver, and these are controlled by an event-driven scheme to maintain accuracy. The key of this approach is how to manage events for circuit simulation. We introduced two types of events: self-control events for a subcircuit and prediction correcting events between subcircuits. They control simulation accuracy, and bring simulation efficiency through multi-rate behavior of a large scale circuit. The event-driven scheme also brings some useful functions which are not available from a direct method circuit simulator, such as a selected block simulation function and a batch simulation function for load variation. We simulated logic modules (buffer, adder, and counter) with about 1000 MOSFETs with our event-driven MOS circuit simulator. Our simulator was 5-7 times faster than a SPICE-like circuit simulator, while maintaining the less than 1% error accuracy. The selected block simulation function enables to shorten simulation time without losing any accuracy by selecting valid blocks in a circuit to simulate specified node waveforms. Using this function, the logic modules were simulated 13-28 times faster than the SPICE-like circuit simulator while maintaining the same accuracy.

This letter presents a new design method for approximate inverse systems using all-pass networks. The efficacy of approximate inverse systems for input and parameter estimation of nonminimum phase systems is well recognized. in the previous methods, only time domain design of FIR (finite impulse response) type approximate inverse systems were considered. Here, we demonstrate that IIR (infinite impulse response) type approximate inverse systems outperform the previous methods. A nonlinear optimization technique is adopted for designing the proposed system in the frequency domain. Numerical examples are also presented to show the effectiveness of the proposed method.

A learning algorithm is presented for nearest neighbor pattern classifiers for the cases where mixed supervised and unsupervised training data are given. The classification rule includes rejection of outlier patterns and fuzzy classification. This partially supervised learning problem is formulated as a multiobjective program which reduces to purely super-vised case when all training data are supervised or to the other extreme of fully unsupervised one when all data are unsupervised. The learning, i. e. the solution process of this program is performed with a gradient method for searching a saddle point of the Lagrange function of the program.

Existing edge detection methods provide unsatisfactory results when contrast changes largely within an image due to non-uniform illumination. Koch et al. developed an energy function based upon the Hopfield neural network, whose coefficients were fixed by trial and error, and remain constant for the entire image, irrespective of the differences in intensity level. This paper presents an improved edge detection method for non-uniformly illuminated images. We propose that the energy function coefficients for an image with inconsistent illumination should not remain fixed, rather should vary as a second-order function of the intensity differences between pixels, and actually use a schedule of changing coefficients. The results, compared with those of existing methods, suggest a better strategy for edge detection depending upon both the dynamic range of the original image pixel values as well as their contrast.

In general, a time-limited signal such as a single sinusoidal waveform framed by a frame period T can be utilized for conveying a multi-level symbol in data transmission. If such a signal is analyzed by the conventional DFT (Discrete Fourier Transform) analysis, the infinite number of frequency components with frequency spacing fD = T1 is needed. This limits the accuracy with which the original frequency of the unframed sinusoidal waverform can be identified. It is especially difficult to identify two similar framed sinusoids whose frequency spacing is narrower than fD. An analytical principle for time-limited signals is therefore proposed by introducing the concept of an Extended Frame into DFT. Waveform analysis more accurate than DFT is achieved by taking into account multiple correlations between extended frames made of an input frame signal and the element frequency components corresponding to the length of each extended frame. In this approach, it is possible to use arbitrary element frequency spacing less than fD. It also allows an element frequency to be selected as a real number times of fD, rather than as an integer times of fD that is used for DFT. With this analyzing mechanism, it is verified that an input frame signal with only the frequency components which coincide with any of the element frequencies can be exactly analyzed. The disturbance caused by the input white noise is examined. As a result, it is found that the superior noise suppression function is achieved by this method over a conventional matched filter. In addition, the error caused by using a finite number of element frequencies and the A/D conversion accuracy required for sampling an input signal are examined, and it is shown that these factors need not impede practical implementation. For this reason, this principle is useful for multi-ary transmission systems, noise tolerant receivers, or systems requiring precise filtering of time limited waveforms.

In this study, we discuss a discrete-time cellular neural network (DTCNN) and its applications including convergence property and stability. Two theorems about the convergence condition of nonreciprocal non-uniform DTCNNs are described, which cover those of reciprocal one as a special case. Thus, it can be applied to wide classes of image processings, such as associative memories, multiple visual patterns recognition and others. Our DTCNN realized by the software simulation can largely reduce the computational time compared to the continuous-time CNN.

The quality of Si substrates affecting the oxide reliability was investigated using various kinds of test structures like flat capacitor, field edge array and gate edge array. The field edge array test structure which resembles the conditions found for real device is shown to be quite effective to determine the quality of oxides. Oxide grown on a P type epitaxial layer on P+ silicon substrate shows the highest reliability in all test structures. Gettering of heavy metals and/or crystal defects by the P+ silicon substrate is the dominant mechanism for the improvement of the oxide reliability. H2 annealed silicon shows a good reliability if monitored using the flat capacitor. However, using the field edge array test structure, which is strongly influenced by real device process, the reliability of the oxide grown on H2 annealed silicon degrades.

A new methodology for simulation-based CMOS process design has been proposed, using a Hierarchical Response Surface Method (HRSM) and an efficient experimental calibration. The design methodology has been verified using a 0.4 micron CMOS process. The proposed HRSM achieved a 60% reduction of process and device design cost in comparison with those of conventional TCAD. The procedure was performed in conjunction with an experimental calibration technique to provide a reliable threshold voltage prediction including process variation effects. The total CPU cost was 200 hr. on SUN SPARC 10 and the error of the predicted threshold voltage was less than 0.02 V.

A simplified distribution base resistance model (SDM) is proposed to identify each component of the base resistance and determine the dominant. This model divides the parasitic base resistance into one straight path and two surrounding paths. It is clarified that the link base resistance is dominant in a short emitter and the surrounding polysilicon base electrode resistance is dominant in a long emitter. In the SDM, the distance of the link base is reduced to half; with metal silicide as the extrinsic base electrode, the base resistance will be reduced to 75%.

An 8-to 10-bit CMOS A/D converter with a conversion rate of more than 16 megasample/second is required in consumer video systems. Subranging architecture is widely used to realize such A/D converters. This architecture, however, exhibits an reference voltage error caused by resistor ladder loadings. The error has been discussed with respect to a flash A/D converter by Dingwall. However, it can not be applied for a subranging A/D converter as it is. The analysis of this error is very important in realizing the desired accuracy of a subranging A/D converter. This paper describes a static analysis to improve the linearity, and reports the results of this analysis for two typical types, one with invividual comparator arrays for coarse and fine A/D conversions, and the other with the same comparator array for both conversions. This analysis makes it clear that a subranging A/D converter has unique saw-tooth characteristic in fine linearity errors. Furthermore, this analysis clarifies what conditions are necessary to achieve the desired accuracy. It is necessary, for example, that the product of the total input capacitance of the comparators C, the conversion rate fs and the total ladder resistance R is less than 0.03 in A/D converters with individual comparator arrays and 0.016 in A/D converters with the same comparator array in order to achieve 10-bit accuracy.

This paper proposes an integrated interference suppression scheme which realizes interference-resistant satellite digital signal transmission systems. It employs a notch filter in the receiving side to suppress the co-channel interference (CCI) signal. Moreover, the proposed scheme employs an adaptive equalizer combined with a forward error correction (FEC) scheme to improve the Pe (probability of error) performance degradation due to the inter-symbol interference caused by notch filtering of the desired signal. In the typical frequency modulation (FM) CCI environment with a BWi/FN of 2.3 (BWi: interference signal required bandwidth, fN: one half the Nyquist bandwidth of the desired signal), a Δf / fN of 1.05 (Δf: interference frequency offset) and a D/U of 3 dB (desired to undesired (interference) signal power ratio), the proposed scheme improves the required Eb/NO by 1.5 dB at a Pe of 10-4 compared to that without an adaptive equalizer.

This paper introduces a new image representation method that is named the projective image representation (PIR). We consider an image as a collage of symmetric segments each of which can be well represented by its projection data of a single orientation. A quadtree-based method is adopted to decompose an image into variable sized segments according to the complexity within it. Also, we deal with the application of the PIR to the image compression and propose an efficient algorithm, the quadtree-structured projection vector quantization (QTPVQ) which combines the PIR with the VQ. As the VQ is carried out on the projection data instead of the pixel intensities of the segment, the QTPVQ successfully overcomes the drawbacks of the conventional VQ algorithms such as the blocking artifact and the difficulty in manipulating the large dimension. Above all, the QTPVQ improves the subjective quality greatly, especially at low bit rate, which makes it applicable to low bit rate image coding.

A novel circuit design technique for realizing a linear CMOS transconductance element, consisting of an adaptively biased source-coupled differential pair using a quadritail cell, is proposed. In the circuitry, the quadritail cell, which provides an output current proportional to the square of a differential input voltage, cancels a nonlinear term of the source-coupled differential pair. The circuit have a superior linearity and a wide linear input voltage range compared with the conventional linear CMOS transconductance elements because the transconductance characteristic is theoretically linear over wide input voltage range when all the MOS field-effect transistors (MOSFETs) are operating in the saturation region and the MOSFETs' behaviors are according to the relation based on the square-law characteristic. The proposed adaptively biased source-coupled differential pair was verified by using transistorarrays and discrete components on a breadboard.

Shortened prime codes (SPR-codes) are presented, which can maintain the fixed code weight for any arbitrary number of codewords while still preserve the same cross and auto-correlation constraints as original prime codes. The use of SPR-codes can reduce both cost and power loss of optical encoders/decoders. Tunable all-optical SPR-code encoders are also designed, which are based on rapidly tunable optical delay lines. It is shown that using this type of encoders not only can further reduce the coding power loss, but also can achieve a very cost-effective fashion.

The degradation of I-V characteristics under constant emitter-base reverse voltage stress in advanced self-aligned bipolar transistors was analyzed. Experimental analyses have been taken the stress field effect into account when predicting hot-carrier degradation. These analyses showed that base current starts to increase when the reverse voltage stress is about 3 V. The dependence of the base current change on reverse voltages of more than 3 V was also investigated experimentally, and equations expressing hot-carrier degradation in terms of the exponential dependence of excess base current on both reverse stress voltage and stress-enhancing voltage related to emitter-base breakdown voltage were derived.

In this paper, we give a direct proof of the result of Latteux and Turakainen that the full class of recursively enumerable languages can be obtained from minimal linear languages (which are generated by linear context-free grammars with only one nonterminal symbol) by Dyck reductions (which reduce pairs of parentheses to the empty word).

In this article, a new multiplication type D/A conversion system using CCD is proposed and the result of simulations for evaluating its performance is reported. The system consists of a recursive charge divider which divides input charge-packet Qin sequentially into output charge-packets Qin2-i and two charge-packet accumulators which accumulates output charge-packets from the recursive divider selectively according to digital input signal bits atarting from MSB. The system converts input digital signal bit by bit, fully in chargedomain, thus the power consumption for this system is supposed to be very low. Also in this article, an effective method to achieve higher accuracy for splitting a charge-packet into two equal-sized packets using very simple hard-ware structure is proposed. As the result of simulations, we have found that the upper limit of accuracy for the conversion is determined by transfer efficiency of CCD, and within this range a trade-off relationship exists among conversion-accuracy, circuit-size and conversion-rate. This unique relationship enables to reduce the circuit size of D/A converter significantly maintaining the accuracy of conversion by slowing down the conversion-rate. This D/A converter is appropriate especially for the system integration because of its simple structure, tolerance to the fabrication error and low power consumption inherrent in the nature of CCD. By using of this system, it is expected to be possible to realize a focal plane image processor performing parallel analog operations such as DCT conversion with CCD imager incorporated on the same Si chip by the same MOS process technology.

A direct gradient descent learning algorithm of energy function in Hopfield neural networks is proposed. The gradient descent learning is not performed on usual error functions, but the Hopfield energy functions directly. We demonstrate the algorithm by testing it on an analog-to-digital conversion and an associative memory problems.

This paper describes the new analog-digital merged circuit architecture which utilizes the pulse modulation signals. By reconsidering the information representing and processing principles, and the circuit operations governed by the physical law, the new circuit architecture is proposed to overcome the limitations of existent VLSI technologies. The proposed architecture utilizes the pulse width modulation (PWM) signal which has analog information in the time domain, and be constructed with the novel PWM circuits which carry out the multi-input arithmetic operations, the signal conversions and the data storage. It has a potential to exploit the high speed switching capability of deep sub-µm devices, and to reduce the number of devices and the power dissipation to one-tenth of those of the binary digital circuits. Therefore it will effectively implement the intelligent processing systems utilizing 0.5-0.2µm scaled CMOS devices.

This paper reviews an application of optical techniques to Microwave Signal Processing (MSP), such as frequency multiplexing using external optical modulators (EOMs), and microwave frequency add-drop multiplexing and mixing using semisconductor optical amplifiers (SOAs), as well as microwave phase control in the optical domain. The cascaded EOM links can be applied to microwave and millimeter-wave signal distribution networks. The add-drop links using SOAs can make it possible to realize a compact and cost-effective radio repeater for radio signal distribution. The several SOA mixing link configurations are also described.