This paper describes the design of a high-speed 4-2 compressor for fast multipliers. Through the survey of the six kinds of representative conventional 4-2 compressor (RBA 1-3 and NBA 1-3) in both the redundant binary (RB) and the normal binary (NB) scheme, we extracted two problems that degrades the operating speed. The first is the use of multi-input complex gates and the second is the existence of transmission gates (TG) at the input and/or output stages. To solve these problems, we propose high-speed 4-2 compressors using the RB scheme, which we call the high-speed redundant binary adders (HSRBAs). Six kinds of HSRBAs, HSRBA 1-6, were derived by making the Boolean equations suitable for high-speed CMOS circuits. Among them, HSRBA2, HSRBA4 and HSRBA6 have no multi-input complex gate and input/output TG, and perform at a delay time of 0.89 ns which is the fastest of all 4-2 compressors. We investigated the logical relation between HSRBAs and conventional 4-2 compressors by analyzing the Boolean equations for each circuit. This investigation shows that all the conventional redundant binary adders RBA1-3 have the same logic structures as HSRBA2. We also showed the conventional normal binary adders NBA1-3 have the same logic structures as HSRBA1, HSRBA3 and HSRBA5, respectively. This implies all 4-2 compressors can be derived from the same equation regardless of RB or NB. We applied the HSRBA2 to a 5454-bit multiplier using 0.5-µm CMOS technology. The multiplication time at the supply voltage of 3.3 V was 8.8 ns. This is the fastest 5454-bit multiplier with 0.5-µm CMOS so far, and 83% of the speed improvement is due to the high speed 4-2 compressor.

Discussed here is progress achieved in the development of video codec LSIs.First, the amount of computation for various standards, and signal handling capability (throughput) and power dissipation for video codec LSIs are described. Then, general technologies for improving throughtput are briefly summarized. The paper also reviews three approaches (i.e., video signal processor, building block and monolithic codes) for implementing video codes standards. The second half of the paper discusses various high-throughput technologies developed for programmable Video Signal Processor (VSP) LSIs. A number of VSP LSIs are introduced, including the world's first programmable VSP, developed in February 1987 and a monolithic codec ship, built in February 1993 that is sufficient in itself for the construction of a video encoder for encoding full-CIF data at 30 frames per second. Technologies for reduction of power dissipation while keeping maintaining throughput are also discussed.

A single chip MPEG2 MP@HL Video decoder has been developed, which consists mainly of specific functional units and macroblock level pipeline buffers. A new organization is also devised for a set of off-chip frame memories and the interfaces associated with it. Owing to sophisticated I/O interfaces among functional units, the macroblock level pipeline in conjunction with different decording facilities attains a high throughput to such an extent as to decode HDTV images in real time. Moreover, a set of these functional units, pipeline buffers, and frame memory interfaces, together with a sequence controller, is integrated for the first time in a single chip, which has the total area of 8.8 9.2mm2 with a 0.6µm triple-mental CMOS technology, and dissipates 1.2 W from a single 3.3 V supply.

This paper overviews fiber-oriented wireless communication systems, particularly in the area of microcell systems. The benefits of fiber-oriented wireless systems are discussed focusing on an application board scheme to facilitate new service deployment in light of intelligent networks. Dynamic range improvement technologies to remove interference are highlighted. Overall system performance is calculated for an economical FP-LD. Furthermore, effective modem use and a potential diversity technique are introduced. This strategy will play a role in realizing flexible fiber-optic subscriber networks.

Air interfaces of the future mobile communication are widely spreading, because of the multimedia service demands, technology trends and radio propagation conditions. Radio-Highway Networks are expected to realize the universal, seamless and multi-air-interface capability for mobile access networks, and play an important role in the future multimedia radio communications. For the radio-highway networks, this paper newly proposes natural bandpass sampling - asynchronous time division multiple access (NBS-ATDMA) method, where radio signals are natural bandpass sampled at the radio base station and are asynchronously multiplexed on the optic fiber bus link and intelligently transmitted to its desired radio control station. We theoretically analyze the loss probability of the radio signal due to collision in the network and the carrier-to-noise power ratio of received radio signals at the radio control station. Moreover, in order to reduce the loss probability, two access control methods, carrier sense and pulse width control, are proposed, and it is clarified that these improve the number of base station connected to radio highway networks.

This paper proposes an adaptive modulation system with a punctured convolutional code for land mobile communications to achieve high quality, high bit rate, and high spectral efficient data transmission in multipath fading environments. The proposed system adaptively controls the coding rate of the punctured convolutional code, symbol rate, and modulation level according to the instantaneous fading channel conditions. During good channel conditions, the modulation parameters are selected to increase the transmission rate as much as possible with satisfying a certain transmission quality. As channel conditions become worse, lower rate modulation parameters are applied or transmission is stopped. The performances in fading environments are evaluated theoretically and by computer simulations. The results show that the proposed system can realize higher quality transmission without the degradation in average bit rate compared to conventional adaptive modulation systems.

This paper proposes a new method to design an optimal pipelined instructions set processor for ASIP development using a formal HW/SW codesign methodology. First, a HW/SW partioning algorithm for selecting an optimal pipelined architecture is outlined. Then, an adaptive detabase approach is presented that enables to enhance the optimality of the design through very accurate estimation of the performance of a pipelined ASIP in the HW/SW partitioning process. The experimental results show that the proposed method is effective and efficient.

In order to pave the way to B-ISDN, one of the most important issues for network providers is to identify the most efficient B-ISDN introduction strategy. This paper focuses on the costs of introducing ATM transmission systems into backbone transport networks which must provide highly reliable broad band transmission capability. In this context, the main rival to ATM is Synchronous Transfer Mode (STM); recent Synchronous Digital Hierarchy (SDH) equipment supports the establishment of advanced STM-based high speed transport networks. This paper offers a cost comparison of ATM and STM based backbone transport networks. A digital path network in STM has a hierarchical structure determined by the hierarchical multiplexing scheme employed. The minimum cost STM path network can only be determined by developing a path design method that considers all hierarchical path levels and yields the optimum balance of link cost and node cost. Virtual paths have desirable features such as non-deterministic path bandwidth and non-hierarchical and direct multiplexing capability into high speed optical transmission links. These features make it possible to implement a non-hierarchical VP network with ATM cross connect systems which can handle any bandwidth VP with a universal cell switching function. This paper shows that the non-hierarchical VP routing, which strongly minimizes link cost, can be implemented without significantly increasing node cost. Network design simulations show that the virtual path scheme, possible only in an ATM network, yields the most cost effective path network configuration.

A unified process flow management system (UPFMS) that combines a CIM system, process/device simulator, CAD system, and manufacturing line schedular has been developed. This new system uses a new language called PDL to describe the process flow as common information for all systems. The UPFMS consists of the flow edit section, the flow inspection section, and several types of interface programs to make it suitable for use with other systems. The process flow data described using the PDL in the UPFMS provides data for controlling lots in CIM system. If modification of the process flow data in the CIM system is required, the process flow data is returned to the UPFMS and modified with inspection using a knowledge data base. Then, the error-free process flow data is sent back to the CIM system for Processes after flow inspection. Moreover, the UPFMS, with the new language PDL, generates recipe data for the equipment using an interface program, and recipe data is input to several types of equipment. Furthermore, the PDL process flow data can also be used as input data for the manufacturing line scheduler using another interface program. Mask and layout data in a CAD system can be exchanged among process/device simulators by using the UPFMS, and thus two-dimensional device characteristics. Spice paramenters can be also to be created. The UPFMS combines with CIM system, process/device simulator, CAD system, and the manufacturing line scheduler using common information, PDL. The process flow data created in the UPFMS can be used to control all systems from the simulation to CIM system as common data.

High-performance ULSI devices require ultraclean silicon surfaces, the complete removal of native oxides, and atomic level flatness and stabilization of the cleaned surfaces against molecular contaminants. Dry cleaning techniques are an attractive alternative to conventional wet processing for future ULSI production using cluster chambers or multi-process cham-bers. Organic contaminants, including photoresist polymers, are effectively removed by photo-excited ozone cleaning. We have found photo-excited halogen radicals to be useful for removing trace metals and native oxides from silicon surfaces without damaging on silicon and silicon-dioxide surfaces. We success-fully terminated hydrogen on (100) silicon surfaces by annealing in pure hydrogen ambient. A dry cleaning system with these sequential processes will be useful in constructing fully-integrated mass-production lines of high-performance ULSI devices.

A detabase system that provides step-by-step guidance for LSI failure analysts has been developed. This system has three main functions: database, navigator, and chip tracking. The datebase stores failure analysis information such as analysis method and failure mechanisms including image data. It also stores conditions and results of each analysis step and decisions to proceeds to the next analysis step. With 2000 failure analysis cases, data retrieval takes 6.6 seconds, a table containing 20 photos is presented in 6.5 seconds, and a different set of data can be displayed in 0.6 seconds. The navigator displays a standard analysis procedure illustrated in flow charts.The chip tracking shows where the particular chip is and what analysis it is undergoing, which is useful for the situation where many chips are simultaneously analyzed. Thus, this system has good enough functions of analysis procedure management and performance of quick data access to make failure analysis easier and more successful.

Multiple TDMA bursts assignment between a base station and a personal terminal will be required for multimedia communications that offers high speed signal transmission such as voice and data simultaneous transmission. This paper proposes a reliable packet transmission method for TDMA based wireless multimedia communications. The proposed method employs an adaptive transmission rate control according to the packet length and a burst diversity technique is applied to improve the frame error rate of a packet. The frame error rate performance has been approximated theoretically by using fade- and infade-duration statistics of a Rayleigh fading channel and a computer simulation has been carried out for two control channels, FACCH/SACCH (Fast/Slow Associated Control CHannel) in the PHS as well as GSM. Both results indicate that the frame error rate is dramatically improved, about one order, when two bursts have different frequency and improved by about 25% when the two bursts have the same frequency.

The realization of scientific manufacturing of ULSIs in the 21st century will require the development of a technical infrastructure of "Ultra Clean Technology" and the firm establishment of the three principles of high performance processes. Three principles are 1)Ultra Clean Si Wafer Surface, 2)Ultra Clean Processing Environment, and 3)Perfect Parameter controlled process. This paper describes the methods of resolving the problems inherent in Ultra Clean Technology, taking as examples issues in quarter-micron or more advanced semiconductor process and manufacturing equipment, particularly when faced with the challenges of plasma dry etching. Issues indispensable to the development of tomorrow's highly accurate and reliable plasma dry etching equipment are the development of technologies for the accurate measurement of plasma parameters, ultra clean gas delivery systems, chamber cleaning technology on an in-situ basis, and simulating the plasma chemistry.This paper also discusses the standardization of semiconductor manufacturing equipment, which is considered one of the ways to reduce the steep rise in production line construction costs. The establishment of Ultra Clean Technology also plays a vital role in this regard.

In this paper, we study three-dimensional motion estimation using optical flow. We construct a weighted quotient-form objective function that provides an unbiased estimator. Using this objective function with a certain projection operator as a weight drastically reduces the computational cost for estimation compared with using the maximum likelihood estimator. To reduce the variance of the estimator, we examine the weight, and we show by theoretical evaluations and simulations that, with an appropriate projection function, and when the noise variance is not too small, this objective function provides an estimator whose variance is smaller than that of the maximum likelihood estimator. The use of this projection is based on the knowledge that the depth function has a positive value (i. e., the object is in front of the camera) and that it is generally smooth.

A new matched-filter (MF) acquisition scheme with adaptive threshold is proposed for a frequency-hopped/spread-spectrum multiple-access (FH/SSMA) system. Detection and false alarm probabilities are derived for combined interference environments. The combined interference consists of partialband noise jamming or tone jamming, multiple access interference (MAI), multipath interference, and thermal noise. We use Gaussian approximation for modeling the MAI and multipath interference. Equal power assumption of the users is employed which is typically used in the SSMA system analysis. In the proposed scheme, MF output is compared to an adaptive threshold determined by the number of jammed frequency slots. It is shown that the proposed adaptive-threshold acquisition scheme achieves higher detection probability and lower false alarm probability than a conventional fixed-threshold scheme for each jammed fractional bandwidth, JSR, the number of multipaths, and the number of users. It is also shown that adaptive threshold achieves faster acquisition and higher packet throughput than fixed threshold in application to FH/SSMA packet radio system.

The dynamic channel assignment (DCA) strategy proposed here uses information on the mobile station speed and direction of motion to reduce the number of forced call terminations and channel changes in micro cellular systems. This SMD (speed and moving direction) strategy is compared with the main DCA strategies by simulating a one-dimensional service area covering a road on which there are high-speed mobile stations (HSMSs) and low-speed mobile stations (LSMSs).The simulation results show that the SMD strategy has the best performance in terms of forced call termination and channel change. The performance difference between the SMD strategy and the other DCA strategies increases as cell size decreases and as HSMS speed increases. While the SMD strategy does not yield the best total call blocking rate, its total carried load is the best when cells are small and HSMS speed is high. Also, the SMD performance improves when the HSMS offered load is small and the LSMS offered load is large. Although the SMD strategy requires information on the speed and direction of each mobile station and it increases call blockings somewhat, it reduces the number of forced call terminations and channel changes considerably, which is important in micro cellular systems.

This paper proposes a novel mobile communications system of integrating microcell and macrocell for future land mobile communications which allows the user to enjoy mobile communications services by using one terminal regardless of his terminal speed. Current and developing digital land mobile communications systems are classified into two categories according to their differences in cell size, operating environments, service requirements and terminal speeds. One is a microcell system offering cordless telephone services for the user moving at low speeds and the other is a macrocell system offering vehicle telephone services for the user moving at high speeds. In order to access these two systems, the user needs to have two different terminals and to use an appropriate one according to the operating environments, service requirements and terminal speeds. In this paper, we propose a land mobile communications system in which the user can place a call without any of the inconvenienced described above. The proposed system consists of multi layered composite microcell system with no handover areas, each layer being composed of a number of microcells. This paper presents the detailed structure of this system and evaluates the performances of the channel capacity and the frequency of handovers during a call based on computer simulation results.

A microphone array system with multi-stage processing for speech enhancement is presented in this paper. Two beamformers with uniform directional patterns, one aimed at the target source and the other at the interfering sources, convert the multi-channel inputs into two data sequences. A novel microphone array structure with a small aperture has been designed to obtain the dual beamformers. The outputs of the two beam-formers are then presented to a post-processing stage to further improve the quality and intelligibility of the speech signal. The post-processing stage can be selected from one of three different algorithms that are presented, which are suitable for different acoustic environments. Applications for such a system include hands-free telephony, teleconferencing and also special situations where speech signals must be picked up in an extremely noisy acoustic environment in which the microphones are hidden (e.g. in a forensic covert recording system).

In this paper, we show a collusion attack on the novel and sophisticated ID-based non-interactive key sharing scheme proposed by Tanaka [2], [3]. It is based on a linear algebraic approach [4]. We discuss its complexity and provide numerical simulation results of the success probability in forging the shared keys.

In order to reduce the ever increasing cost for ULSI manufacturing due to the complexity of integrated circuits, dramatic simplification in the logic LSI architecture as well as the very flexible circuit configuration have been achieved using a highfunctionality device neuron-MOSFET (γMOS).In γMOS logic circuits, however, computations based on the multiple-valued logic is the key for enhancing the functionality. Therefore, much higher accuracy of processing is required. After brief description of the operational principle of γMOS logic, the relationship between the number of multiple logic levels and the functionality enhancement is discussed for further enhancing the functionality of γMOS logic circuits by increasing the number of multiple logic levels, and the accuracy requirements for the manufacturing processes are studied. The order of a few percent accuracy is required for all principal device structural parameters when it is aimed to handle 50-level multiple-valued variable in the γMOS logic circuit.